CN110233805A - Switch, the system and method for variable cell - Google Patents
Switch, the system and method for variable cell Download PDFInfo
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- CN110233805A CN110233805A CN201910589070.8A CN201910589070A CN110233805A CN 110233805 A CN110233805 A CN 110233805A CN 201910589070 A CN201910589070 A CN 201910589070A CN 110233805 A CN110233805 A CN 110233805A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/101—Packet switching elements characterised by the switching fabric construction using crossbar or matrix
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3018—Input queuing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3027—Output queuing
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/30—Peripheral units, e.g. input or output ports
- H04L49/3072—Packet splitting
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/90—Buffering arrangements
- H04L49/9057—Arrangements for supporting packet reassembly or resequencing
Abstract
The present invention provides switch, the system and methods of a kind of variable cell；Wherein, the cutting module in the device is connect with input equipment；Recombination module is connect with output equipment；Cutting module carries out cutting to the pending data packet that input equipment is sent according to preset cell length, generates cell to be processed；Cell to be processed includes standard cell and tail cell；Switching Module determines dispatching cycle according to the standard cell head or tail header of cell to be processed；According to dispatching cycle and preset arbitrated logic, cell to be processed is cached and transmitted；Recombination module receives the cell to be processed that Switching Module is sent, and according to standard header and tail header, recombinates to cell to be processed, obtain reorganizing packets, reorganizing packets are sent to output equipment.The present invention is transmitted with elongated cell, is adjusted dispatching cycle according to the cell of different length in transmission process, is improved efficiency of transmission, reduce cache management difficulty.
Description
Technical field
The present invention relates to network communication technology fields, more particularly, to switch, system and the side of a kind of variable cell
Method.
Background technique
Switching fabric is the core component of the communication equipments such as router, interchanger, and basic function is exactly to complete equipment input
The data forwarding of port and specific output exit port.Currently, the CrossBar switching fabric application based on crossover node band caching
When the switching equipment that the data frame lengths such as Ethernet, FC change greatly, generallys use fixed length cell structure and data frame is carried out
Cutting；Using shorter cell as the minimum unit of transfer management, lesser storage cell can be reduced to each node of CrossBar
The size requirement of caching, and improve the service efficiency of caching；In addition, cell transmission also has many advantages, such as that scheduling is balanced.
In actual operation, fixed length cutting can fill out cell in data frame curtailment cell length to be slit
The transmission filled, and fill data occupies bus bandwidth, reduces efficiency of transmission；Or (such as meet destination port to feature is identical
The conditions such as consistent with priority) data frame first integrated and carry out cutting again, in this way in data frame curtailment letter to be slit
It when first length, is filled with the data of next frame, leads in single cell that there are the data of multiple data frames, the positions of frame head
It is uncertain, increase the management difficulty of caching.
Summary of the invention
In view of this, the purpose of the present invention is to provide switch, the system and method for a kind of variable cell, to improve
Efficiency of transmission, and reduce cache management difficulty.
In a first aspect, the device includes being sequentially connected the embodiment of the invention provides a kind of switch of variable cell
Cutting module, Switching Module and recombination module；Cutting module is connect with input equipment；Recombination module is connect with output equipment；
Cutting module is used to carry out cutting to the pending data packet that input equipment is sent according to preset cell length, generates to be processed
Cell；Cell to be processed includes standard cell and tail cell；Standard cell includes standard cell load and standard header；Tail letter
Member includes tail cell load and tail header；The length of tail cell load is less than or equal to the length of standard cell；Switching Module
For the standard cell head or tail header according to cell to be processed, dispatching cycle is determined；According to dispatching cycle and preset secondary
Logic is cut out, cell to be processed is cached and transmitted；Recombination module is used to receive the cell to be processed of Switching Module transmission, and
According to standard header and tail header, cell to be processed is recombinated, reorganizing packets are obtained, reorganizing packets are sent
To output equipment.
With reference to first aspect, the embodiment of the invention provides the first possible embodiments of first aspect, wherein on
Stating cutting module includes sequentially connected cutting module, header generation unit and encapsulation unit；Cutting module is used for according to pre-
If cell length to data packet to be processed carry out cutting, obtain standard cell load and tail cell load；Header generates single
Member generates standard header and tail header for obtaining the parameter of standard cell load and tail cell load；Standard header
Priority, destination port and cell length including standard cell load；Tail header includes the priority of tail cell, destination
Mouth, cell length and the instruction of tail cell；Encapsulation unit is marked for being packaged to standard header and standard cell load
Definite message or answer member；Tail header and tail cell load are packaged, tail cell is obtained.
The possible embodiment of with reference to first aspect the first, the embodiment of the invention provides second of first aspect
Possible embodiment, wherein the structure that above-mentioned Switching Module is based on corsspoint switch matrix (Crossbar) is established；Switching Module
The intersection cache device of input buffer and the second quantity including the first quantity；The numerical value of second quantity is equal to the first quantity
Square of numerical value；Input buffer and intersection cache device are connected according to the structure of corsspoint switch matrix；Input buffer with cut
Sub-module connection；Intersection cache device is connect with recombination module.
The possible embodiment of second with reference to first aspect, the embodiment of the invention provides the third of first aspect
Possible embodiment, wherein above-mentioned input buffer includes that input-buffer administrative unit, input-buffer unit and control are single
Member；Input-buffer unit includes the input-buffer subspace for setting quantity and being sized；Input-buffer administrative unit, input are slow
Memory cell is connect two-by-two with control unit；Input-buffer administrative unit is used to delay for standard cell load or tail cell load distribution
Deposit address number；Input-buffer unit is used to for standard cell load or tail cell load to be stored in buffer address number corresponding
In input-buffer subspace；Control unit is used for according to the current corresponding standard cell head or tail header of cell to be processed,
Determine the cell length of cell to be processed；According to cell length, dispatching cycle is determined；According to dispatching cycle, virtual output queue
The system information elements transmission state of (VoQ, Virtual Output Queue) mechanism and intersection cache device feedback, it is secondary to generate first
Cut out result；It is numbered according to arbitration result and buffer address, reads standard cell load or tail cell load, and by cell to be processed
It is transmitted in intersection cache device.
The third possible embodiment with reference to first aspect, the embodiment of the invention provides the 4th kind of first aspect
Possible embodiment, wherein above-mentioned recombination module includes that recombination memory management unit, recombination cache unit and control recombination are single
Member；Recombination cache unit includes setting quantity and the recombination being sized caching subspace；One recombination caching subspace is corresponding
One buffer address number；Memory management unit is recombinated to be used to compile for standard cell load or tail cell load distribution buffer address
Number；Recombination cache unit is used to for standard cell load or tail cell load being stored in buffer address and numbers corresponding recombination caching
In subspace；Recomposition unit is controlled to be used to read caching according to preset recombination control rule, standard header and tail header
Standard cell load and tail cell load in address number corresponding recombination caching subspace, believe standard cell load and tail
First load is recombinated, and reorganizing packets are obtained.
Second aspect, the embodiment of the present invention also provide a kind of exchange system of variable cell, including input equipment, output are set
The switch of standby and above-mentioned variable cell.
The third aspect, the embodiment of the present invention also provide a kind of exchange method of variable cell, this method be applied to it is above-mentioned can
Become the switch of cell；This method comprises: cutting module input equipment is sent according to preset cell length it is to be processed
Data packet carries out cutting, generates cell to be processed；Cell to be processed includes standard cell and tail cell；Standard cell includes standard
Cell load and standard header；Tail cell includes tail cell load and tail header；The length of tail cell load is less than or waits
In the length of standard cell；Switching Module determines dispatching cycle according to the standard cell head or tail header of cell to be processed；Root
According to dispatching cycle and preset arbitrated logic, cell to be processed is cached and transmitted；Recombination module receives Switching Module hair
The cell to be processed sent, and according to standard header and tail header, cell to be processed is recombinated, recombination data is obtained
Reorganizing packets are sent to output equipment by packet.
In conjunction with the third aspect, the embodiment of the invention provides the first possible embodiments of the third aspect, wherein on
Stating cutting module includes sequentially connected cutting module, header generation unit and encapsulation unit；According to preset cell length
Cutting is carried out to the pending data packet that input equipment is sent, generates cell to be processed, comprising: dividing die root tuber is according to preset letter
First length carries out cutting to data packet to be processed, obtains standard cell load and tail cell load；Header generation unit obtains
The parameter of standard cell load and tail cell load generates standard header and tail header；Standard header includes standard letter
Priority, destination port and the cell length of first load；Tail header includes that the priority of tail cell, destination port, cell are long
Degree and the instruction of tail cell；Encapsulation unit is packaged standard header and standard cell load, obtains standard cell；Tail is believed
First head and tail cell load are packaged, and obtain tail cell.
The first possible embodiment in conjunction with the third aspect, second the embodiment of the invention provides the third aspect can
The embodiment of energy, wherein above-mentioned Switching Module is established based on the structure of corsspoint switch matrix；Switching Module includes the first quantity
Input buffer and the second quantity intersection cache device；The numerical value of second quantity is equal to square of the numerical value of the first quantity；
Input buffer and intersection cache device are connected according to the structure of corsspoint switch matrix；Input buffer is connect with cutting module；
Intersection cache device is connect with recombination module.
In conjunction with second of the third aspect possible embodiment, the third the embodiment of the invention provides the third aspect can
The embodiment of energy, wherein above-mentioned input buffer includes input-buffer administrative unit, input-buffer unit and control unit；
Input-buffer unit includes the input-buffer subspace for setting quantity；The corresponding buffer address in one input-buffer subspace is compiled
Number；Input-buffer administrative unit, input-buffer unit are connect two-by-two with control unit；The above method further include: input-buffer pipe
Managing unit is that standard cell load or tail cell load distribution buffer address are numbered；Input-buffer unit by standard cell load or
Tail cell load is stored in buffer address and numbers in corresponding input-buffer subspace；Control unit is according to current letter to be processed
The corresponding standard cell head or tail header of member, determines the cell length of cell to be processed；According to cell length, scheduling week is determined
Phase；According to the system information elements transmission state that dispatching cycle, virtual output queue mechanism and intersection cache device are fed back, first is generated
Arbitration result；It is numbered according to arbitration result and buffer address, reads standard cell load or tail cell load, and by letter to be processed
Member is transmitted in intersection cache device.
The embodiment of the present invention brings following the utility model has the advantages that the embodiment of the invention provides a kind of exchange of variable cell dresses
It sets, system and method；Cutting module carries out cutting to the pending data packet that input equipment is sent according to preset cell length,
Generate cell to be processed；Cell to be processed includes standard cell and tail cell；Switching Module is believed according to the standard of cell to be processed
First head or tail header, determines dispatching cycle；According to dispatching cycle and preset arbitrated logic, cell to be processed is cached
And transmission；Recombination module receives the cell to be processed that Switching Module is sent, and according to standard header and tail header, treats place
Reason cell is recombinated, and obtains reorganizing packets, reorganizing packets are sent to output equipment.Which is with the progress of elongated cell
Transmission, and dispatching cycle is adjusted according to the cell of different length in transmission process, efficiency of transmission is improved, and reduce caching
Management difficulty.
Other features and advantages of the present invention will illustrate in the following description, alternatively, Partial Feature and advantage can be with
Deduce from specification or unambiguously determine, or by implementing above-mentioned technology of the invention it can be learnt that.
To enable the above objects, features and advantages of the present invention to be clearer and more comprehensible, better embodiment is cited below particularly, and match
Appended attached drawing is closed, is described in detail below.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 is a kind of structural schematic diagram of the switch of variable cell provided in an embodiment of the present invention；
Fig. 2 is a kind of structural schematic diagram of cutting module provided in an embodiment of the present invention；
Fig. 3 is a kind of structural schematic diagram of recombination module provided in an embodiment of the present invention；
Fig. 4 is the data flow signal for the packet switching construction that a kind of length provided in an embodiment of the present invention can be changed cell
Figure；
Fig. 5 is the structural schematic diagram for the packet switching construction that a kind of length provided in an embodiment of the present invention can be changed cell；
Fig. 6 is the signal flow schematic diagram of Input Buffer module provided in an embodiment of the present invention during the work time；
Fig. 7 is the structural representation of CrossPoint Buffer node (intersection cache device) provided in an embodiment of the present invention
Figure；
Fig. 8 is the structural schematic diagram of Packet Assemble module provided in an embodiment of the present invention；
Fig. 9 is a kind of structural schematic diagram of the exchange system of variable cell provided in an embodiment of the present invention；
Figure 10 is a kind of flow diagram of the exchange method of variable cell provided in an embodiment of the present invention.
Specific embodiment
Technical solution of the present invention is clearly and completely described below in conjunction with embodiment, it is clear that described reality
Applying example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, the common skill in this field
Art personnel every other embodiment obtained without making creative work belongs to the model that the present invention protects
It encloses.
Existing switching fabric is mostly based on the CrossBar of crossover node band caching and establishes；Crossover node band caching
CrossBar is that 20 generation propose a kind of switching fabric the eighties, it is by creating virtual output queue (Virtual in input side
Output Queueing, VOQ) mechanism eliminate head obstruction (Head of Line Blocking) phenomenon, and by
CrossBar, which intersects, places a small amount of caching on crossover node, realize the isolation for outputting and inputting scheduling, reduce answering for scheduling
It is miscellaneous to spend the continuous productive process, it can be achieved that high speed.It is currently using this switching fabric in many mature commercial chips.
It is changed greatly when the CrossBar switching fabric of crossover node band caching is applied to the data frame lengths such as Ethernet, FC
Switching equipment when, data frame is usually split as cell, it is lesser using shorter cell as the minimum unit of transfer management
Storage cell can reduce the size requirement to each nodal cache of CrossBar, and improve the service efficiency of caching；In addition, cell passes
It is defeated also to have the advantages that dispatch equilibrium etc..
The existing CrossBar switching fabric based on cell generallys use fixed length cell structure, there is a problem of following:
1, fixed length cutting can be filled cell in data frame curtailment cell length to be slit, and filler
According to transmission occupy bus bandwidth, reduce efficiency of transmission.
2, the information of cell would generally be added in cell as header, increase cell transmission loss, and increase
Buffer memory capacity demand.
To solve the problems, such as that cell is filled, A designer person proposes prioritization scheme, i.e., identical to feature (such as meet mesh
The conditions such as port is consistent with priority) data frame first integrated and carry out cutting again, in this way in data frame length to be slit
It when insufficient cell length, is filled with the data of next frame, avoids the meaningless loss of bus bandwidth.But this solution party
For case there is also there are the data of multiple data frames in certain problem, such as single cell, the position of frame head is uncertain, increases slow
The management difficulty deposited；The partial data of next frame is read simultaneously because not can avoid when group packet, processing is bad to will affect tune
The flexibility of degree.
Based on this, the embodiment of the invention provides switch, the system and methods of a kind of variable cell, can be applied to
In the communication equipments such as router, interchanger.
For the exchange convenient for understanding the present embodiment, first to a kind of variable cell disclosed in the embodiment of the present invention
Device describes in detail.
A kind of structural schematic diagram of the switch of variable cell shown in Figure 1, which includes sequentially connected
Cutting module 10, Switching Module 20 and recombination module 30；Cutting module is connect with input equipment；Recombination module and output equipment connect
It connects.The pending data packet that cutting module is used to send input equipment according to preset cell length carries out cutting, generation to
Handle cell；Cell to be processed includes standard cell and tail cell；Standard cell includes standard cell load and standard header；
Tail cell includes tail cell load and tail header；The length of tail cell load is less than or equal to the length of standard cell；Exchange
Module is used to determine dispatching cycle according to the standard cell head or tail header according to cell to be processed；According to dispatching cycle and
Preset arbitrated logic is cached and is transmitted to cell to be processed；Recombination module be used for receive Switching Module transmission wait locate
Cell is managed, and according to standard header and tail header, cell to be processed is recombinated, reorganizing packets are obtained, will be recombinated
Data packet is sent to output equipment.
Above-mentioned cutting module can be by sequentially connected cutting unit 11, header generation unit 12 and 13 groups of encapsulation unit
At structural schematic diagram is as shown in Figure 2；Wherein, cutting unit be used for according to preset cell length to data packet to be processed into
Row cutting obtains standard cell load and tail cell load；The length of standard cell load is identical as preset cell length；When
When the remaining data frame length of pending data packet is less than preset cell length, using remaining data frame as tail cell load；
Header generation unit is used to obtain the parameter of standard cell load and tail cell load, generates standard header and tail cell
Head；Standard header includes priority, destination port and the cell length of standard cell load；Tail header includes tail cell
Priority, destination port, cell length and the instruction of tail cell；Encapsulation unit be used for standard header and standard cell load into
Row encapsulation, obtains standard cell；Tail header and tail cell load are packaged, tail cell is obtained.
Above-mentioned Switching Module can be established based on the structure of corsspoint switch matrix (Crossbar)；Switching Module is usually by
The input buffer of one quantity and the intersection cache device of the second quantity are constituted；The numerical value of second quantity is equal to the number of the first quantity
Square of value；I.e. input buffer is N number of (input buffer 1, input buffer 2 ... input buffer N), intersection cache device
For N2A (intersection cache device 1, intersection cache device 2 ... intersection cache device N)；Input buffer and intersection cache device are pressed
According to the structure connection of corsspoint switch matrix；One input buffer is connect with a cutting module；Intersection cache device and recombination
Module connection；Intersection cache device is arranged according to the form of line-column matrix, the corresponding intersection cache of each input buffer
Device row, the corresponding intersection cache device column of each recombination module；During the work time, Switching Module receives cell to be processed
Afterwards, the length of the cell can be determined according to header, and according to cell length and transmission rate, determines dispatching cycle；In the tune
It spends in the period, which can be transferred to recombination module；After dispatching cycle, according to preset arbitrated logic and interchange mode
Transmission situation in block generates arbitration result to next cell；After arbitration result, which is shown, to be transmitted, to next
Cell is transmitted.Under normal conditions, longer than the dispatching cycle of tail cell when the dispatching cycle of standard cell；With in the prior art
Substantially using comparing same dispatching cycle, efficiency of transmission is improved.
Above-mentioned recombination module includes recombination memory management unit 31, recombination cache unit 32 and controls recomposition unit 33,
Structural schematic diagram is as shown in Figure 3；Recombinate the recombination buffer address that cache unit includes setting quantity；Memory management unit is recombinated to use
It is numbered in for standard cell load or tail cell load distribution buffer address；Recombinate cache unit be used for standard cell load or
Tail cell load is stored in buffer address and numbers in corresponding recombination buffer address；Recomposition unit is controlled to be used for according to preset heavy
Group control rule, standard header and tail header read buffer address and number the corresponding standard letter recombinated in buffer address
First load and tail cell load, recombinate standard cell load and tail cell load, obtain reorganizing packets.
The embodiment of the invention provides a kind of switches of variable cell；Cutting module is according to preset cell length pair
The pending data packet that input equipment is sent carries out cutting, generates cell to be processed；Cell to be processed includes standard cell and tail
Cell；Switching Module determines dispatching cycle according to the standard cell head or tail header of cell to be processed；According to dispatching cycle and
Preset arbitrated logic is cached and is transmitted to cell to be processed；Recombination module receives the letter to be processed that Switching Module is sent
Member, and according to standard header and tail header, cell to be processed is recombinated, reorganizing packets are obtained, by recombination data
Packet is sent to output equipment.Which is transmitted with elongated cell, and according to the cell tune of different length in transmission process
It improves efficiency of transmission whole dispatching cycle, and reduces cache management difficulty.
The embodiment of the invention also provides the packet switching construction that a kind of length can be changed cell, which is based on
Switching fabric shown in FIG. 1 realizes that the data flow schematic diagram of the structure is as shown in Figure 4；The structure includes exchange access
(Switch Access) and two parts of exchange network (Switch Fabric), exchange access are divided into cutting (Packet again
Segment) and recombination (Packet Assemble) two functional modules, cutting module receive complete data frame, based on single
Data frame is cut, and when curtailment cell length to be cut, without filling, is forwarded according to true length；
And the header comprising information such as priority, destination port, cell length, the instructions of tail cell is generated for each cell, as
Channel associate signals are transmitted；Exchange network is forwarded according to the forwarding information carried in cell to specific destination port, weight
Group module recovers complete data frame according to shuffling information after cell reception is complete；The scheduling interval of exchange network is according to institute
The actual length for recalling cell carries out adaptively, guaranteeing that cell is transmitted back-to-back；Each nodal cache as unit of cell into
Row management, reduces cache management difficulty.
Switching fabric schematic diagram proposed in this paper as shown in figure 5, Packet Segment module complete data frame cutting,
The encapsulation of cell and header information is completed in cutting, and header is sent to Switch with the first count of cell as with circuit-switched data
In the Input Buffer (input buffer) of Fabric (switching fabric)；Packet Assemble (recombination) module receive from
The cell that CrossPoint Buffer (intersection cache) is sended over, and completed according to the assembling information carried in header
The recombination of data frame.Packet Segment (cutting) and Packet Assemble module together constitute exchange AM access module；
Switch Fabric module is by N number of Input Buffer and N2A CrossPoint Buffer is constituted, and Input Buffer draws
Entering VOQ mechanism prevents that head obstruction occurs in case of congestion, and CrossPoint Buffer is arranged according to the form of line-column matrix
Column, the corresponding CrossPoint Buffer row of each Input Buffer module, each Packet Assemble module pair
Answer a CrossPoint Buffer column.
Above-mentioned Input Buffer module (being equivalent to input buffer) includes input-buffer administrative unit, input-buffer list
Cell to be processed is split into cell load data and header by member and control unit, is carried out at data and control two paths
Reason；Input-buffer unit includes the input-buffer address for setting quantity；Input-buffer administrative unit, input-buffer unit and control
Unit connects two-by-two；Input-buffer administrative unit is used to number for standard cell load or tail cell load distribution buffer address；
Input-buffer unit is used to for standard cell load or tail cell load being stored in buffer address with numbering corresponding input-buffer
In location；Control unit is used for the tail header of the standard cell head or tail cell load according to standard cell load, virtual output
The system information elements transmission state of queue (VoQ, Virtual Output Queue) mechanism and intersection cache device feedback, generates the
One arbitration result；It is numbered according to arbitration result and buffer address, reads standard cell load or tail cell load, and will be to be processed
Cell transmission is into crosspoint buffer.
Input Buffer module signal flow schematic diagram during the work time is as shown in fig. 6, input shown in Fig. 6
In buffer, control unit is made of VOQ, Arbiter (moderator) and transmission control；It is realized especially by following manner:
(1) input of control channel is header relevant information, and header marker pulse can enter cache management mould first
Block application obtains idle address block number.
(2) address block number enters corresponding VOQ together with information such as destination port, length and priority inside header
FIFO or chained list can be used to realize in queue, VOQ queue.
(3) VOQ information corresponding with destination port can enter Arbiter arbitration modules, and moderator can effectively refer to according to VOQ
Show the free time instruction with rear class CrossPoint Buffer, generates arbitration result in real time.
(4) transmission control module can be the two conditions that meet that rear class caching is idle and current transmission closes to an end the case where
Lower latch arbitration result reads time delay by current transmission cell length and caching RAM at the time of arbitration result latches and codetermines,
The arbitration result of latch can be fed back in VOQ, and triggering goes out team and arbitration result update action by arbitration cell, and then transmits control
Module can be as fast as possible obtain updated arbitration result, to realize the back-to-back transmission of elongated cell.
(5) since the reading of caching needs time delay, so header information can enter the CrossPoint of junior in advance
Buffer, and then pre-cooling is dispatched, and propagation delay time is reduced；
(6) input of data channel is cell load data, mainly caches the write-in and reading of RAM, writing address root
It is generated according to the cache blocks label of caching management module output, reads address by transmitting the cache blocks in the arbitration information that control is latched
Number generates；
(7) the header information that the cell load data and transport management module that cache module is read latch can be in dispatching terminal
Mouth instruction is lower to enter the corresponding CrossPoint Buffer of junior.
The processing of this module has several key points: the read-write of a address management module and caching is single for management with address block
Position, address block capacity are consistent with standard cell size；And there is only the data of a data frame in single cell, and frame is not present
Splicing, reduce cache management difficulty；Which kind of arbitration scheme no matter b arbitration modules use, and arbitration result will follow the variation of VOQ
It timely updates, so that transport management module can obtain newest arbitration knot before the tail cell transmission of indefinite length finishes
Fruit realizes that load data is uninterruptedly exported in the form of flowing water；The header information that c transport management module is obtained from arbitration result
Enter selected CrossPoint Buffer in cell load information in advance, so can with the arbitration of pre-cooling control channel,
Transmission delay is reduced, can accomplish that load data is not stored in CrossPoint Buffer and grade passes directly down under optimal situation
It send.
It is illustrated in figure 7 the structural schematic diagram of CrossPoint Buffer node (intersection cache device), with Input
Buffer structure is similar, and only arbitration and transport management module are transferred to module-external, by each CrossPoint of cross matrix
Buffer is shared.
The process flow of CrossPoint Buffer is also similar with Input Buffer:
(1) control channel: can be applied from cache management by the output header marker pulse of Input Buffer module
To idle buffer address block number, together with the letter such as the cell length of agreement, cell priority and the instruction of tail cell in header
Breath enters VOQ together；VOQ can be realized that VOQ queue head is understood and same column to arbitration information by chained list or FIFO
CrossPoint Buffer output is arbitrated into output arbitration modules together to arbitration information；Arbitration result can be real-time
It is updated according to the variation of VOQ, transmission control module can cache the case where idle and current cell is by the end of transmission in rear class
Under, arbitration result is latched, the transmission for starting next cell is prepared；The arbitration result of latch can feed back corresponding CrossPoint
In the VOQ of Buffer, triggering goes out team, VOQ updates and arbitration result update action, and then transmission control module by arbitration cell
Can be as fast as possible obtain updated arbitration result, to realize the back-to-back transmission of elongated cell；The arbitration knot of latch
Fruit still exports cell information simultaneously and assembles module to the data frame of rear class.
(2) data channel: similar with Input Buffer realization, the cell load information sended over from higher level can store
In the address block obtained to application, after arbitration result locking, start to read data outward under transport management module control；With
Unlike Input Buffer, there are multiple cachings in CrossPoint Buffer column, need a bus Mux according to secondary
The selection in result is cut out, data read-out by the caching that selection arbitration is chosen are conveyed to the data frame assembling module of rear class.
It is illustrated in figure 8 the structural schematic diagram of Packet Assemble module, with preceding two-stage Buffer workflow class
Seemingly.Control plane, the header instruction from CrossPoint Buffer can obtain the free time from caching management module application first
Buffer address block number；The assembling information carried in buffer address number and header can enter in group packet queue, group packet team
Column can judge the institute from certain source port priority data frame according to source port information, precedence information and tail EOP information
There is cell whether to collect to finish, be finished if collecting, cell information can be successively sent to a group packet control module according to a group packet sequence
In；Group packet control module can be numbered according to the buffer address in group cell information of packet queue output, carry cell from caching
Lotus reads, and is indicated according to the tail cell carried in cell information, and data frame EOP instruction is generated at the time of suitable.
The packet switching construction that a kind of length provided in an embodiment of the present invention can be changed cell has the advantage that using in list
It is cut in a data frame with the mode of elongated cell, avoids band caused by the data filling introduced by fixed length cell scheme
Cache management caused by cutting after width waste and data frame splicing is difficult；Cell relevant information is read, cell priority as cell is long
With tail cell mark etc., as being transmitted with circuit-switched data for cell load, the waste of bus bandwidth is avoided；It is tied using arbitration
The mechanism of fruit real-time update adaptively adjusts scheduling interval according in biography cell length, locks the arbitration result of real-time update, real
The back-to-back transmission of existing elongated cell；Using header earlier than the mechanism that cell load exports, so that scheduling result can be in cell
Load updates before reaching caching, it can be achieved that cell load does not enter caching directly transmits, and optimizes switching delay.
The embodiment of the present invention also provides a kind of exchange system of variable cell, and structural schematic diagram is as shown in Figure 9；The system
Switch 90 including input equipment 91, output equipment 92 and above-mentioned variable cell.
The exchange system of variable cell provided in an embodiment of the present invention, with exchanging for variable cell provided by the above embodiment
Structure technical characteristic having the same reaches identical technical effect so also can solve identical technical problem.
Corresponding to above-described embodiment, the embodiment of the present invention also provides a kind of exchange method of variable cell, this method application
In the switch of above-mentioned variable cell, flow diagram is as shown in Figure 10；Method includes the following steps:
Step S100: cutting module cuts the pending data packet that input equipment is sent according to preset cell length
Point, generate cell to be processed；Cell to be processed includes standard cell and tail cell；Standard cell includes standard cell load and mark
Quasi- header；Tail cell includes tail cell load and tail header；The length of tail cell load is less than or equal to standard cell
Length.
Step S102: Switching Module determines dispatching cycle according to the standard cell head or tail header of cell to be processed；Root
According to dispatching cycle and preset arbitrated logic, cell to be processed is cached and transmitted.
Step S104: recombination module receives the cell to be processed that Switching Module is sent, and is believed according to standard header and tail
First head, recombinates cell to be processed, obtains reorganizing packets, and reorganizing packets are sent to output equipment.
Specifically, above-mentioned cutting module includes sequentially connected cutting module, header generation unit and encapsulation unit；On
Stating step S100 can realize especially by following manner:
(1) dividing die root tuber carries out cutting to data packet to be processed according to preset cell length, obtains standard cell load
And tail cell load.
(2) header generation unit obtains the parameter of standard cell load and tail cell load, generate standard header and
Tail header；Standard header includes priority, destination port and the cell length of standard cell load；Tail header includes tail
Priority, destination port, cell length and the instruction of tail cell of cell.
(3) encapsulation unit is packaged standard header and standard cell load, obtains standard cell；To tail header
And tail cell load is packaged, and obtains tail cell.
Specifically, the structure that above-mentioned Switching Module is based on corsspoint switch matrix (Crossbar) is established；Switching Module includes
The intersection cache device of the input buffer of first quantity and the second quantity；The numerical value of second quantity is equal to the numerical value of the first quantity
Square；Input buffer and intersection cache device are connected according to the structure of corsspoint switch matrix；Input buffer and dividing die
Block connection；Intersection cache device is connect with recombination module.
Specifically, above-mentioned input buffer includes input-buffer administrative unit, input-buffer unit and control unit；Input
Cache unit includes the input-buffer subspace for setting quantity；Input-buffer administrative unit, input-buffer unit and control unit
It connects two-by-two；The above method further include:
(1) input-buffer administrative unit is that standard cell load or tail cell load distribution buffer address are numbered.
(2) standard cell load or tail cell load are stored in buffer address and number corresponding input by input-buffer unit
It caches in subspace.
(3) control unit is according to the tail header of the standard cell head or tail cell load of standard cell load, virtual defeated
The system information elements transmission state of dequeue (VoQ, Virtual Output Queue) mechanism and intersection cache device feedback, generates
First arbitration result.
(4) it is numbered according to arbitration result and buffer address, reads standard cell load or tail cell load, and will be to be processed
Cell transmission is into crosspoint buffer.
It can be changed the switching fabric of cell, the computer program product of system and method, packet provided by the embodiment of the present invention
The computer readable storage medium for storing program code is included, the instruction that program code includes can be used for executing previous methods implementation
Method in example, specific implementation can be found in embodiment of the method, and details are not described herein.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description
And/or the specific work process of device, it can refer to corresponding processes in the foregoing method embodiment, details are not described herein.
Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Pipe present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that: its according to
So be possible to modify the technical solutions described in the foregoing embodiments, or to some or all of the technical features into
Row equivalent replacement；And these are modified or replaceed, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (10)
1. a kind of switch of variable cell, which is characterized in that described device includes sequentially connected cutting module, interchange mode
Block and recombination module；The cutting module is connect with input equipment；The recombination module is connect with output equipment；
The cutting module is for cutting the pending data packet that the input equipment is sent according to preset cell length
Point, generate cell to be processed；The cell to be processed includes standard cell and tail cell；The standard cell includes standard cell
Load and standard header；The tail cell includes tail cell load and tail header；The length of the tail cell load is less than
Or the length equal to the standard cell；
The Switching Module is used for the standard cell head or tail header according to the cell to be processed, determines dispatching cycle；Root
According to the dispatching cycle and preset arbitrated logic, the cell to be processed is cached and transmitted；
The recombination module is used to receive the cell to be processed that the Switching Module is sent, and according to the standard header and institute
Tail header is stated, the cell to be processed is recombinated, reorganizing packets are obtained, the reorganizing packets are sent to described
Output equipment.
2. the apparatus according to claim 1, which is characterized in that the cutting module include sequentially connected cutting module,
Header generation unit and encapsulation unit；
The cutting module is used to carry out cutting to the pending data packet according to preset cell length, obtains the standard
Cell load and the tail cell load；
The header generation unit is used to obtain the parameter of the standard cell load and the tail cell load, described in generation
Standard header and the tail header；The standard header includes the priority of the standard cell load, destination port
And cell length；The tail header includes priority, destination port, cell length and the instruction of tail cell of the tail cell；
The encapsulation unit obtains the standard letter for being packaged to the standard header and the standard cell load
Member；The tail header and the tail cell load are packaged, the tail cell is obtained.
3. the apparatus of claim 2, which is characterized in that the Switching Module is built based on the structure of corsspoint switch matrix
It is vertical；The Switching Module includes the input buffer of the first quantity and the intersection cache device of the second quantity；Second quantity
Numerical value be equal to first quantity numerical value square；The input buffer and the intersection cache device are according to the friendship
Pitch the structure connection of switch matrix；The input buffer is connect with the cutting module；The intersection cache device with it is described
Recombination module connection.
4. device according to claim 3, which is characterized in that the input buffer include input-buffer administrative unit,
Input-buffer unit and control unit；The input-buffer unit includes setting quantity and the input-buffer being sized son sky
Between；The corresponding buffer address number in one input-buffer subspace；The input-buffer administrative unit, the input are slow
Memory cell is connect two-by-two with described control unit；
The input-buffer administrative unit is used to compile for the standard cell load or the tail cell load distribution buffer address
Number；
The input-buffer unit is used to the standard cell load or the tail cell load being stored in the buffer address
It numbers in the corresponding input-buffer subspace；
Described control unit is used for according to the current corresponding standard cell head or tail header of cell to be processed, determine it is described to
Handle the cell length of cell；According to the cell length, dispatching cycle is determined；According to the dispatching cycle, virtually export team
The system information elements transmission state of column mechanism and intersection cache device feedback, generates arbitration result；According to the arbitration result
And the buffer address number, the standard cell load or the tail cell load are read, and the cell to be processed is passed
It transports in the intersection cache device.
5. device according to claim 4, which is characterized in that the recombination module includes recombination memory management unit, again
Group cache unit and control recomposition unit；The recombination cache unit includes that setting quantity and the recombination being sized caching are empty
Between；One corresponding buffer address number in recombination caching subspace；
The recombination memory management unit is used to compile for the standard cell load or the tail cell load distribution buffer address
Number；
The recombination cache unit is used to the standard cell load or the tail cell load being stored in the buffer address
It numbers in corresponding recombination caching subspace；
The control recomposition unit is used for according to preset recombination control rule, the standard header and the tail header,
It reads the buffer address and numbers the corresponding standard cell load recombinated in caching subspace and the tail cell
Load recombinates the standard cell load and the tail cell load, obtains reorganizing packets.
6. a kind of exchange system of variable cell, which is characterized in that including input equipment, output equipment and such as claim 1-5
The switch of described in any item variable cells.
7. a kind of exchange method of variable cell, which is characterized in that the method is applied to variable letter as described in claim 1
The switch of member；The described method includes:
The cutting module carries out cutting to the pending data packet that the input equipment is sent according to preset cell length, raw
At cell to be processed；The cell to be processed includes standard cell and tail cell；The standard cell includes standard cell load
And standard header；The tail cell includes tail cell load and tail header；The length of the tail cell load is less than or waits
In the length of the standard cell；
The Switching Module determines dispatching cycle according to the standard cell head or tail header of the cell to be processed；According to institute
Dispatching cycle and preset arbitrated logic are stated, the cell to be processed is cached and transmitted；
The recombination module receives the cell to be processed that the Switching Module is sent, and according to the standard header and the tail
Header, recombinates the cell to be processed, obtains reorganizing packets, and the reorganizing packets are sent to the output
Equipment.
8. the method according to the description of claim 7 is characterized in that the cutting module include sequentially connected cutting module,
Header generation unit and encapsulation unit；The pending data that the input equipment is sent according to preset cell length
Packet carries out cutting, generates cell to be processed, comprising:
The dividing die root tuber carries out cutting to the pending data packet according to preset cell length, obtains the standard cell
Load and the tail cell load；
The header generation unit obtains the parameter of the standard cell load and the tail cell load, generates the standard
Header and the tail header；The standard header includes priority, destination port and the letter of the standard cell load
First length；The tail header includes priority, destination port, cell length and the instruction of tail cell of the tail cell；
The encapsulation unit is packaged the standard header and the standard cell load, obtains the standard cell；
The tail header and the tail cell load are packaged, the tail cell is obtained.
9. according to the method described in claim 8, it is characterized in that, the Switching Module is based on corsspoint switch matrix
(Crossbar) structure is established；The Switching Module includes that the input buffer of the first quantity and the crosspoint of the second quantity are delayed
Storage；The numerical value of second quantity is equal to square of the numerical value of first quantity；The input buffer and the intersection
Point cache device is connected according to the structure of the corsspoint switch matrix；The input buffer is connect with the cutting module；It is described
Intersection cache device is connect with the recombination module.
10. according to the method described in claim 9, it is characterized in that, the input buffer include input-buffer administrative unit,
Input-buffer unit and control unit；The input-buffer unit includes the input-buffer subspace for setting quantity；Described in one
The corresponding buffer address number in input-buffer subspace；The input-buffer administrative unit, the input-buffer unit and institute
Control unit is stated to connect two-by-two；The method also includes:
The input-buffer administrative unit is that the standard cell load or the tail cell load distribution buffer address are numbered；
The standard cell load or the tail cell load are stored in the buffer address and numbered by the input-buffer unit
In the corresponding input-buffer subspace；
Described control unit is according to the standard header of the corresponding standard cell load of the current cell to be processed or described
The tail header of tail cell load determines the cell length of the cell to be processed；According to the cell length, scheduling week is determined
Phase；According to the dispatching cycle, virtual output queue mechanism and the intersection cache device feed back system information elements transmission state,
Generate arbitration result；It is numbered according to the arbitration result and the buffer address, reads the standard cell load or the tail
Cell load, and by the cell transmission to be processed into the intersection cache device.
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