CN110233131B - Metal plug and forming method thereof - Google Patents
Metal plug and forming method thereof Download PDFInfo
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- CN110233131B CN110233131B CN201810175124.1A CN201810175124A CN110233131B CN 110233131 B CN110233131 B CN 110233131B CN 201810175124 A CN201810175124 A CN 201810175124A CN 110233131 B CN110233131 B CN 110233131B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Abstract
The invention discloses a metal plug and a forming method thereof, comprising the following steps: forming a first interlayer dielectric layer on a semiconductor substrate, and forming a plurality of grid electrodes in the first interlayer dielectric layer; removing part of the first interlayer dielectric layer to form a first plug hole in the first interlayer dielectric layer between the adjacent gates; filling metal into the first plug hole to form a first sub-metal plug; forming a second interlayer dielectric layer adjacent to the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first sub-metal plug; removing part of the second interlayer dielectric layer to form a second plug hole exposing the first sub-metal plug above the position corresponding to the first sub-metal plug; and filling metal into the second plug hole to form a second sub-metal plug. A metal plug is divided into a plurality of sections to be formed, so that holes are prevented from being formed in the metal plug, and the performance of the metal plug is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a metal plug and a method for forming the metal plug.
Background
In the process of manufacturing a semiconductor device, the conduction of current is usually realized through a metal connection structure, so as to realize a specific function of the semiconductor device. Generally, metal plugs are connected between different semiconductor devices and respectively connected with the gate and the source/drain regions.
In the use process of the metal plug formed by the prior art, the resistance of the metal plug is higher, and the passing current is lower under the same voltage, so that the performance of a semiconductor device is seriously influenced.
Therefore, a method for forming a metal plug capable of reducing the resistance of the metal plug is needed.
Disclosure of Invention
In the forming method of the metal plug disclosed by the embodiment of the invention, one metal plug is formed for multiple times, so that the resistance of the metal plug is finally reduced, and the conductivity of the metal plug is improved.
The invention discloses a forming method of a metal plug, which comprises the following steps: forming a first interlayer dielectric layer on a semiconductor substrate, and forming a plurality of grid electrodes in the first interlayer dielectric layer; removing part of the first interlayer dielectric layer to form a first plug hole in the first interlayer dielectric layer between the adjacent gates; filling metal into the first plug hole to form a first sub-metal plug; forming a second interlayer dielectric layer adjacent to the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first sub-metal plug; removing part of the second interlayer dielectric layer to form a second plug hole exposing the first sub-metal plug above the position corresponding to the first sub-metal plug; and filling metal into the second plug hole to form a second sub-metal plug.
According to one aspect of the invention, the first sub-metal plug is connected with the second sub-metal plug to form a dielectric layer metal plug.
According to an aspect of the present invention, the width of the second sub metal plug is equal to the width of the first sub metal plug.
According to an aspect of the present invention, the metal material filled into the first plug hole and/or the second plug hole includes W, Al or Cu.
According to an aspect of the present invention, after the forming of the first plug hole and before the forming of the first sub metal plug, the method further includes: and forming silicide at the bottom of the first plug hole.
According to one aspect of the invention, the material of the silicide comprises: WSi2、TiSi2、TaSi2One or more of (a).
According to an aspect of the present invention, before filling the first plug hole and the second plug hole with metal, respectively, the method further includes: barrier layers are formed to cover inner walls of the first plug hole and the second plug hole, respectively.
According to an aspect of the present invention, after forming the barrier layer, the method further includes: a seed layer is formed overlying the barrier layer surface.
According to an aspect of the present invention, the second plug hole is formed while including: removing part of the second interlayer dielectric layer above the grid to form a first grid plug hole for exposing the grid; and filling metal into the first gate plug hole to form a first sub-gate metal plug.
According to an aspect of the present invention, after forming the second sub metal plug and the first sub gate metal plug, the method further includes: forming a third interlayer dielectric layer adjacent to the second interlayer dielectric layer, wherein the third interlayer dielectric layer covers the second sub-metal plug and the first sub-gate metal plug; removing part of the third interlayer dielectric layer to form a third plug hole and a second grid plug hole above the corresponding positions of the second sub-metal plug and the first sub-grid metal plug respectively and expose the second sub-metal plug and the first sub-grid metal plug; and filling metal into the third plug hole and the second gate plug hole to form a third sub-metal plug and a second sub-gate metal plug.
According to an aspect of the invention, the third sub-metal plug is connected with the second sub-metal plug, and the dielectric layer metal plug includes the first sub-metal plug, the second sub-metal plug and the third sub-metal plug.
According to an aspect of the present invention, the first sub-gate metal plug is connected to the second sub-gate metal plug to form a gate metal plug.
According to one aspect of the invention, the metal plug includes a dielectric layer metal plug and a gate metal plug.
According to one aspect of the invention, the thickness of the second dielectric layer and/or the third dielectric layer is less than or equal to 25 nm.
According to an aspect of the present invention, after forming the first sub metal plug, the method further includes: and grinding by adopting a mechanical planarization process to enable the top of the grid electrode to be flush with the top of the first sub-metal plug.
According to an aspect of the invention, the third interlayer dielectric layer is formed before. Further comprising: and grinding by adopting a mechanical planarization process to enable the top of the second sub-metal plug to be flush with the top of the first sub-gate metal plug.
According to one aspect of the invention, the number of layers forming the interlayer dielectric layer is more than three, the formed dielectric layer metal plug comprises more than three sub-metal plugs, and the gate metal plug comprises more than two sub-gate metal plugs.
According to one aspect of the invention, the dielectric layer metal plug comprises a plurality of sub-metal plugs, and the gate metal plug comprises a plurality of sub-gate metal plugs.
According to one aspect of the present invention, the aspect ratio of the plurality of sub-metal plugs to the plurality of gate metal plugs is γ, γ ≦ 4.
According to one aspect of the invention, the thickness of the multiple interlevel dielectric layers is less than or equal to 25 nm.
Accordingly, the present invention also provides a metal plug comprising: the grid-type semiconductor device comprises a semiconductor substrate, a first interlayer dielectric layer and a plurality of grids, wherein the first interlayer dielectric layer is adjacently arranged above the semiconductor substrate, and the grids are distributed in the first interlayer dielectric layer at intervals; the first sub-metal plug is formed in the first interlayer dielectric layer between the adjacent grid electrodes; the second interlayer dielectric layer is adjacently arranged above the first interlayer dielectric layer; and the second sub-metal plug is formed in the second interlayer dielectric layer, the position of the second sub-metal plug corresponds to the position of the first sub-metal plug, and the second sub-metal plug is connected with the first sub-metal plug.
According to an aspect of the invention, the second sub-metal plug and the first sub-metal plug form a dielectric layer metal plug.
According to one aspect of the invention, the method further comprises the following steps: and the first sub-gate metal plug is formed in the second interlayer dielectric layer above the gate.
According to one aspect of the invention, the method further comprises the following steps: the third interlayer dielectric layer is adjacently arranged above the second interlayer dielectric layer; the third sub-metal plug is formed in the third interlayer dielectric layer, the position of the third sub-metal plug corresponds to the position of the second sub-metal plug, and the third sub-metal plug is connected with the second sub-metal plug; and the second sub-gate metal plug is formed in the third interlayer dielectric layer, corresponds to the first sub-gate metal plug in position, and is connected with the first sub-gate metal plug.
According to an aspect of the invention, the first sub-gate metal plug and the second sub-gate metal plug constitute a gate metal plug, and the dielectric layer metal plug includes a first sub-metal plug, a second sub-metal plug and a third sub-metal plug.
According to one aspect of the invention, the metal plug includes a dielectric layer metal plug and a gate metal plug.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the invention, part of the second interlayer dielectric layer is removed to form a second plug hole exposing the first sub-metal plug above the position corresponding to the first sub-metal plug; and filling metal into the second plug hole to form a second sub-metal plug. And forming a second sub-metal plug so that the metal plug is composed of a plurality of sub-metal plugs, and the height and the width of the formed sub-metal plugs are relatively close to each other, so that no hole is formed in the finally formed metal plug, and the electric conduction capability of the metal plug is improved.
Further, a seed layer is formed overlying the barrier layer surface. After the seed layer is formed and the metal is filled into the plug hole, no defect appears at the interface.
Furthermore, the aspect ratio of the plurality of sub-metal plugs to the plurality of gate metal plugs is gamma, and gamma is less than or equal to 4. When the height and the width of the sub-metal plug and the metal plug are close to each other, the formed metal plug structure is more regular, no hole is formed in the metal plug structure, the formed metal plug structure is more compact, and the conductivity is better.
Drawings
Fig. 1-5 are schematic cross-sectional views illustrating a metal plug formation process according to an embodiment of the invention.
Detailed Description
As described above, the conventional metal plug has a problem of high resistance during use.
The research finds that the reasons causing the problems are as follows: and forming a very thick dielectric layer at one time, forming a plug hole through one-time etching, and filling metal into the plug hole to form a metal plug. Under the process, the plug hole is not fully filled, and a hole is easily generated in the metal plug, so that the effective conduction area of the metal plug is reduced, and the working resistance of the metal plug is increased. When the same function is achieved, a larger voltage is required, the load of the semiconductor device is increased, and the application range of the semiconductor device is narrowed.
In order to solve the problem, the invention provides a method for forming a metal plug, which divides a metal plug into a plurality of sections to be formed, the height and the width of each section of sub-metal plug are relatively close, the sub-metal plug without holes inside is easy to form, finally, the holes do not appear inside the whole metal plug, and the conduction performance of the metal plug is improved.
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be understood that the relative arrangement of parts and steps, numerical expressions and numerical values set forth in these embodiments should not be construed as limiting the scope of the invention unless it is specifically stated otherwise.
Further, it will be appreciated that the dimensions of the various elements shown in the figures are not necessarily drawn to scale relative to actual dimensions, for example, the thickness or width of some layers may be exaggerated relative to other layers for ease of illustration.
The following description of the exemplary embodiment(s) is merely illustrative and is not intended to limit the invention or its application or uses in any way.
Techniques, methods, and apparatus that are known to one of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the present description where applicable.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined or illustrated in one figure, further discussion thereof will not be required in the subsequent description of the figures.
Referring to fig. 1, a first interlayer dielectric layer 111 is formed on a semiconductor substrate 100, and a plurality of gates 120 are formed in the first interlayer dielectric layer 111.
The semiconductor substrate 100 serves as a foundation for subsequent semiconductor devices. The material of the semiconductor substrate 100 may be undoped single crystal silicon, impurity-doped single crystal silicon, silicon-on-insulator (SOI), or the like. Specifically, in the embodiment of the present invention, the material of the semiconductor substrate 100 is undoped monocrystalline silicon.
The first interlayer dielectric layer 111 plays a role of isolation. The material of the first interlayer dielectric layer 111 is SiO2。
The gate 120 plays a controlling role in the semiconductor device. The material of the gate 120 comprises polysilicon, or W, Al, etc. Specifically, in the embodiment of the present invention, the material of the gate 120 is polysilicon.
Before forming the gate 120, the method further includes; gate dielectric layers 121 are formed at two sides of the gate electrode 120 to protect the gate electrode 120. In the embodiment of the present invention, the gate dielectric layer 121 is made of SiN.
In the embodiment of the present invention, after forming the gate 120, the method further includes: portions of the first interlayer dielectric layer 111 are removed to form first plug holes 130 in the first interlayer dielectric layer 111 between adjacent gates 120.
Generally, different units of a semiconductor device are connected by metal, and then conduction is realized. The first plug hole 130 is thus formed for the purpose of subsequently filling the interior thereof with metal.
Referring to fig. 2, a metal is filled into the first plug hole 130 to form a first sub-metal plug 131.
Forming the first sub-metal plugs 131 is a necessary step for forming dielectric layer metal plugs. The material of the first sub-metal plugs 131 includes W, Al or Cu, etc. Specifically, in the embodiment of the present invention, the material of the first sub metal plug 131 is W. In another embodiment of the present invention, the material of the first sub-metal plug 131 is Al.
Generally, when the plug hole is shallow, that is, when the depth and the width of the plug hole are close to each other, after the metal is filled, the occurrence of the hole can be effectively avoided, the density of the metal plug can be increased, and the conductivity of the metal plug can be improved. Therefore, in the embodiment of the present invention, the same metal plug is formed in multiple times. And the aspect ratio of the sub-gate plug is gamma, and gamma is less than or equal to 4. Specifically, in the embodiment of the present invention, the aspect ratio γ of the first sub metal plug 131 is 3. Here, the aspect ratio γ of the first sub metal plug 131 is h 1:w1As shown in fig. 2.
In the embodiment of the present invention, after the first plug hole is formed and before the first sub metal plug 131 is formed, the method further includes: a silicide 160 is formed at the bottom of the first plug hole. Silicide 160 serves to optimize metal plug conduction. The materials of silicide 160 include: WSi (Wireless sensor network interface)2、TiSi2、TaSi2One or more of (a). Specifically, in the embodiment of the present invention, the silicide 160 is WSi2。
In an embodiment of the present invention, before filling the first plug hole with the metal, the method further includes: a barrier layer 150 is formed covering the inner wall of the first plug hole. Forming the barrier layer 150 can prevent stress from being generated at the interface directly after filling the first plug hole with metal.
After forming the barrier layer 150, further comprising forming a seed layer 140 overlying the barrier layer 150. The seed layer 140 is formed to better fill metal into the seed layer, thereby avoiding the occurrence of interface defects.
In an actual manufacturing process, it is difficult to ensure that the top of the first sub metal plug 131 is flush with the top of the gate 120. Therefore, in the embodiment of the present invention, after forming the first sub-metal plugs 131, a mechanical planarization process is further performed to polish the top of the gate 120 to be flush with the top of the first sub-metal plugs 131.
Referring to fig. 3, a second interlayer dielectric layer 112 is formed adjacent to the first interlayer dielectric layer 111.
The function of the second interlayer dielectric layer 112 is the same as that of the first interlayer dielectric layer 111, and the second interlayer dielectric layer 112 covers the first sub-metal plug 131.
Since it is necessary to form a shallower second plug hole later, in the embodiment of the present invention, the thickness of the second interlayer dielectric layer 112 is less than or equal to 25 nm. Specifically, in the embodiment of the present invention, the thickness of the second interlayer dielectric layer 112 is 20 nm. The size is such that the depth and width of the plug hole are close, no hole exists in the formed metal plug structure, and the structure is more compact.
After the second interlayer dielectric layer 112 is formed, a portion of the second interlayer dielectric layer 112 is removed to form a second plug hole 170.
The second plug hole 170 is formed to fill metal into the inside thereof. The position of the second plug aperture 170 corresponds to the position of the first plug aperture previously described, and the second plug aperture 170 exposes the first sub metal plug 131. Here, "positionally corresponding" means that the second plug bore 170 coincides with the longitudinal center axis of the first plug bore longitudinal section, as shown by the center axis 10 in fig. 3.
In the embodiment of the present invention, the second plug hole 170 is formed, and at the same time, the method further includes: a portion of the second interlayer dielectric layer 112 above the gate 120 is removed to form a first gate plug hole 180 exposing the gate 120.
The first gate plug hole 180 is formed for subsequent filling of metal therein to form a gate metal plug, thereby achieving connection with the gate 120.
Referring to fig. 4, metal is filled into the second plug hole 170 and the first gate plug hole 180, respectively, to form a second sub-metal plug 171 and a first sub-gate metal plug 181.
The second sub-metal plug 171 is connected to the first sub-metal plug 131 to form a dielectric layer metal plug. In the embodiment of the present invention, the second sub-metal plugs 171 and the first sub-metal plugs 131 have the same width. And the aspect ratio γ of the second sub-metal plug 171 is less than or equal to 4. Here, the aspect ratio γ is h2:w2As shown in fig. 4. Specifically, in the embodiment of the present invention, the aspect ratio γ of the second sub metal plug 171 is 1.
Similarly, before filling metal, the method also comprises the following steps: the barrier layer 150 and the seed layer 140 are sequentially formed on the inner wall of the second plug hole 170.
Here, the material of the second sub-metal plug 171 may be the same as or different from that of the first sub-metal plug 131. Specifically, in the embodiment of the present invention, the material of the second sub metal plug 171 is the same as the material of the first sub metal plug 131. The material of the second sub-metal plugs 171 is W.
The first sub-gate metal plug 181 is a part of the gate metal plug. As described above, in order to form a metal plug with better conductivity, the gate metal plug is also formed several times, as in the dielectric layer metal plug. The height-to-width ratio gamma of the sub-gate metal plug is less than or equal to 4. Specifically, in the embodiment of the present invention, the aspect ratio γ ═ h of the first sub-gate metal plug 1812:w3＝1。
The first sub-gate metal plug 181 and the first sub-gate metal plug 131 may be made of the same material or different materials. Specifically, in the embodiment of the present invention, the material of the first sub-gate metal plug 181 is the same as the material of the first sub-gate metal plug 131, and is W.
Similarly, after the first sub-gate metal plug 181 is formed, the method further includes: a mechanical planarization process is used to polish the top of the second sub-metal plug 171 to be flush with the top of the first sub-gate metal plug 181.
Referring to fig. 5, a third interlayer dielectric layer 113 is formed adjacent to the second interlayer dielectric layer 112.
As described above, since the metal plug needs to be formed many times, the interlayer dielectric layer needs to be formed many times. And the third interlayer dielectric layer 113 is formed to cover the second sub-metal plug 171 and the first sub-gate metal plug 181.
Similarly, the thickness of the third interlayer dielectric layer 113 is less than or equal to 25 nm. Specifically, in the embodiment of the present invention, the thickness of the third interlayer dielectric layer 113 is 20 nm.
After the third interlayer dielectric layer 113 is formed, similarly, the method further includes: a portion of the third interlayer dielectric layer 113 is removed to form a third plug hole (not shown) and a second gate plug hole (not shown) above the corresponding positions of the second sub-metal plug 171 and the first sub-gate metal plug 181, respectively. Here, the meaning of "corresponding position" is the same as that of the foregoing "position corresponding", and is not described herein again. In the embodiment of the present invention, the third plug hole and the second gate plug hole expose the second sub-metal plug 171 and the first sub-gate metal plug 181, respectively.
After the third plug hole and the second gate plug hole are formed, the method further comprises the following steps: metal is filled into the third plug hole and the second gate plug hole to form a third sub metal plug 191 and a second sub gate metal plug 182, respectively. In the embodiment of the present invention, the material of the third sub-metal plug 191 and the second sub-gate metal plug 182 are the same and are both W.
In the embodiment of the present invention, the third sub-metal plug 191 is connected to the second sub-metal plug 171, and the widths of the two are equal. And the aspect ratio γ of the third sub-metal plug 191 and the second sub-gate metal plug 182 is less than or equal to 4. The third sub-metal plug 191 has an aspect ratio γ h 3:w41. The second sub-gate metal plug 182 has an aspect ratio γ h3:w5＝1。
The widths of the first sub-metal plug 131, the second sub-metal plug 171, and the third sub-metal plug 191 are the same, and the second sub-metal plug 171 is connected to the first sub-metal plug 131 and the third sub-metal plug 191, respectively. Obviously, the dielectric layer metal plugs include a first sub-metal plug 131, a second sub-metal plug 171, and a third sub-metal plug 191.
The second sub-gate metal plug 182 and the first sub-gate metal plug 181 may be made of the same material or different materials. Specifically, in the embodiment of the present invention, the second sub-gate metal plug 182 and the first sub-gate metal plug 181 are made of the same material and are both W. And the gate metal plugs include a second sub-gate metal plug 182 and a first sub-gate metal plug 181.
In the embodiment of the present invention, the second sub-gate metal plug 182 has the same width dimension as the first sub-gate metal plug 181.
In the embodiment of the invention, the metal plug comprises a gate metal plug and a dielectric layer metal plug. By forming three layers of interlayer dielectric layers, forming the sub-metal plug for three times and forming the sub-gate metal plug for two times, the finally formed metal plug is free of holes, and meanwhile, the formed metal plug is relatively compact, so that the conductivity of the metal plug is improved.
It should be noted that, in other embodiments of the present invention, more than three interlayer dielectric layers may be formed, and further more than three sub metal plugs and more than two sub gate metal plugs may be formed. For example, in another embodiment of the present invention, 5 times the interlayer dielectric layer is formed, 5 times the sub-metal plug is formed, and 4 times the sub-gate metal plug is formed, thereby forming the dielectric layer metal plug and the gate metal plug, respectively.
It should be noted that, when the number of layers forming the dielectric layer is more than three, the dielectric layer metal plug includes a plurality of sub-metal plugs, and the gate metal plug includes a plurality of sub-gate metal plugs. And the aspect ratio gamma of the plurality of sub-metal plugs and the plurality of sub-gate metal plugs is less than or equal to 4. And the thickness of the multiple interlayer dielectric layers is less than or equal to 25 nm.
In summary, in the method for forming a metal plug disclosed in the embodiment of the present invention, the metal plug includes a dielectric layer metal plug and a gate metal plug, the dielectric layer metal plug includes a sub-metal plug formed multiple times, and the gate metal plug includes a sub-gate metal plug formed multiple times, so that no hole exists in the formed metal plug, the conduction performance of the metal plug is ensured, the semiconductor device can realize corresponding functions at a lower voltage, and the performance of the semiconductor device is improved.
Accordingly, with continued reference to fig. 4, the present invention further provides a metal plug, including: a semiconductor substrate 100, a first interlayer dielectric layer 111, a gate 120 and a first sub-metal plug 131.
A first interlayer dielectric layer 111 is disposed adjacent to and above the semiconductor substrate 100. The function of the first interlayer dielectric layer 111 is as described above.
The first sub-metal plugs 131 are formed in the first interlayer dielectric layer 111 between the adjacent gates 120, and the function of the first sub-metal plugs 131 is described above.
In the embodiment of the invention, the method further comprises the following steps: a second interlayer dielectric layer 112 and a second sub-metal plug 171.
A second interlevel dielectric layer 112 is disposed adjacent to and above the first interlevel dielectric layer. The second sub-metal plugs 171 are formed in the second interlayer dielectric layer 112. In the embodiment of the present invention, the position of the second sub-metal plug 171 corresponds to the position of the first sub-metal plug 131, and the second sub-metal plug 171 is connected to the first sub-metal plug 131. The second sub-metal plugs 171 and the first sub-metal plugs 131 form dielectric layer metal plugs.
It should be noted that the embodiment of the present invention further includes: the first sub-gate metal plug 181. The first sub-gate metal plug 181 is formed in the second interlayer dielectric layer 112 above the gate electrode 120.
Referring to fig. 5, the embodiment of the invention further includes: a third interlayer dielectric layer 113, a third sub-metal plug 191 and a second sub-gate metal plug 182.
A third interlayer dielectric layer 113 is disposed adjacent to and above the second interlayer dielectric layer 112. The third sub-metal plug 191 is formed in the third interlayer dielectric layer 113, the position of the third sub-metal plug 191 corresponds to the position of the second sub-metal plug 171, and the third sub-metal plug 191 is connected to the second sub-metal plug 171. In the embodiment of the present invention, the dielectric layer metal plugs include a first sub-metal plug 131, a second sub-metal plug 171, and a third sub-metal plug 191. And the first sub-gate metal plug 181 and the second sub-gate metal plug 182 constitute a gate metal plug.
In the embodiment of the invention, the metal plug comprises a dielectric layer metal plug and a gate metal plug.
It should be noted that, in other embodiments of the present invention, the dielectric layer metal plug may further include more than 3 sub-metal plugs, and the gate metal plug may also include more than 3 sub-gate metal plugs, which is not limited herein.
Thus far, the present invention has been described in detail. Some details well known in the art have not been described in order to avoid obscuring the concepts of the present invention. It will be fully apparent to those skilled in the art from the foregoing description how to practice the presently disclosed embodiments.
Although some specific embodiments of the present invention have been described in detail by way of illustration, it should be understood by those skilled in the art that the above illustration is only for the purpose of illustration and is not intended to limit the scope of the invention. It will be appreciated by those skilled in the art that modifications may be made to the above embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.
Claims (21)
1. A method for forming a metal plug, comprising:
forming a first interlayer dielectric layer on a semiconductor substrate, and forming a plurality of grids in the first interlayer dielectric layer;
removing part of the first interlayer dielectric layer to form a first plug hole in the first interlayer dielectric layer between the adjacent grid electrodes;
filling metal into the first plug hole to form a first sub-metal plug;
forming a second interlayer dielectric layer adjacent to the first interlayer dielectric layer, wherein the second interlayer dielectric layer covers the first sub-metal plug;
removing part of the second interlayer dielectric layer to form a second plug hole exposing the first sub-metal plug above the position corresponding to the first sub-metal plug, and simultaneously removing part of the second interlayer dielectric layer above the grid to form a first grid plug hole exposing the grid; and
Filling metal into the second plug hole to form a second sub-metal plug, and filling metal into the first gate plug hole to form a first sub-gate metal plug; the first sub-metal plug is directly connected with the second sub-metal plug;
forming a third interlayer dielectric layer adjacent to the second interlayer dielectric layer, wherein the third interlayer dielectric layer covers the second sub-metal plug and the first sub-gate metal plug;
removing part of the third interlayer dielectric layer to form a third plug hole and a second gate plug hole above the corresponding positions of the second sub-metal plug and the first sub-gate metal plug respectively, and exposing the second sub-metal plug and the first sub-gate metal plug; and
filling metal into the third plug hole and the second gate plug hole to form a third sub-metal plug and a second sub-gate metal plug;
wherein the width of the second sub-metal plug is equal to the width of the first sub-metal plug, the aspect ratio gamma of the second sub-metal plug is less than or equal to 4, and
the third sub-metal plug is connected with the second sub-metal plug, and the width of the third sub-metal plug is equal to that of the second sub-metal plug.
2. The method of claim 1, wherein the metallic material filled into the first plug aperture and/or the second plug aperture comprises W, Al or Cu.
3. The method of forming a metal plug according to claim 1, further comprising, after forming said first plug aperture and before forming said first sub-metal plug: and forming silicide at the bottom of the first plug hole.
4. The method as claimed in claim 3, wherein the silicide material comprises: WSi (Wireless sensor network interface)2、TiSi2、TaSi2One or more of (a).
5. The method of claim 1, wherein prior to filling the first plug hole and the second plug hole with metal, respectively, further comprising: forming a barrier layer covering the inner walls of the first and second plug holes, respectively.
6. The method of claim 5, further comprising, after forming the barrier layer: and forming a seed layer covering the barrier layer.
7. The method as claimed in claim 1, wherein the dielectric layer metal plugs comprise the first sub-metal plugs, the second sub-metal plugs and the third sub-metal plugs.
8. The method as claimed in claim 7, wherein the first sub-gate metal plug is connected to the second sub-gate metal plug to form a gate metal plug.
9. The method as claimed in claim 8, wherein the metal plug comprises the dielectric metal plug and the gate metal plug.
10. The method of claim 1, wherein a thickness of the second interlayer dielectric layer and/or the third interlayer dielectric layer is less than or equal to 25 nm.
11. The method of claim 1, further comprising, after forming the first sub-metal plug: and grinding by adopting a mechanical planarization process to enable the top of the grid electrode to be flush with the top of the first sub-metal plug.
12. The method as claimed in claim 7, further comprising, before forming the third interlayer dielectric layer: and grinding by adopting a mechanical planarization process to enable the top of the second sub-metal plug to be flush with the top of the first sub-gate metal plug.
13. The method as claimed in claim 8, wherein the number of layers forming the interlayer dielectric layer is more than three, and the dielectric layer metal plug is formed to include more than three sub-metal plugs, and the gate metal plug includes more than two sub-gate metal plugs.
14. The method as claimed in claim 13, wherein the dielectric metal plug comprises a plurality of sub-metal plugs, and the gate metal plug comprises a plurality of sub-gate metal plugs.
15. The method as claimed in claim 14, wherein an aspect ratio of the plurality of sub-metal plugs to the plurality of gate metal plugs is γ, γ ≦ 4.
16. The method of claim 15, wherein a thickness of the plurality of interlayer dielectric layers is less than or equal to 25 nm.
17. A metal plug, comprising:
the grid-type semiconductor device comprises a semiconductor substrate, a first interlayer dielectric layer and a plurality of grids, wherein the first interlayer dielectric layer is adjacently arranged above the semiconductor substrate, and the grids are distributed in the first interlayer dielectric layer at intervals;
the first sub-metal plug is formed in the first interlayer dielectric layer between the adjacent grid electrodes;
the second interlayer dielectric layer is adjacently arranged above the first interlayer dielectric layer;
the second sub-metal plug is formed in the second interlayer dielectric layer, the position of the second sub-metal plug corresponds to the position of the first sub-metal plug, and the second sub-metal plug is directly connected with the first sub-metal plug;
The third interlayer dielectric layer is adjacently arranged above the second interlayer dielectric layer;
a third sub-metal plug formed in the third interlayer dielectric layer, the position of the third sub-metal plug corresponding to the position of the second sub-metal plug, and the third sub-metal plug being connected to the second sub-metal plug;
a first sub-gate metal plug; and
the second sub-gate metal plug is formed in the third interlayer dielectric layer, corresponds to the first sub-gate metal plug in position, and is connected with the first sub-gate metal plug;
wherein the width of the second sub-metal plug is equal to the width of the first sub-metal plug, the aspect ratio gamma of the second sub-metal plug is less than or equal to 4, and
the third sub-metal plug is connected with the second sub-metal plug, and the width of the third sub-metal plug is equal to that of the second sub-metal plug.
18. The metal plug according to claim 17, wherein said second sub-metal plug and said first sub-metal plug constitute a dielectric layer metal plug.
19. The metal plug of claim 18, wherein said first sub-gate metal plug is formed in said second interlevel dielectric layer above said gate.
20. The metal plug according to claim 17, wherein the first sub-gate metal plug and the second sub-gate metal plug constitute a gate metal plug, and the dielectric layer metal plug comprises the first sub-metal plug, the second sub-metal plug, and the third sub-metal plug.
21. The metal plug according to claim 20, wherein said metal plug comprises said dielectric layer metal plug and said gate metal plug.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972154A (en) * | 2013-02-01 | 2014-08-06 | 中芯国际集成电路制造(上海)有限公司 | Inserting plug forming method |
| CN105280591A (en) * | 2014-06-12 | 2016-01-27 | 台湾积体电路制造股份有限公司 | Self-aligned interconnect with protection layer |
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| US8901627B2 (en) * | 2012-11-16 | 2014-12-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Jog design in integrated circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103972154A (en) * | 2013-02-01 | 2014-08-06 | 中芯国际集成电路制造(上海)有限公司 | Inserting plug forming method |
| CN105280591A (en) * | 2014-06-12 | 2016-01-27 | 台湾积体电路制造股份有限公司 | Self-aligned interconnect with protection layer |
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