CN110232293A - Based on maximum delay subchain and the minimum delay cascade APUF circuit of subchain - Google Patents
Based on maximum delay subchain and the minimum delay cascade APUF circuit of subchain Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
- G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
Abstract
The present invention relates to field of information security technology, and in particular to based on maximum delay subchain and the minimum delay cascade APUF circuit of subchain.APUF circuit includes: step signal generator block, upper path circuitry module, underpass circuit module and arbitrator module.Upper and lower path circuitry module is made of maximum delay subchain and minimum delay subchain cascade.The maximum delay subchain quantity of upper and lower path circuitry module cascade is identical as minimum delay subchain quantity, and the total quantity of the delay subchain of upper path circuitry module cascade, identical as the total quantity of delay subchain of underpass circuit module cascade.Wherein the moderator of maximum delay subchain is to be or door with door, the moderator of minimum delay subchain.Attack resistance APUF circuit increase it is non-linear, have the advantages that certain anti-attack ability, higher uniqueness and compared with other attack resistance schemes stability decline it is less.
Description
Technical field
The present invention relates to field of information security technology, and in particular to based on maximum delay subchain and minimum delay subchain cascade
APUF circuit.
Background technique
With the development of Internet of Things and Radio Frequency Identification Technology, need to carry out a large amount of data friendship between object and object, people and object
Mutually, how the effective of lightweight carries out the basic problem that authentication is to ensure that Internet of things system safety to physical entity.Object
It is generated in reason unclonable function (physical unclonable function, PUF) extraction ic manufacturing process
Uncontrollable process deviation generates response, since the process deviation of its manufacturing process has inevitable and random uncontrollable spy
Point, the response that the PUF on each chip is generated is different, is considered " chip finger print ".The basic application of PUF is that generation is secret
Key and the certification for carrying out physical entity, since the verification process based on PUF has the characteristics that lightweight, the application in Internet of Things
It also is the research hotspot of PUF and Internet of Things.PUF is generally divided into strong PUF and weak PUF: the excitation response pair quantity of strong PUF and its
The area exponentially grade relationship of circuit, and the excitation response pair quantity of weak PUF is directly proportional to its circuit area.Therefore PUF is general by force
It applies during light-weight authentication, and weak PUF is typically employed in and generates in code key and identity.
Moderator PUF (Arbiter PUF, APUF) is a kind of strong PUF being widely studied, the structure of standard APUF circuit
As shown in Figure 1.Standard APUF circuit includes step signal generator, delay subchain, moderator.Wherein, delay subchain constitutes two
Signal paths are upper access and underpass respectively.Step signal generator standard APUF circuit head end, to delay subchain
Two signal paths simultaneously provide a rising edge step signal；Moderator prolongs in the end of standard APUF circuit, reception
The output signal of two signal paths of Shi Zilian.For eventually arriving at the two paths of signals of moderator, it is compared by moderator
Speed, when the signal of upper access is first reached than the signal of underpass, moderator output 1, otherwise export 0.
Delay subchain is composed in series by n grades of delay units, and the structure of delay units at different levels by two two as shown in Fig. 2, selected
One selector composition.Every grade of delay unit has upper input port, lower input port, upper output port, lower output port and excitation
Input port；Upper input port, the lower input port of 1st grade of delay unit receive step signal respectively；N-th grade of delay unit
Upper output port, lower output port are to moderator output signal；Upper input port, the lower input terminal of remaining delay unit at different levels
Mouth is separately connected upper output port, the lower output port of upper level delay unit；The excitation input port of delay units at different levels connects
Receive pumping signal.Specific path of the signal from input port to output port by being applied to two two simultaneously in every grade of delay unit
Select the pumping signal Ci on a selector to determine: when Ci is 0, upper input port, lower input port received signal are with straight line
Path reaches upper output port and lower input port by selector respectively；Work as CiWhen being 1, upper input port, lower input port
Received signal reaches lower output port and upper input port by selector respectively with crossedpath.Therefore pumping signal Ci can
The reconstruct of realizing route, with the variation of excitation, standard APUF circuit configurable 2nKind path.
The circuit structure of two signal paths is full symmetric up and down in standard APUF circuit, but since circuit manufactures
Technique, the delay of upper and lower path can generate small uncontrollable difference, cause the delay of upper and lower two signal paths different, therefore
The process that moderator generates response is just extracted the difference of circuit fabrication process.Again because the path of APUF arrival moderator is can
With what is reconstructed according to excitation, therefore n grades of APUF has 2nKind excitation response pair, so APUF is a kind of strong PUF.
The research hotspot of present APUF first is that safety because total be delayed of upper and lower path is by delays at different levels in APUF
Linear superposition forms, so a kind of mathematical model of simple linear superposition can be established to APUF, attacker only needs to collect
Small part excitation response pair recycles the algorithm of machine learning to learn to obtain the parameters of linear model, and attacker has been at this time
Through the behavior of software simulation PUF can be used, it is equivalent to and has cloned a PUF circuit, PUF has safety no longer, existing to grind
Study carefully and shows that 64 grades can be directed in the case where only needing 400 excitation response pairs using linear model and evolution strategy algorithm
APUF reach 95% or more success attack rate.
Summary of the invention
To solve problems of the prior art, the present invention is proposed based on maximum delay subchain and minimum delay subchain grade
The APUF circuit of connection improves the anti-modeling attacking ability of APUF circuit, when in face of machine learning modeling attack, has compared with high safety
Property.
In order to solve the above technical problems, the present invention proposes following technical scheme:
It is proposed by the present invention to be based on maximum delay subchain and the minimum delay cascade APUF circuit of subchain, it is a kind of attack resistance
APUF circuit, comprising: step signal generator block, upper path circuitry module, underpass circuit module and arbitrator module.Its
In, upper path circuitry module is to cascade the upper access constituted, underpass circuit mould by maximum delay subchain and minimum delay subchain
Block is to cascade the underpass constituted by maximum delay subchain and minimum delay subchain.
The upward path circuitry module of step signal generator block, underpass circuit module provide step signal simultaneously, secondary
The step signal that device module receives the step signal through upper tunnel and transmits through underpass is cut out, arbitrator module is relatively up and down
The speed of two access output signals, when the output signal of the output signal ratio underpass of upper access first reaches, moderator output
1,0 is otherwise exported, the output result of arbitrator module is the output signal of APUF circuit.
In upper path circuitry module, there are two types of the transmission paths of step signal: the first path is to first pass through maximum delay
Subchain passes through minimum delay subchain again, and second of path is to first pass through minimum delay subchain to pass through maximum delay subchain again；It is lower logical
In the circuit module of road, there are two types of the transmission paths of step signal: the first path is to first pass through maximum delay subchain to pass through again most
Small delay subchain, second of path are to first pass through minimum delay subchain to pass through maximum delay subchain again.
To ensure PUF response stability, the maximum delay subchain quantity of upper path circuitry module cascade and minimum delay
Subchain quantity is identical, and the maximum delay subchain quantity of underpass circuit module cascade is identical as minimum delay subchain quantity, and
And the total quantity of the maximum delay subchain of upper path circuitry module cascade and minimum delay subchain, in underpass circuit module
Cascade maximum delay subchain is identical with the minimum delay total quantity of subchain.
Wherein, the circuit structure of maximum delay subchain is consistent with standard APUF circuit structure, includes delay subchain, arbitration
Device.Wherein, delay subchain be composed in series by n grades of delay units, every grade of delay unit have upper input port, lower input port, on
Output port, lower output port and excitation input port, delay subchain constitute two signal paths, are the first access and the respectively
Two accesses.The step signal of rising edge is input to the first access and alternate path of delay subchain simultaneously, and final output is to secondary
Cut out device.Moderator is and door.When the signal of the first access of the subchain that is delayed and alternate path becomes 1 entirely, the output of moderator
It just can be 1, for this explanation when a most slow step signal reaches, output can just be set 1 by maximum delay subchain, and maximum is prolonged at this time
The whole delay of Shi Zilian is the maximum delay in the first access and alternate path.
The circuit structure of minimum delay subchain is consistent with standard APUF circuit structure, includes delay subchain, moderator.Its
In, delay subchain is composed in series by n grades of delay units, and every grade of delay unit has upper input port, lower input port, upper output end
Mouth, lower output port and excitation input port.The subchain that is delayed constitutes two signal paths, is third path and four-way respectively
Road.The step signal of rising edge is input to the third path and fourth passage of delay subchain simultaneously, and final output is to moderator.
Moderator is or door.When arbitrarily signal becomes 1 all the way in the third path and fourth passage of the subchain that is delayed, the output of moderator
It will be 1, for this explanation when a most fast signal reaches, output can just be set 1 by minimum delay subchain, at this time minimum delay
The whole delay of chain is the minimum delay in third path and fourth passage.
Also, the delay size of the arbitrary signal access of maximum delay subchain or minimum delay subchain, is manufactured by circuit
Technique generate difference and determine, be uncertain.
It is delayed in the cascade APUF circuit of subchain proposed by the present invention based on maximum delay subchain and minimum, maximum delay
Subchain is k with minimum delay subchain cascade series, and every grade of delay subchain is composed in series by n grades of delay units, therefore is entirely resisted and attacked
The sum for hitting delay unit in APUF circuit is m=k × n, and wherein k, m, n are positive integer, and k is the even number not less than 2.
Further, arbitrator module uses d type flip flop.
Proposed by the present invention based in maximum delay subchain and the minimum delay cascade APUF circuit of subchain, believe up and down
Number access is formed by maximum delay subchain and k grades of minimum delay subchain multi-stage cascades, and each delay subchain has two bars
Access, therefore there are many combinations for the final Actual path for being transported to the two paths of signals in arbitrator module in each delay subchain.
Moreover, delay is the maximum delay in two accesses of subchain for maximum delay subchain；For minimum delay subchain
For, delay is the minimum delay in two accesses of subchain, therefore, the two paths of signals being finally transported in arbitrator module
Delay parameter be not fully linear superposition.
Beneficial effect
The invention adopts the above technical scheme compared with prior art, has the following technical effect that
1, the present invention is by using maximum delay subchain and the minimum delay cascade design scheme of subchain is based on, to APUF electricity
Be added in line structure it is non-linear, to improve anti-modeling attacking ability.
2, other attack resistance structures, such as exclusive or APUF, feedforward APUF are compared, it is less that PUF responds reduced stability.
3, comparison with standard APUF, the response of generation is related to more delay unit numbers, has better uniqueness.
Detailed description of the invention
Fig. 1 is standard APUF electrical block diagram.
Fig. 2 is standard APUF delay unit structural schematic diagram.
Fig. 3 be the maximum delay subchain proposed by the present invention based on door, based on or door minimum delay subchain circuit
Structural schematic diagram.
Fig. 4 is the APUF circuit structure proposed by the present invention based on maximum delay subchain and minimum delay subchain two-stage cascade
Schematic diagram.
Specific embodiment
Present invention is further described in detail with specific embodiment with reference to the accompanying drawing.
Specific embodiment 1:
Fig. 3 be the maximum delay subchain proposed by the present invention based on door, based on or door minimum delay subchain circuit
Structural schematic diagram.
Based on the maximum delay subchain 20 with door, circuit structure and standard APUF shown in FIG. 1 electricity shown in Fig. 3 (a)
Line structure is consistent, includes delay subchain 21, moderator 22.Wherein, delay subchain 21 is composed in series by n grades of delay units 10, such as
Shown in Fig. 2, every grade of delay unit 10 has upper input port, lower input port, upper output port, lower output port and excitation input
Port, delay subchain 21 constitute two signal paths, are the first access A and alternate path B respectively.The step signal of rising edge is same
When be input to the first access A and alternate path B of delay subchain 21, and final output is to moderator 22.Moderator 22 is and door.
When the signal of the first access A and alternate path B of the subchain 21 that is delayed become 1 entirely, the output of moderator 22 just can be 1, this says
Bright when a most slow step signal reaches, output can just be set 1 by maximum delay subchain 20, at this time maximum delay subchain 20
Whole delay is the maximum delay in the first access A and alternate path B.
Shown in Fig. 3 (b) based on or door minimum delay subchain 30, circuit structure and standard APUF shown in FIG. 1 electricity
Line structure is consistent, includes delay subchain 31, moderator 32.Wherein, delay subchain 31 is composed in series by n grades of delay units 10, such as
Shown in Fig. 2, every grade of delay unit 10 has upper input port, lower input port, upper output port, lower output port and excitation input
Port.The subchain 31 that is delayed constitutes two signal paths, is third path C and fourth passage D respectively.The step signal of rising edge is same
When be input to the third path C and fourth passage D of delay subchain 31, and final output is to moderator 32.Moderator 32 is or door.
When arbitrarily signal becomes 1 all the way in the third path C and fourth passage D of the subchain 31 that is delayed, the output of moderator 32 all can be
1, for this explanation when a most fast signal reaches, output can just be set 1 by minimum delay subchain 30, at this time minimum delay subchain 30
Whole delay be minimum delay in third path C and fourth passage D.
Also, the delay size of the arbitrary signal access of maximum delay subchain 20 or minimum delay subchain 30, by circuit
Manufacturing process generate difference and determine, be uncertain.
Specific embodiment 2:
Fig. 4 is the APUF circuit structure proposed by the present invention based on maximum delay subchain and minimum delay subchain two-stage cascade
Schematic diagram.The APUF circuit includes: step signal generator block 100, upper path circuitry module 200, underpass circuit module
300 and arbitrator module 400.Wherein, upper path circuitry module 200 is by maximum delay subchain 20 and minimum 30 grades of subchain of delay
Join the upper access X constituted, underpass circuit module 300 is made of maximum delay subchain 20 and minimum delay subchain 30 cascade
Underpass Y, arbitrator module 400 use d type flip flop.
The upward path circuitry module 200 of step signal generator block 100, underpass circuit module 300 provide rank simultaneously
Jump signal, and arbitrator module 400 receives the step signal transmitted through upper access X and the step signal transmitted through underpass Y, arbitration
Device module 400 compares the speed of two access output signals up and down, when the output signal of the output signal ratio underpass Y of upper access X
When first reaching, otherwise moderator output 1 exports 0, the output result of arbitrator module is the output signal of APUF circuit.
In upper path circuitry module 200, there are two types of the transmission paths of step signal: the first path is to first pass through maximum to prolong
For Shi Zilian 20 again by the minimum subchain 30 that is delayed, second of path is to first pass through minimum delay subchain 30 again by maximum delay
Chain 20；In underpass circuit module 300, there are two types of the transmission paths of step signal: the first path is to first pass through maximum delay
For subchain 20 again by the minimum subchain 30 that is delayed, second of path is to first pass through minimum delay subchain 30 again by maximum delay subchain
20。
To ensure PUF response stability, 20 quantity of maximum delay subchain and minimum of upper 200 cascade of path circuitry module
30 quantity of subchain that is delayed is identical, 20 quantity of maximum delay subchain of 300 cascade of underpass circuit module and minimum delay subchain
30 quantity are identical, and the sum of the maximum delay subchain 20 of upper 200 cascade of path circuitry module and minimum delay subchain 30
Amount is identical as the maximum delay subchain 20 of 300 cascade of underpass circuit module and the minimum delay total quantity of subchain 30.
Circuit shown in Fig. 4, as a preferred solution of the present invention, wherein maximum delay subchain and most lower delay subchain
Series k=2 is cascaded, and the total series m of delay unit in entire APUF circuit is determined by the number of the pumping signal applied, it is fixed
Adopted m=64, then being composed in series delay unit the quantity n=m/k, i.e. n=32 of maximum delay subchain or minimum delay subchain.
From fig. 4, it can be seen that for the APUF circuit structure of maximum delay subchain and minimum delay subchain two-stage cascade, when
When not applying pumping signal, since cascade maximum delay subchain 20 and minimum delay subchain 30 respectively have two bars channels, because
This, the inside of upper path circuitry module 200 is practical 4 bars channels, and the inside of underpass circuit module 300 actually also has 4
Bars channel.Therefore, comparison with standard APUF circuit structure, maximum delay subchain proposed by the present invention and minimum delay subchain two
The cascade circuit structure of grade has increased modeling complexity, improves the attack tolerant of circuit structure.And so on, according to electricity
The demand of road application environment increases cascade series k (k is the even number not less than 2), as attack resistance APUF to a certain extent
When in circuit using k grades of maximum delay subchains and minimum delay subchain cascade, i.e., there are k/2 grades of maximums to prolong in upper path circuitry module
There are k/2 grades of maximum delay subchains and k/2 grades of minimums in Shi Zilian and k/2 grades of minimum delay subchain cascades, underpass circuit module
The subchain that is delayed cascade, be finally conveyed at this time the subchain physical channel that the two paths of signals of arbitrator module is passed through will be difficult to it is pre-
It surveys, significantly increases modeling complexity.
Further, when using maximum delay subchain and minimum delay subchain multi-stage cascade in attack resistance APUF circuit,
Step signal eventually arrives at moderator, required delay continuously across a plurality of maximum delay subchain or a plurality of minimum delay subchain
For the superposition of whole subchains delay.For any one delay subchain, delay is a certain bars in the delay subchain
The specific delay of access, determinant include: the received pumping signal of delay subchain, are composed in series prolonging for the delay subchain
Shi Danyuan, the delay subchain are maximum delay subchain or minimum delay subchain.In addition, the selection of subchain signal path not only with
Pumping signal is related, also related with itself process deviation of subchain.Therefore, by attack resistance APUF circuit knot proposed by the present invention
Structure, under different excitations, the specific path for the delay subchain finally passed through by the two paths of signals that arbitrator module is arbitrated
It is that user and attacker institute are unascertainable, in other words, when attacker's attack is based on maximum delay subchain and minimum delay
When the APUF circuit of chain multi-stage cascade, accurately model could be obtained by needing to be arranged more delay parameters, and these are delayed
Parameter is not fully linear superposition, can just obtain one by comparing after the delay parameter superposition in multiple paths in the subchain that is delayed
The delay of a delay subchain.Therefore, based on maximum delay subchain and the minimum delay cascade APUF circuit comparison with standard of subchain
APUF has the ability of stronger anti-modeling attack.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (7)
1. based on maximum delay subchain and the minimum delay cascade APUF circuit of subchain, it is characterised in that:
The APUF circuit, comprising: step signal generator block, upper path circuitry module, underpass circuit module and arbitration
Device module, wherein upper path circuitry module is to cascade the upper access (X) constituted by maximum delay subchain and minimum delay subchain,
Underpass circuit module is to cascade the underpass (Y) constituted by maximum delay subchain and minimum delay subchain；
The upward path circuitry module of step signal generator block, underpass circuit module provide step signal, moderator simultaneously
Module receives step signal transmit through upper access (X) and the step signal through underpass (Y) transmission, arbitrator module relatively on
The speed of lower two access output signals, it is secondary when the output signal of the output signal ratio underpass (Y) of upper access (X) first reaches
Device output 1 is cut out, otherwise exports 0, the output result of arbitrator module is the output signal of APUF circuit.
2. according to claim 1 based on maximum delay subchain and the minimum delay cascade APUF circuit of subchain, feature
Be: in the upper path circuitry module, there are two types of the transmission paths of step signal: the first path is to first pass through maximum delay
Subchain passes through minimum delay subchain again, and second of path is to first pass through minimum delay subchain to pass through maximum delay subchain again.
3. according to claim 1 based on maximum delay subchain and the minimum delay cascade APUF circuit of subchain, feature
Be: in the underpass circuit module, there are two types of the transmission paths of step signal: the first path is to first pass through maximum delay
Subchain passes through minimum delay subchain again, and second of path is to first pass through minimum delay subchain to pass through maximum delay subchain again.
4. according to claim 1 based on maximum delay subchain and the minimum delay cascade APUF circuit of subchain, feature
Be: the maximum delay subchain quantity of upper path circuitry module cascade is identical as minimum delay subchain quantity, underpass circuit
The maximum delay subchain quantity of module cascade is identical as minimum delay subchain quantity；Also, upper path circuitry module cascade
Delay subchain total quantity it is identical as the total quantity of delay subchain of underpass circuit module cascade.
5. as claimed in any of claims 1 to 4 cascade based on maximum delay subchain and minimum delay subchain
APUF circuit, it is characterised in that: the circuit structure of the maximum delay subchain is consistent with standard APUF circuit structure, includes delay
Subchain, moderator, wherein delay subchain be composed in series by n grades of delay units, every grade of delay unit have upper input port, under it is defeated
Inbound port, upper output port, lower output port and excitation input port, delay subchain constitute the first access (A) and the of signal
Two accesses (B), moderator are and door；
The step signal of rising edge is input to the first access (A) and alternate path (B) of delay subchain simultaneously, and final output arrives
Moderator, when the first access (A) for the subchain that is delayed and the output signal of alternate path (B) become 1 entirely, i.e., ought be most slow one
When step signal reaches moderator, the output of moderator just can be 1, i.e. output can just be set 1 by maximum delay subchain, at this point, most
The whole delay of big delay subchain is the maximum delay in the first access (A) and alternate path (B).
6. as claimed in any of claims 1 to 4 cascade based on maximum delay subchain and minimum delay subchain
APUF circuit, it is characterised in that: the circuit structure of the minimum delay subchain is consistent with standard APUF circuit structure, includes delay
Subchain, moderator, wherein delay subchain be composed in series by n grades of delay units, every grade of delay unit have upper input port, under it is defeated
Inbound port, upper output port, lower output port and excitation input port, delay subchain constitute the third path (C) and the of signal
Four accesses (D), moderator are or door；
The step signal of rising edge is input to the third path (C) and fourth passage (D) of delay subchain simultaneously, and final output arrives
Moderator, when be delayed subchain third path (C) and fourth passage (D) in arbitrarily signal becomes 1 all the way when, i.e., ought be most fast one
When a step signal reaches moderator, the output of moderator all can be 1, i.e., output can just be set 1 by minimum delay subchain, at this point,
The whole delay of minimum delay subchain is the minimum delay in third path (C) and fourth passage (D).
7. according to claim 1 based on maximum delay subchain and the minimum delay cascade APUF circuit of subchain, feature
Be: arbitrator module uses d type flip flop.
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| CN112019347A (en) * | 2020-08-20 | 2020-12-01 | 东南大学 | Lightweight security authentication method based on XOR-APUF |
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| MENG LI 等: "Practical public PUF enabled by solving max-flow problem on chip", 《2016 53ND ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC)》 * |
| 李冰 等: "基于SRAM 物理不可克隆函数的高效真随机种子发生器设计", 《电子与信息学报》 * |
| 王若男: "基于FPGA的仲裁PUF技术研究", 《中国优秀硕士学位论文全文数据库 信息科技辑》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112019347A (en) * | 2020-08-20 | 2020-12-01 | 东南大学 | Lightweight security authentication method based on XOR-APUF |
| CN112019347B (en) * | 2020-08-20 | 2022-08-16 | 东南大学 | Lightweight security authentication method based on XOR-APUF |
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