CN1102261C - BCH sign encode, decode and multiple error-correcting device based on group transform method - Google Patents

Abstract

The present invention relates to a BCH symbolic coding-decoding and multiplex error-correcting device series formed in a group transform method, namely an error-correcting semiconductor device which is formed by utilizing BCH codes and has the function of correcting multiplex errors. A series of BCH code encoders designed according to the number of transmitted bits and the number of multiplex errors are used for outputting BCH codes, and a corresponding BCH code decoding error-correcting device specially designed can automatically detect and correct errors in signal communication after receiving the BCH codes. An encoding and decoding method originally realized by a computer can be completed by one to two integrated circuits. The present invention reliably realizes high performance and low cost and can be widely used for various fields.

Description

BCH symbolic coding, decoding, multiple error-correcting device that group transform method constitutes

The invention belongs to be used for wideband territory CDMA spectrum-expanding communication system in, the large-scale semiconductive device.The present invention is the up-to-date series electronic device towards 21st century.

In digital communication, to the detection of multiple random error and the conventional method of error correction be: own orthogonal symbol (Self-orthogonal code) method and BCH symbol in the convolutional code, i.e. BCH code [1] (Bose-Chaudhuri-Hocgaenghem Code) method.Relatively, the numeric code rate of BCH code will be higher than convolutional code between the two.

Use BCH code, can judge the position (being decoding problem or multiple number method) that multiple random error takes place, in addition error correction.The method of conventional and famous judgement is: Peterson method [2], Berlekamp-Massey method [3], Chien ' Search[3] the synthetic and multiple number method [4] of the shift LD apparatus of method James L.Massey.To the BCH code number of answering, it calculates quite complicated, generally must rely on COMPUTER CALCULATION with this several method.When random error took place when particularly 32 of 3 heavy above and code word lengths were above, amount of calculation can increase greatly.The number of the unknown number of finding the solution is calculated as follows:

(n，t)＝(n！)/((n-t)！*t！)

N is a symbol lengths that transmits word, and t is some heavy error number.When being 62 as n,

t＝1，(62，1)＝62

t＝2，(62，2)＝61*62/2＝1891

t＝4，(62，4)＝59*60*61*62/(2*3*4)＝557845

T random error detected the conventional computer algorithm to be had: Newtow ' s identical relation, the Vandermonde determinant, error location polynomial (error cocation polynomial), mistake numerical value polynomial expression (error evaluationpolynomial) etc., because unknown number huge amount, if find the solution unknown number with above all kinds of methods, bring into use from BCH code is to find the solution unknown number with mass computing computer large-scale matrix so far always, uses to only limit to use in the dark cosmic communication [5].

The present invention promptly is the weak point at the multiple number method of existing BCH code, be that amount of calculation is too big, must use mainframe computer to find the solution designs, adopt the novel algorithm of group translating, design the Code And Decode error correction semiconductor devices series of special-purpose BCH symbol, only use the integrated circuit of two correspondences, can finish coding and decoding and error problem, expanded the range of application of BCH code widely BCH code.

The object of the present invention is achieved like this, at first, need not above cited determinant, identical relation, polynomial expression, but in Galois (Galois) Galois field (in the group theory, being the Galois body), generation ranks and inspection ranks to BCH code carry out the finite group conversion, group translating refers to common row, column vector transformation, and mirror is to conversion, rotational transform.To generate the ranks of ranks and inspection row-column transform Cheng Jiyue platform shape (reduced echelon form) line, the end that find the solution knows that number just is included in the relativeness of checking ranks.If two wrong generations are arranged, respectively at the 18th during with 48 bit positions, the symptom value of the 18th and the 48th generation with check going vectorial equating that ranks the 18th row and the 48th goes.Unknown number is included in the relativeness of checking ranks like this, and this is an important feature.Another important feature is, checks that the length of ranks can be compressed according to transmitting data length, and these two characteristics are inventions of theoretical side.

Then, put into custom-designed BCH code scrambler with generating ranks behind the group translating with the inspection ranks, can design a series of BCH code scramblers according to figure place that is transmitted and multiple wrong number, the BCH code of output binary coding form, after this yard received by the BCH code decoding and error device of custom-designed correspondence, can detect and correct the mistake in the signal communication automatically.The semiconductor devices specification of present patent application has: the random error position is from 1 to 9, and word length is from 7 to 1023 seriation semiconductor devices (seeing that group transform method constitutes the multiple error-detecting of BCH code, error-correcting device specification table).

Below in conjunction with accompanying drawing invention is described in detail.Fig. 1 is that Fig. 2 is a BCH code scrambler block diagram with the communication sketch plan of BCH code error correction, and Fig. 3 is the decoding and error device block diagram of BCH code.

Scrambler, demoder, the error-corrector position in signal path is described out among Fig. 1.Signal arrives first the scrambler of BCH code from binary-coded signal source among the figure, and its output is the BCH code of binary coding form.Form with BCH code sends to the signal destination, and the multiple interference source in the transmission in the signal path may disturb the signal in the communications, produces digital mistake.Pass through BCH code decoding and error device during reception earlier.The major function of BCH code decoding and error device is the Bose-Chaudhuri-Hocquenghem Code generation symptom value according to input binary coding form.The positional value that locates errors and take place according to the symptom value is corrected again.Be sent to binary-coded signal source destination again through the signal after the decoding and error.Conciliate logical error-corrector owing to added the scrambler of BCH code, signal of communication is satisfactorily transmitted and error correction.

Illustrate the principle and the structure of this invention below.

The symbol lengths that for example transmits word is 63, and 2 heavy wrong inspection ranks are: (the not inspection ranks before the conversion)

α is an element in the Galois body

After the finite group conversion, check the ranks H^ of row-column transform Cheng Jiyue platform shape line =[P, I ₁₂] ^T

This is one 63 row, the matrix ranks of 12 row.Wherein P is the even number ranks, I ₁₂Be the unit ranks on 12 rank.Recompress one and just become 62 row, the matrix ranks of 12 row.

What Fig. 2 described is the structural drawing block diagram of scrambler.Among the figure

The 1st, common shift register is the input data register, and its length is variable, equal to transmit binary-coded signal source data length, as transmitting 50 binary signal source datas, then the length of register is exactly 50, and what deposited the centre is exactly one the 50 long data of binary digit.The shift register length of present patent application is that 7 binary digits are to 1023 binary digits.

The 2nd, common memory is the coding memory.What deposited the centre is the value of the BCH code generation ranks after the conversion.Its width is by multiple improper value decision, and its length is by transmitting binary-coded signal source data length decision.As transmitting 50 binary signal source datas, double error-detecting is arranged and correct function, then the width of memory is 12, length is 50.The memory length of present patent application is to 1023 binary digits from 7 binary digits.

The 3rd, common multiplier, the multiplier of input end are the values that generates ranks in the memory, and multiplicand is the value of shift register.Amass and deliver to the next shift register from output terminal.

The 4th, shift register is the BCH code check register, and its length is by multiple improper value decision, and is consistent with the width of memory.As transmitting 50 binary signal source datas, double error-detecting is arranged and correct function, then the BCH code register is 12.

The 5th, time schedule controller.Finish the control of scrambler.What last transmission was exported is the binary coded data of importing in data register and the BCH code register.

What Fig. 3 described is the structural drawing block diagram of demoder, error-corrector.This is that a code word length is 62, has double mistake to correct the block diagram of function, among the figure

6 and 8 is address counters of memory, is address counter.It has two effects, and the one, use as address counter, the 2nd, the positional value that points out faults and take place.

7 and 9 is memories, is the decoding memory.What wherein deposit is the value of the inspection ranks behind the group translating, and the width of memory is by multiple improper value decision, and its length is by transmitting binary-coded signal source data length decision.As transmitting 50 binary signal source datas, double error-detecting is arranged and correct function, then the width of memory is 12, length is 62.The memory length of present patent application is that 7 binary digits are to 1023 binary digits.

The 10th, multiplier multiplies each other the value of checking ranks in data and the memory of input, generation symptom value.

The 11st, the symptom value register.The symptom value is the multiple wrong information that takes place of reflection.Its length is by multiple improper value decision, and is consistent with the width of memory.As transmitting 50 binary signal source datas, double error-detecting is arranged and correct function, then symptom value register length is 12.

The 12nd, totalizer.

The 13rd, comparer.Symptom value and each vector value sum of checking ranks are compared, and when the two was equal, the tagging position was 1.

The 14th, marker bit.Length is 1.When marker bit is 1, illustrate that the multiple wrong positional value that takes place finds, respectively in the address counter of memory.

The 15th, time schedule controller.Finish control to demoder and error-corrector.

16 and 18 is code translators, translates the multiple wrong positional value that takes place according to the number in the address counter of memory.

The 17th, shift register is the input data register, and what put into is the input data.

19 and 20 is the position error-correcting devices that constitute with door and phase inverter.According to marker bit be 1 and address decoder translate the positional value that a certain bit-errors takes place, negated in a certain bit value position.

The work overall process of demoder, error-corrector is:

Receive the data of a Bose-Chaudhuri-Hocquenghem Code, in the information drive access, multiple mistake is sneaked into wherein:

--→ receive the data of a Bose-Chaudhuri-Hocquenghem Code removed the BCH code check bit, and remaining valid data are put into shift register 17, and each vector value of the inspection ranks in the data of this reception simultaneously and the memory 7 multiplies each other, and it is long-pending for the symptom value, puts into symptom value register 11.

--→ time schedule controller is by each vector value summation of respectively checking ranks in memory 7 and 9, allow and with the symptom value relatively, when the two is equal, stop, the tagging position is 1.

--→ translate positional value and the marker bit that a certain bit-errors takes place according to code translator 16 and 18 is 1 this two condition, position error- correcting device 19 and 20 pairs of corresponding wrong data bit are carried out complementary operation (error-correction operation). and operating process is serial operation, and the data of exporting from error-correcting device 20 are data of process decoding and error correction.

In digital communication widely, BCH code scrambler and BCH code demoder error-corrector can detect and correct the multiple random error in the information transmission communication.On using, can be widely used in high performance communication system, automatic control system, various fields such as computer network system, device is easy to be reliable, and performance improves greatly, and economic effect is considerable.

In the diffCDMA spectrum-expanding communication system [6] at present, we have used the mainframe computer simulated experiment quite successful, and random error is from 1 to 9 when following when code word length is 1023, and random error detects and the error correction experiment, and the result is all correct, desirable.

This novel semi-conductor device will be used widely in control system with in the computer network system.

Main reference document: [1] R.C.Bose ﹠amp; D.K.Ray-Chaudhuri " On a class of error errorcorrecting binary group codes ", Information and Control, 3, pp.279～290, March 1960.[2] " signed theory ", work such as high loyal hero, Japan コ ロ Na society publishes [3] John B.Anderson " SOURCE AND CHANNEL CODING " Kluwer Academic Publishers, Boston/Dordrecht/Lonton[4] James L.Massey, " Shift Register Synthesis and BCH Decoding ", IEEE Transactions on Information Theory, Vol.rr-15, No.1.January 1969.[5] " ス ペ Network ト Le diffusion communication シ ス テ system " Hengshan Mountain light hero, the Kuixi Yin ﹠amp of Japanese science tech publishing house [6]; Masahichi Kishi " The high capacity and high speed diffCDMA with the BBCH double error correction and continuous phase primary modulation ", IEEE PRIMR99, Sep.99, No:KO-0172, Osaka, Japan.

Group transform method consists of the multiple error detection of BCH code, error-correcting device specification table

＜unit bit position 〉

Specification: 1～9 of the number that random error occurs, 7～1023 of code word lengths.

The position on # hurdle is long to be to have compressibility, is maximal value in the table.

The device of a specification of each behavior

The information bit specification			BCH code scrambler specification			BCH code demoder, error-corrector specification
										The long # in character code position	The long # of data bit	Random error number (individual)	The input data register long # in position	BCH code check register-bit is long	The long # of the long width bits of coding memory	The input data register long # in position	Symptom value register position is long	The address counter position is long	The long # of the long width bits of decoding memory
7	4	1	4	3	4*3	4	3	3	7*3
										15	11	1	11	4	11*4	11	4	4	15*4
15	7	2	7	8	7*8	7	8	4	15*8
										15	5	3	5	10	5*10	5	10	4	15*10
31	26	1	26	5	26*5	26	5	5	31*5
										31	21	2	21	10	21*10	21	10	5	31*10
31	16	3	16	15	16*15	16	15	5	31*15
										31	11	4	11	20	11*20	11	20	5	31*20
31	6	5	6	25	6*25	6	25	5	31*25
										63	57	1	57	6	57*6	57	6	6	63*6
63	51	2	51	12	51*12	51	12	6	63*12
										63	45	3	45	18	45*18	45	18	6	63*18
63	39	4	39	24	39*24	39	24	6	63*24
										63	36	5	36	27	36*27	36	27	6	63*27
63	30	6	30	33	30*33	30	33	6	63*33
										63	24	7	24	39	24*39	24	39	6	63*39
63	18	8	18	45	18*45	18	45	6	63*45
										63	16	9	16	47	16*47	16	47	6	63*47
127	120	1	120	7	120*7	120	7	7	127*7
										127	113	2	113	14	113*14	113	14	7	127*14
127	106	3	106	21	106*21	106	21	7	127*21
										127	99	4	99	28	99*28	99	28	7	127*28
127	92	5	92	35	92*35	92	35	7	127*35
										127	85	6	85	42	85*42	85	42	7	127*42
127	78	7	78	49	78*49	78	49	7	127*49
										127	71	8	71	56	71*56	71	56	7	127*56
127	64	9	64	63	64*63	64	63	7	127*63
										255	247	1	247	8	247*8	247	8	8	255*8
255	239	2	239	16	239*16	239	16	8	255*16
										255	231	3	231	24	231*24	231	24	8	255*24

The information bit specification			BCH code scrambler specification			BCH code demoder, error-corrector specification
										The long # in character code position	The long # of data bit	Random error number (individual)	The input data register long # in position	BCH code check register position is long	The long # of the long width bits of coding memory	The input data register long # in position	Symptom value register position is long	The address counter position is long	The long # of the long width bits of decoding memory
255	223	4	223	32	223*32	223	32	8	255*32
										255	215	5	215	40	215*40	215	40	8	255*40
255	207	6	207	48	207*48	207	48	8	255*48
										255	199	7	199	56	199*56	199	56	8	255*56
255	191	8	191	64	191*64	191	64	8	255*64
										255	187	9	187	68	187*72	187	72	8	255*72
511	502	1	502	9	502*9	502	9	9	511*9
										511	493	2	493	18	493*18	493	18	9	511*18
511	484	3	484	27	484*27	484	27	9	511*27
										511	475	4	475	36	475*36	475	36	9	511*36
511	466	5	466	45	466*45	466	45	9	511*45
										511	457	6	457	54	457*54	457	54	9	511*54
511	448	7	448	63	448*63	448	63	9	511*63
										511	439	8	439	72	439*72	439	72	9	511*72
511	430	9	430	81	430*81	430	81	9	511*81
										1023	1013	1	1013	10	1013*10	1013	10	10	1023*10
1023	1003	2	1003	20	1003*20	1003	20	10	1023*20
										1023	993	3	993	30	993*30	993	30	10	1023*30
1023	983	4	983	40	983*40	983	40	10	1023*40
										1023	973	5	973	50	973*50	973	50	10	1023*50
1023	963	6	963	60	963*60	963	60	10	1023*60
										1023	953	7	953	70	953*70	953	70	10	1023*70
1023	943	8	943	80	943*80	943	80	10	1023*80
										1023	933	9	933	90	933*90	933	90	10	1023*90

Claims (3)

1. BCH symbolic coding of utilizing group translating to constitute, decoding, the multiple error-correcting method, in digital communication, to the detection of multiple random error and the better method of error correction is the BCH code method, this method is promptly further made group translating to BCH code, utilize it to have the function that multiple mistake is corrected, automatically the mistake in the signal communication is detected and corrects, it is characterized in that in the Galois Galois field, generation ranks and inspection ranks to BCH code carry out the finite group conversion, the ranks of ranks and inspection row-column transform Cheng Jiyue platform shape line will be generated, then, put into custom-designed BCH code scrambler with generating ranks behind the group translating with the inspection ranks, a series of BCH code scramblers according to figure place that is transmitted and multiple wrong number design, the BCH code of output binary coding form, after this yard received by the BCH code decoding and error device of custom-designed correspondence, can detect and correct the mistake in the signal communication automatically.

2. by described a kind of BCH symbolic coding, decoding, the multiple error-correcting method of utilizing group translating to constitute of claim 1, it is characterized in that the structure of scrambler comprises input data register, coding memory, multiplier, BCH code check register and time schedule controller.

3. by described a kind of BCH symbolic coding, decoding, the multiple error-correcting method of utilizing group transform method to constitute of claim 1, it is characterized in that decoding, the structure of multiple error-correcting device comprises address counter, decoding memory, multiplier, symptom value register, totalizer, comparer, marker bit, time schedule controller, code translator, input data register and the position error-correcting device that constitutes with door and phase inverter.

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