CN110212910B - Pulse registering circuit and control method thereof - Google Patents
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
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Abstract
The invention relates to a pulse register circuit and a control method thereof, and the pulse register circuit comprises a first switch, a second switch discharge channel, a controllable discharge channel, a first capacitor, a second capacitor, a first voltage detection unit, a second voltage detection unit, a first logic unit, a second logic unit and a monostable trigger; the input signal output circuit also comprises four input signals, namely an input A, an input B, an input C and an input D, and comprises an output signal output A. The invention can be widely used in circuits such as digital-to-analog conversion circuits, digital phase-locked loop circuits and the like, and realizes the operations of sampling, storing, operating, reproducing and the like of pulse signals in the circuits.
Description
Technical Field
The invention relates to the field of pulse register circuit design, in particular to a pulse register circuit and a control method thereof.
Background
The pulse register circuit is a key circuit module for digital-analog mixing, and can be applied to digital-analog mixing circuits such as digital phase-locked loops, digital-analog converters and the like. The digital phase-locked loop and the digital-to-analog converter based on the pulse processing unit can effectively realize the advantages of low voltage, high precision, strong Lu nation property, high portability and the like.
The conventional similar pulse processing circuit has the problems of complex circuit, low precision, easy influence of voltage fluctuation and the like. In summary, an effective pulse register circuit is lacking in the digital-analog hybrid circuit in the prior art.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a pulse register circuit and a control method thereof, which can be widely used in digital-to-analog conversion circuits, digital phase-locked loop circuits, and other circuits to implement operations such as sampling, storing, operating, and reproducing of pulse signals in the circuits.
The invention is realized by adopting the following scheme: a pulse register circuit comprises a first switch, a second switch, a discharge channel, a controllable discharge channel, a first capacitor, a second capacitor, a first voltage detection unit, a second voltage detection unit, a first logic unit, a second logic unit and a monostable trigger; the input signal output circuit also comprises four input signals which are respectively an input A, an input B, an input C and an input D, and comprises an output signal output A;
the first switch is a device with a single-pole double-throw switch, and the state of the active end of the first switch is controlled by an input A; one fixed end is connected with a high level, the other fixed end is grounded through the discharge channel, the active end of the first switch is respectively connected to one end of the first capacitor and the input end of the first voltage detection unit, the other end of the first capacitor is grounded, the output end and the input end B of the first voltage detection unit are respectively connected to two input ends of the first logic unit, the output end output signal C of the first logic unit is connected to the control port x of the controllable discharge channel, the control port y of the controllable discharge channel is connected with the input end D, the discharge port n of the controllable discharge channel is grounded, the discharge port p of the controllable discharge channel is respectively connected to the fixed end of the second switch, the input end of the second voltage detection unit and one end of the second capacitor, and the active end of the second switch is connected to the first input end of the monostable trigger, the second switch is a device with the function of a single-pole single-throw switch, and the state of the active end of the second switch is controlled by an input C; the other end of the second capacitor is grounded, and the other fixed end of the second switch is connected with a high level; the output end of the second voltage detection unit and the control port y of the controllable discharge channel are respectively connected to two input ends of a second logic unit, the output end of the second logic unit is connected to the second input end of the monostable trigger, and the output end of the monostable trigger is connected to the output A.
Further, the discharge channel is a dual-port device including a resistor or a constant current source.
Further, the controllable discharge channel is a four-port device, the controllable discharge channel is realized by adopting a resistor, when the control port x is at an effective level, the resistors at the two ends of the discharge ports p and n are R1 and correspond to the discharge mode A; when the control port y is at an effective level, the resistance at the two ends of the discharge ports p and n is R2 and corresponds to the discharge mode B; when the resistance R1 is larger than R2, the discharge speed of the discharge mode A is slower than that of the discharge mode B, and the pulse can be shortened; when the resistance R1 is smaller than R2, the discharge speed of the discharge mode A is faster than that of the discharge mode B, and the pulse can be subjected to extension treatment; when the resistance R1 is equal to R2, the discharge rate of the discharge mode A is the same as that of the discharge mode B, and the pulse is reduced proportionally.
Further, the controllable discharge channel is a four-port device, a constant current source is adopted to realize the controllable discharge channel, when the control port x is at an effective level, the current flowing through the two ends of the discharge ports p and n is I1, and corresponds to the discharge mode A; when the control port y is at an effective level, the current flowing through the two ends of the discharge ports p and n is I2 and corresponds to the discharge mode B; when the current I1 is less than I2, the discharge speed of the discharge mode A is slower than that of the discharge mode B, and the pulse can be shortened; when the current I1 is greater than I2, the discharge speed of the discharge mode A is higher than that of the discharge mode B, and the pulse can be subjected to extension treatment; when the current I1 is equal to I2, the discharge speed of the discharge mode A is the same as that of the discharge mode B, and the pulse is reduced proportionally.
The invention provides a control method based on the pulse register circuit, which comprises the following steps: when the input A is at an invalid level, the first switch connects the end of the first capacitor which is not connected with the ground to the power supply voltage for charging; when the input A is at an effective level, the first switch connects the first capacitor to the discharge channel, and the discharge channel discharges the first capacitor at the moment; meanwhile, the first voltage detection unit monitors the voltage A on the first capacitor, and when the voltage A is lower than a preset threshold voltage, an output signal B of the first voltage detection unit is set to be an effective level;
the signal B and the input B act on the first logic unit and generate a signal C, and when the input B is at an active level and the signal B is at an inactive level, the signal C is at an active level; otherwise, the signal C is at an invalid level;
input C controls the second switch; when the input C is at an effective level, the second switch is closed, the ungrounded end of the second capacitor is connected to the power supply to charge, and the controllable discharge channel is connected to the second capacitor;
the signal C and the input D act on a controllable discharge channel; according to the difference of the discharge speed, the controllable discharge channel has two discharge modes, namely a discharge mode A and a discharge mode B; when the signal C is at an effective level, the controllable discharge channel discharges the second capacitor in a discharge mode A; when the input D is an effective level, the controllable discharge channel discharges the second capacitor in a discharge mode B;
the second voltage detection unit monitors the voltage D on the second capacitor and generates an output signal E, when the voltage D is lower than a preset voltage, the second voltage detection unit sets the signal E to be an effective level, otherwise, the signal E is set to be an invalid level;
the signal E and the input D act on the second logic unit simultaneously and generate a signal F; when the input D and the signal E are at the effective level at the same time, the signal F is at the effective level; otherwise, the voltage level is invalid; the signal F and the input C act on the monostable trigger at the same time, when the input C is an effective level, the monostable trigger is reset, and the output A is set to be an ineffective level; when signal F is active, the monostable flip-flop is set and output a is set to an active level.
Compared with the prior art, the invention has the following beneficial effects: the method can be widely applied to circuits such as digital-to-analog conversion circuits, digital phase-locked loop circuits and the like, and can realize operations such as sampling, storage, operation, reproduction and the like of pulse signals in the circuits.
Drawings
Fig. 1 is a schematic circuit diagram according to an embodiment of the present invention.
FIG. 2 is a timing diagram of the circuit according to the embodiment of the present invention.
FIG. 3 is a schematic diagram of a discharge channel and a controllable discharge channel according to an embodiment of the invention. Wherein (a) is a discharge channel and (b) is a controllable discharge channel.
Fig. 4 is a schematic diagram of an application example of the embodiment of the invention.
Fig. 5 is a timing diagram of fig. 4.
Detailed Description
The invention is further explained below with reference to the drawings and the embodiments.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
As shown in fig. 1, the present embodiment provides a pulse register circuit, which includes a first switch, a second switch, a discharge channel, a controllable discharge channel, a first capacitor, a second capacitor, a first voltage detection unit, a second voltage detection unit, a first logic unit, a second logic unit, and a monostable flip-flop; the input signal output circuit also comprises four input signals which are respectively an input A, an input B, an input C and an input D, and comprises an output signal output A;
the first switch is a device with a single-pole double-throw switch, and the state of the active end of the first switch is controlled by an input A; one fixed end is connected with a high level, the other fixed end is grounded through the discharge channel, the active end of the first switch is respectively connected to one end of the first capacitor and the input end of the first voltage detection unit, the other end of the first capacitor is grounded, the output end and the input end B of the first voltage detection unit are respectively connected to two input ends of the first logic unit, the output end output signal C of the first logic unit is connected to the control port x of the controllable discharge channel, the control port y of the controllable discharge channel is connected with the input end D, the discharge port n of the controllable discharge channel is grounded, the discharge port p of the controllable discharge channel is respectively connected to the fixed end of the second switch, the input end of the second voltage detection unit and one end of the second capacitor, and the active end of the second switch is connected to the first input end of the monostable trigger, the second switch is a device with the function of a single-pole single-throw switch, and the state of the active end of the second switch is controlled by an input C; the other end of the second capacitor is grounded, and the other fixed end of the second switch is connected with a high level; the output end of the second voltage detection unit and the control port y of the controllable discharge channel are respectively connected to two input ends of a second logic unit, the output end of the second logic unit is connected to the second input end of the monostable trigger, and the output end of the monostable trigger is connected to the output A.
In this embodiment, as shown in (a) of fig. 3, the discharge channel is a two-port device and includes a resistor or a constant current source, and the discharge speed of the discharge channel is different depending on the resistance value or the current value of the constant current source.
In this embodiment, as shown in (b) of fig. 3, the controllable discharge channel is a four-port device, the controllable discharge channel is implemented by using resistors, when the control port x is at an active level, the resistors at two ends of the discharge ports p and n are R1, and correspond to the discharge mode a; when the control port y is at an effective level, the resistance at the two ends of the discharge ports p and n is R2 and corresponds to the discharge mode B; when the resistance R1 is larger than R2, the discharge speed of the discharge mode A is slower than that of the discharge mode B, and the pulse can be shortened; when the resistance R1 is smaller than R2, the discharge speed of the discharge mode A is faster than that of the discharge mode B, and the pulse can be subjected to extension treatment; when the resistance R1 is equal to R2, the discharge rate of the discharge mode A is the same as that of the discharge mode B, and the pulse is reduced proportionally.
Preferably, the controllable discharge channel may also be implemented by using a constant current source, and when the control port x is at an active level, the current flowing through the two ends of the discharge ports p and n is I1, and corresponds to the discharge mode a; when the control port y is at an effective level, the current flowing through the two ends of the discharge ports p and n is I2 and corresponds to the discharge mode B; when the current I1 is less than I2, the discharge speed of the discharge mode A is slower than that of the discharge mode B, and the pulse can be shortened; when the current I1 is greater than I2, the discharge speed of the discharge mode A is higher than that of the discharge mode B, and the pulse can be subjected to extension treatment; when the current I1 is equal to I2, the discharge speed of the discharge mode A is the same as that of the discharge mode B, and the pulse is reduced proportionally.
The present embodiment provides a control method based on the pulse register circuit described above, which specifically includes: when the input A is at an invalid level, the first switch connects the end of the first capacitor which is not connected with the ground to the power supply voltage for charging; when the input A is at an effective level, the first switch connects the first capacitor to the discharge channel, and the discharge channel discharges the first capacitor at the moment; meanwhile, the first voltage detection unit monitors the voltage A on the first capacitor, and when the voltage A is lower than a preset threshold voltage, an output signal B of the first voltage detection unit is set to be an effective level;
the signal B and the input B act on the first logic unit and generate a signal C, and when the input B is at an active level and the signal B is at an inactive level, the signal C is at an active level; otherwise, the signal C is at an invalid level;
input C controls the second switch; when the input C is at an effective level, the second switch is closed, the ungrounded end of the second capacitor is connected to the power supply to charge, and the controllable discharge channel is connected to the second capacitor;
the signal C and the input D act on a controllable discharge channel; according to the difference of the discharge speed, the controllable discharge channel has two discharge modes, namely a discharge mode A and a discharge mode B; when the signal C is at an effective level, the controllable discharge channel discharges the second capacitor in a discharge mode A; when the input D is an effective level, the controllable discharge channel discharges the second capacitor in a discharge mode B;
the second voltage detection unit monitors the voltage D on the second capacitor and generates an output signal E, when the voltage D is lower than a preset voltage, the second voltage detection unit sets the signal E to be an effective level, otherwise, the signal E is set to be an invalid level;
the signal E and the input D act on the second logic unit simultaneously and generate a signal F; when the input D and the signal E are at the effective level at the same time, the signal F is at the effective level; otherwise, the voltage level is invalid; the signal F and the input C act on the monostable trigger at the same time, when the input C is an effective level, the monostable trigger is reset, and the output A is set to be an ineffective level; when signal F is active, the monostable flip-flop is set and output a is set to an active level.
Preferably, fig. 2 shows a timing diagram of the circuit of the present embodiment. In this embodiment, the active level of the other signals is high and the inactive level is low, except that the active level of the input C and the signal F is low and the inactive level is high.
As shown in fig. 2, when the input a is low, the first capacitor is always in a charging state, so the voltage a is kept at the power voltage; when the input a changes to high level at time T1, the discharge channel 1 discharges the capacitor 1; as the charge on the capacitor 1 becomes less, the voltage a will drop all the time; when the voltage a drops below the threshold voltage 1 at time T2, the signal B transitions from low to high; on the other hand, the input B transitions high at time T3, causing the signal C to transition high because time T3 is earlier than time T2, and until time T2, the signal B transitions high, causing the signal C to transition low; at the same time, input C transitions low at time T4 and returns high at time T5, causing the second capacitor to be charged, voltage D to be pulled up to the supply voltage, signal E to low, the monostable flip-flop to be reset and output a to low; the second capacitor remains in this state until time T3, the high level of signal C causes controlled current source 2 to start discharging the second capacitor and voltage D drops; when the voltage D drops below the threshold voltage 2 at time T6, the signal E flips to a high level; when the signal E is inverted to be at a high level, the input D is still at a low level, so that the signal F is kept unchanged; until T7 moment, the input D is turned into high level, the signal F is changed into low level, and then the output A is set into high level; at time T8, input C goes low again, causing the second capacitor to charge again, voltage D to return to the supply voltage, signal E to go low and signal F to go high, the monostable flip-flop is reset again, and output a goes low.
The above-mentioned embodiment is only a specific sequential logic case of the circuit of the present invention to illustrate the operation principle of the circuit described in this embodiment, and it does not mean that the operational sequential logic of the circuit of this embodiment is only the example. In fact, as the timing between input a, input B, input C and input D changes, the timing logic of each signal changes accordingly, resulting in different timing logic conditions. But these sequential logics will follow the working principle of the circuit described in this embodiment.
FIG. 4 shows an example of an application of the circuit according to the present embodiment, which can be implemented by subtracting the pulse 1 defined by the input A and the input B from the pulse 2 defined by the input C and the input D; and is driven by sample a to appear at pulse 3 defined by output a and output B. The specific operation timing logic is shown in fig. 5, and the pulse width of pulse 3 is equal to the width of pulse 1 minus the width of pulse 2.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing is directed to preferred embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. However, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present invention are within the protection scope of the technical solution of the present invention.
Claims (5)
1. A pulse register circuit is characterized by comprising a first switch, a second switch, a discharge channel, a controllable discharge channel, a first capacitor, a second capacitor, a first voltage detection unit, a second voltage detection unit, a first logic unit, a second logic unit and a monostable trigger, wherein the first switch is connected with the first voltage detection unit; the input signal output circuit also comprises four input signals which are respectively an input A, an input B, an input C and an input D, and comprises an output signal output A;
the first switch is a device with a single-pole double-throw switch, and the state of the active end of the first switch is controlled by an input A; one fixed end is connected with a high level, the other fixed end is grounded through the discharge channel, the active end of the first switch is respectively connected to one end of the first capacitor and the input end of the first voltage detection unit, the other end of the first capacitor is grounded, the output end and the input end B of the first voltage detection unit are respectively connected to two input ends of the first logic unit, the output end output signal C of the first logic unit is connected to the control port x of the controllable discharge channel, the control port y of the controllable discharge channel is connected with the input end D, the discharge port n of the controllable discharge channel is grounded, the discharge port p of the controllable discharge channel is respectively connected to the fixed end of the second switch, the input end of the second voltage detection unit and one end of the second capacitor, and the active end of the second switch is connected to the first input end of the monostable trigger, the second switch is a device with the function of a single-pole single-throw switch, and the state of the active end of the second switch is controlled by an input C; the other end of the second capacitor is grounded, and the other fixed end of the second switch is connected with a high level; the output end of the second voltage detection unit and the control port y of the controllable discharge channel are respectively connected to two input ends of a second logic unit, the output end of the second logic unit is connected to the second input end of the monostable trigger, and the output end of the monostable trigger is connected to the output A.
2. The pulse registering circuit of claim 1, wherein said discharge channel is a two-port device comprising a resistor or a constant current source.
3. The pulse register circuit of claim 1, wherein the controllable discharge channel is a four-port device, and the controllable discharge channel is implemented by using resistors, and when the control port x is at an active level, the resistors at the two ends of the discharge ports p and n are R1 and correspond to the discharge mode a; when the control port y is at an effective level, the resistance at the two ends of the discharge ports p and n is R2 and corresponds to the discharge mode B; when the resistance R1 is larger than R2, the discharge speed of the discharge mode A is slower than that of the discharge mode B, and the pulse can be shortened; when the resistance R1 is smaller than R2, the discharge speed of the discharge mode A is faster than that of the discharge mode B, and the pulse can be subjected to extension treatment; when the resistance R1 is equal to R2, the discharge rate of the discharge mode A is the same as that of the discharge mode B, and the pulse is reduced proportionally.
4. The pulse register circuit of claim 1, wherein the controllable discharge channel is a four-port device, a constant current source is used to realize the controllable discharge channel, when the control port x is active, the current flowing through the two ends of the discharge ports p and n is I1, and corresponds to the discharge mode a; when the control port y is at an effective level, the current flowing through the two ends of the discharge ports p and n is I2 and corresponds to the discharge mode B; when the current I1 is less than I2, the discharge speed of the discharge mode A is slower than that of the discharge mode B, and the pulse can be shortened; when the current I1 is greater than I2, the discharge speed of the discharge mode A is higher than that of the discharge mode B, and the pulse can be subjected to extension treatment; when the current I1 is equal to I2, the discharge speed of the discharge mode A is the same as that of the discharge mode B, and the pulse is reduced proportionally.
5. A control method based on the pulse register circuit of any one of claims 1-4, characterized in that: when the input A is at an invalid level, the first switch connects the end of the first capacitor which is not connected with the ground to the power supply voltage for charging; when the input A is at an effective level, the first switch connects the first capacitor to the discharge channel, and the discharge channel discharges the first capacitor at the moment; meanwhile, the first voltage detection unit monitors the voltage A on the first capacitor, and when the voltage A is lower than a preset threshold voltage, an output signal B of the first voltage detection unit is set to be an effective level;
the signal B and the input B act on the first logic unit and generate a signal C, and when the input B is at an active level and the signal B is at an inactive level, the signal C is at an active level; otherwise, the signal C is at an invalid level;
input C controls the second switch; when the input C is at an effective level, the second switch is closed, the ungrounded end of the second capacitor is connected to the power supply to charge, and the controllable discharge channel is connected to the second capacitor;
the signal C and the input D act on a controllable discharge channel; according to the difference of the discharge speed, the controllable discharge channel has two discharge modes, namely a discharge mode A and a discharge mode B; when the signal C is at an effective level, the controllable discharge channel discharges the second capacitor in a discharge mode A; when the input D is an effective level, the controllable discharge channel discharges the second capacitor in a discharge mode B;
the second voltage detection unit monitors the voltage D on the second capacitor and generates an output signal E, when the voltage D is lower than a preset voltage, the second voltage detection unit sets the signal E to be an effective level, otherwise, the signal E is set to be an invalid level;
the signal E and the input D act on the second logic unit simultaneously and generate a signal F; when the input D and the signal E are at the effective level at the same time, the signal F is at the effective level; otherwise, the voltage level is invalid; the signal F and the input C act on the monostable trigger at the same time, when the input C is an effective level, the monostable trigger is reset, and the output A is set to be an ineffective level; when signal F is active, the monostable flip-flop is set and output a is set to an active level.
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