CN110190844A - Time correction circuit and its time-correcting method - Google Patents
Time correction circuit and its time-correcting method Download PDFInfo
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- CN110190844A CN110190844A CN201910585489.6A CN201910585489A CN110190844A CN 110190844 A CN110190844 A CN 110190844A CN 201910585489 A CN201910585489 A CN 201910585489A CN 110190844 A CN110190844 A CN 110190844A
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- 238000003379 elimination reaction Methods 0.000 claims abstract description 164
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- 230000033228 biological regulation Effects 0.000 claims description 3
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- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/012—Modifications of generator to improve response time or to decrease power consumption
Abstract
The present invention provides a kind of time correction circuit and its time-correcting method.Time correction circuit includes frequency eliminator, time counter and computing circuit.Frequency eliminator receives clock signal and frequency elimination value, according to frequency elimination value to generate frequency elimination clock signal.Time counter foundation frequency elimination clock signal uses the generation output time to carry out counting action.Computing circuit is according to output time and the time difference of system time, to adjust frequency elimination value.
Description
Technical field
The present invention relates to a kind of time correction circuit and its time-correcting methods, more particularly to a kind of gradual time
Correcting circuit and its time-correcting method.
Background technique
Clocking capability can be performed in the inside setting circuit of general integrated circuit, for showing the time in a power-save mode.So
And the clock signal frequency as provided by integrated circuit internal oscillator can be influenced to generate offset by environmental parameter, it is related to make
It obtains toggle rate and then to deviate, causes the display time incorrect.
Based on above-mentioned problem, integrated circuit must regularly update the time from system end, to ensure to show the correct of time
Property.And since the prior art is to directly display renewal time provided by system end when receiving system end update.It makes
At user in observing time, have an opportunity to observe that the display time generates unnatural bounce.
Summary of the invention
The present invention provides a kind of time correction circuit and time-correcting method, and execution time adjustment that can be gradual is dynamic
Make.
Time correction circuit of the invention includes frequency eliminator, time counter and computing circuit.Frequency eliminator receives clock pulse
Signal and frequency elimination value, according to frequency elimination value to generate frequency elimination clock signal.Time counter couples frequency eliminator, according to frequency elimination clock pulse
Signal uses the generation output time to carry out counting action.Computing circuit couples frequency eliminator and time counter, according to defeated
The time difference of time and system time out, to adjust frequency elimination value.
Time-correcting method of the invention includes: to receive clock signal and frequency elimination value, according to frequency elimination value to generate frequency elimination
Clock signal；According to frequency elimination clock signal to carry out counting action, and use the generation output time；And according to the output time
And the time difference of system time, to adjust frequency elimination value.
Based on above-mentioned, the present invention carrys out output caused by adjustment time correcting circuit by adjusting the frequency elimination value of frequency eliminator
Time.Whereby, time correction circuit, to adjust the output time, can reduce generation wink display time by gradual mode
Between the phenomenon that beating.
To make the foregoing features and advantages of the present invention clearer and more comprehensible, special embodiment below, and it is detailed to cooperate attached drawing to make
Carefully it is described as follows.
Detailed description of the invention
Fig. 1 shows the schematic diagram of the time correction circuit of one embodiment of the invention.
Fig. 2 shows the action flow charts of the time adjustment of the embodiment of the present invention.
Fig. 3 shows the schematic diagram of the time correction circuit of another embodiment of the present invention.
Fig. 4 A and Fig. 4 B are shown respectively in the embodiment of the present invention, execute current frequency elimination value, the stable state of time adjustment movement
The variable condition schematic diagram of frequency elimination value and time difference.
Fig. 5 shows the flow chart of the time-correcting method of the embodiment of the present invention.
Description of symbols
100,300: time correction circuit
110,310: frequency eliminator
120,320: computing circuit
130,330: time counter
311,312: frequency eliminating circuit
340: host
FO: clock signal
S: frequency elimination value
FCNT: frequency elimination clock signal
TOUT: output time
T*: system time
S210~S2110, S510~S530: the step of time adjustment
DT (pre): previous time difference
INI: init flag
STDY: stable state flag
DT: time difference
S*: frequency elimination value is updated
A, B: regulation coefficient
SN: frequency elimination value is updated
CK1: clock signal
BS: default frequency elimination value
Specific embodiment
Fig. 1 is please referred to, Fig. 1 shows the schematic diagram of the time correction circuit of one embodiment of the invention.Time correction circuit 100
Including frequency eliminator 110, computing circuit 120 and time counter 130.Frequency eliminator 110 receives clock signal FO and frequency elimination value
S, according to frequency elimination value S to generate frequency elimination clock signal FCNT.Time counter 130 couples frequency eliminator 110.Time counter 130
Frequency elimination clock signal FCNT is received, and according to frequency elimination clock signal FCNT to carry out counting action, and uses the generation output time
TOUT.In addition, computing circuit 120 couples frequency eliminator 110 and time counter 130.120 receiving time counter of computing circuit
Time TOUT is exported caused by 130, and receives the system time t* transmitted by external host (i.e. system end), according to output
The time difference of time TOUT and system time t*, to adjust generated frequency elimination value S.
It should also be noted that in the embodiment of the present invention, external host can periodic generation system time t*, and when by system
Between t* be sent to computing circuit 120.Computing circuit 120 can generate in advance frequency elimination value S according to preset value, and when receiving system
Between t* when, according to output time TOUT and system time t* time difference dT, generated frequency elimination value S is adjusted.
That is, the time correction circuit 100 of the embodiment of the present invention will not directly adjust output time TOUT according to system time t*.
By adjusting frequency elimination value S, can make caused by output time TOUT progressive variation occurs, avoid time correction circuit 100 according to
Unnatural bounce is generated according to the time that output time TOUT is shown.
About implementation detail, please synchronize referring to Fig.1 and Fig. 2, wherein Fig. 2 shows the time adjustments of the embodiment of the present invention
Action flow chart.In Fig. 2, in step S210, computing circuit 120 can be initialized, set stable state frequency elimination value S* and
Frequency elimination value S at present, and previous time difference dT (pre) is set equal to 0.In addition, computing circuit 120 is also set in step S210
Init flag INI and stable state flag STDY.In the present embodiment, it in step S210, stable state frequency elimination value S* and removes at present
Frequency value S can be preset as being equal to 60, and init flag INI and stable state flag STDY then can be set as identical logical value 1.
Step S220 starts when updating system time t*, and wherein system time t* can be sent by external electronic device,
And it is received by computing circuit 120.The system time t* of step S220 can be to periodically update movement.Computing circuit 120 simultaneously can be according to
Time difference dT is calculated according to system time t* and output time TOUT.
In step S230, the time difference dT of the judgement output of computing circuit 120 time TOUT and system time t* is
It is no to be equal to previous time difference dT (pre), if time difference dT is equal to previous time difference dT (pre), indicates current and remove
Frequency value S and system end are fully synchronized.In the case, computing circuit 120 can first carry out step S240 and execute step S250 again.?
On the other hand, if time difference dT is not equal to previous time difference dT (pre), indicate that current frequency elimination value S has with system end
Error.In the case, computing circuit 120 can directly execute step S250.
In the present embodiment, stable state frequency elimination value S* is updated to frequency elimination value S by step S240, and makes to remove init flag INI,
Make init flag INI logical value 0.The meaning of this step is that computing circuit 120 has learnt to right-on frequency elimination value
S, and stable state frequency elimination value S* is set it to, and indicate this state by removing init flag INI.
Computing circuit 120 makes previous time difference dT (pre) be equal to time difference dT in step S250.In step S260
In, computing circuit 120 judges whether time difference dT is not equal to 0, if the judging result of step S260 is yes, the expression output time
Still there is error between TOUT and system time t*, computing circuit 120 can remove stable state flag STDY by step S270, make stable state
Flag STDY is equal to logical value 0 to indicate current output time TOUT and have error needs to be adjusted.Later, computing circuit 120
Execute step S280.It is opposite, if the judging result of step S260 be it is no, computing circuit 120 directly executes step S280.
In step S280, computing circuit 120 judges whether stable state flag STDY is logical value 0, and is working as stable state flag
When STDY is logical value 0, by step S290, generated according to stable state frequency elimination value S*, current frequency elimination value S and time difference dT
Frequency elimination value SN is updated, and is set frequency elimination value SN is updated to current frequency elimination value S；Wherein, frequency elimination value SN=(1-A) × S+A is updated
× S*+B × dT, A, B are respectively the first adjustment coefficient and second adjustment coefficient, and the first adjustment coefficient A is less than or equal to 1.This
Outside, second adjustment coefficient B can be set according to the first adjustment coefficient A, for example, second adjustment coefficient B can be with the first adjustment
Coefficient A is inversely proportional, or has other proportionate relationships.
It is worth noting that, the size of the first adjustment coefficient A, second adjustment coefficient B can also patrolling according to init flag INI
Value is collected to set.That is, whether can learn according to computing circuit 120 to right-on frequency elimination value S, and set
It is set to stable state frequency elimination value S* setting the first adjustment coefficient A and second adjustment coefficient B.For example bright, when init flag INI is to patrol
When collecting value 1, the first adjustment coefficient A can be set as 1/2, and second adjustment coefficient B then can be set as 2.When init flag INI is
When logical value 0, the first adjustment coefficient A can be set as 1, and second adjustment coefficient B then can be set as 1.It must be noted that
After stable state flag STDY is removed (=0), when time difference dT is for the first time zero, step S280 still can be because of stable state flag STDY
It is not yet set to 1 (this setting must be to subsequent step S2110) and enters step S290 adjustment and update frequency elimination value SN.If but at this time
Stable state frequency elimination value S* (init flag INI is logical value 0) fully synchronized with system end, and time difference dT is zero, meaning
Adjustment completed.That is, the setting of the first adjustment coefficient A and second adjustment coefficient B must make under this state
It is essentially equal in stable state frequency elimination value S* to update frequency elimination value SN.Accordingly, when stable state frequency elimination value S* is fully synchronized with system end (just
Beginning flag INI is logical value 0), then it no longer needs to update frequency elimination value SN (the first adjustment according to current frequency elimination value S adjustment instantly
1) coefficient A should be, it is only necessary to update frequency elimination value SN with right-on stable state frequency elimination value S* and time difference dT fine tuning.
It should also be noted that in the present embodiment, init flag INI is cleared to logical value 0, be by step S240 come into
Capable.In step S240, computing circuit 120 has learnt to right-on frequency elimination value, and sets it to stable state frequency elimination
Value S*.Therefore, when init flag INI is logical value 0, frequency elimination value SN and stable state frequency elimination value are updated caused by step S290
S* and time difference dT are related, that is, will not be adjusted according to current frequency elimination value S.Opposite, when init flag INI is
When logical value 1, indicate that step S240 is not performed, stable state frequency elimination value S* is not right-on frequency elimination value.Therefore, pass through step
S290, computing circuit 120 can be simultaneously according to not right-on stable state frequency elimination value S*, current frequency elimination value S and time differences
DT updates frequency elimination value SN, and is updated by updating frequency elimination value SN to be directed to current frequency elimination value S.
In addition, step S2100 is judged again for whether time difference dT is equal to 0, if time difference dT is not equal to
0, it is re-execute the steps S220, wakes up process when system update system time t*.Relatively, if time difference dT is equal to
0, after thening follow the steps S2110 to set stable state flag STDY as logical value 1, then it re-execute the steps S220.
Actual computation paradigm is enumerated, herein the implementation detail of the embodiment of the present invention is explained in more detail.Believed with clock pulse
For the frequency of number FO is 37.8 megahertz by 36 megahertz drifts.In period first time, computing circuit 120 is in step
Rapid S210 setting stable state frequency elimination value S* and current frequency elimination value S is all equal to 60, sets previous time difference dT (pre) equal to 0, and
Init flag INI and stable state flag STDY are set as logical value 1.Step S220 receives the system time t* updated, operation electricity
Road 120 simultaneously calculates time difference dT equal to 3.It is not identical based on time difference dT and previous time difference dT (pre), operation electricity
Road 120 does not execute step S240, and directly executes step S230 and set previous time difference dT (pre) equal to time difference dT=
3.Then, in step S260, computing circuit 120 judges that time difference dT is steady to remove not equal to 0, and by step S270
State flag STDY is logical value 0.Then, computing circuit 120 judge in step S280 stable state flag STDY for logical value 0, and
It executes step S290 and updates (1/2) × (60)+(1/2) × (60)+(2) frequency elimination value SN=× (3)=66 to calculate, and will more
New frequency elimination value SN is set to current frequency elimination value S, here, be equal to logic 1 based on init flag INI, the first adjustment coefficient A and the
Two regulation coefficient B can be respectively 1/2,2.Then, step S2100 judges that time difference dT is not equal to 0, and executes step
S220。
It holds and continues above-mentioned explanation, in second time period, based on the movement in period first time, time difference at this time
DT can be equal to 0, and computing circuit 120 can determine whether out previous time difference dT (pre) (=3) not equal to the time in step S230
Difference dT (=0), therefore do not execute step S240 (i.e. current frequency elimination value S and system end be not fully synchronized).Computing circuit 120
It is equal to time difference dT=0 by the new previous time difference dT (pre) of step S250 setting, and passes through step S260, S280,
By judging that stable state flag STDY, Lai Zhihang the step S290 for being maintained equal to logical value 0 updates frequency elimination value SN=(1/ to calculate
2) × (60)+(1/2) × (66)+(2) × (0)=63.Then, it is based on time difference dT=0, computing circuit 120 executes step
S2110 is replied to set stable state flag STDY as logical value 1 and is executed step S220 to wait update system time t* next time
Movement generation.
In the third time cycle of second time period, based on current frequency elimination value S=63 at this time, clock signal FO is
37.8 megahertz.Therefore, by making 37.8 megahertz divided by 63 again divided by 6 × 105(default frequency elimination value), when can make frequency elimination
Arteries and veins signal FCNT is just equal to 1 hertz.That is, frequency elimination value S is fully synchronized with system end at present.In week this third time
It is interim, based on time difference dT (being all equal to 0) equal with previous time difference dT (pre), pass through step S230, computing circuit
120 can remove init flag INI as logical value 0, and stable state frequency elimination value S* is made to be equal to right-on current frequency elimination value S=
63.Also, by step S260, S280, S2110, stable state flag STDY and current frequency elimination value S are not changed, achievable
Export the adjustment movement of time TOUT.
In the present embodiment, every a period of time can be 1 minute, alternatively, designer can be arranged according to actual demand
The length of time in each period, the limitation that do not fix.
By above description it is known that in embodiments of the present invention, when the frequency of clock signal FO morphs, this hair
The time correction circuit 100 of bright embodiment can complete the adjustment movement of output time TOUT by three time cycles.Pass through
Gradual adjustment movement, effectively promotes the smoothness of output time showing, promotes visual comfort level.
It is noted that after the completion of the adjustment of above-mentioned current frequency elimination value S, after regular hour length, if send out again
It the phenomenon that frequency drift of raw clock signal FO, then can be by the motion flow of 2 embodiment of earlier figures, further directed to removing at present
Frequency value S is adjusted, and effectively correction output time TOUT.Relevant movement details is similar in explanation above-mentioned, pardons herein
Seldom repeat.
Referring to figure 3., Fig. 3 shows the schematic diagram of the time correction circuit of another embodiment of the present invention.Time correction circuit
300 include frequency eliminator 310, computing circuit 320 and time counter 330.With previous embodiment the difference is that, frequency eliminator
310 include the frequency eliminating circuit 311 and 312 of coupled in series.Frequency eliminating circuit 311 receive clock signal FO, and according to frequency elimination value S with
Frequency elimination is carried out for clock signal FO to generate clock signal CK1.Frequency eliminating circuit 312 then receives clock signal CK1, and according to pre-
If frequency elimination value BS is to carry out frequency elimination for clock signal CK1 to generate frequency elimination clock signal FCNT.In the present embodiment, frequency elimination electricity
The coupling sequence on road 311,312 can exchange, and default frequency elimination value BS can be changeless numerical value.
In addition, in the present embodiment, computing circuit 320 is coupled to host 340, and can receive periodical hair by host 340
The system time t* sent.
Subsidiary one mentions, and in embodiments of the present invention, the hardware structure of frequency eliminating circuit 311,312 can pass through art technology
Frequency eliminating circuit known to personnel is implemented, and does not limit specifically.In addition, the hardware structure of time counting circuit 330 can lead to
Counting circuit well-known to those skilled in the art is crossed to implement, also without specific limitation.Computing circuit 320 then can be
Has the processor of operational capability.Alternatively, computing circuit 320 can be through hardware description language (Hardware
Description Language, HDL) or any other digital circuit well-known to those skilled in the art design method
It is designed, and can programmed logic gate array (Field Programmable Gate Array, FPGA), multiple by scene
It is miscellaneous can program logic device (Complex Programmable Logic Device, CPLD) or special application integrated circuit
The mode of (Application-specific Integrated Circuit, ASIC) is come the hardware circuit realized, for example, fortune
Calculating circuit 320 can be a state machine (state machine) circuit.
A and Fig. 4 B, Fig. 4 A and Fig. 4 B are shown respectively in the embodiment of the present invention referring to figure 4. below, execute time school
The variable condition schematic diagram of the current frequency elimination value of direct action, stable state frequency elimination value and time difference.In Figure 4 A, believe when clock pulse
Number frequency when changing, frequency elimination value S, stable state frequency elimination value S* can be adjusted according to step shown by Fig. 2 embodiment at present
It is whole, and gradual stabilization after multiple steps.If also, over time, the frequency of clock signal again this change
When, frequency elimination value S, stable state frequency elimination value S* can also be gradual at present stabilization.It is found that passing through frequency elimination value S, stable state frequency elimination value in Fig. 4 B
The gradual stable adjustment movement of S*, the convergence that time difference dT can also be gradual, and at steady state level off to 0.
Referring to figure 5., Fig. 5 shows the flow chart of the time-correcting method of the embodiment of the present invention.Wherein, step S510 is received
Clock signal and frequency elimination value, according to frequency elimination value to generate frequency elimination clock signal；Step S520 according to frequency elimination clock signal with into
Row counting action, and use the generation output time；Step S530 then according to output time and the time difference of system time, comes
Adjust frequency elimination value.
Have explanation in detail about the implementation detail of above-mentioned steps, in the embodiment stated before this invention, with it is following not
It repeats more.
In conclusion frequency elimination value of the present invention by adjusting frequency eliminator, carrys out gradual adjustment time correcting circuit and is produced
The raw output time.In this way, which the display time will not be promoted because there is a phenomenon where unexpected bounces for corrective action by exporting the time
Display smooth degree.
Although the present invention is disclosed as above with embodiment, however, it is not to limit the invention, any technical field
In technical staff, without departing from the spirit and scope of the present invention, when can make a little change and retouching, therefore guarantor of the invention
Subject to shield range ought be defined depending on claim.
Claims (20)
1. a kind of time correction circuit, comprising:
Frequency eliminator receives clock signal and frequency elimination value, according to the frequency elimination value to generate frequency elimination clock signal；
Time counter couples the frequency eliminator, and according to the frequency elimination clock signal to carry out counting action, and it is defeated to use generation
Time out；And
Computing circuit couples the frequency eliminator and the time counter, according to the output time and system time
Time difference, to adjust the frequency elimination value.
2. time correction circuit according to claim 1, wherein the computing circuit sets stable state frequency elimination value, and according to institute
Stable state frequency elimination value, current frequency elimination value and the time difference are stated to generate and update frequency elimination value, the computing circuit and according to institute
It states and updates frequency elimination value to adjust the frequency elimination value.
3. time correction circuit according to claim 2, wherein the computing circuit also set the first adjustment coefficient A and
Second adjustment coefficient B is generated with being selectively depending on the stable state frequency elimination value S*, current frequency elimination value S and time difference dT
Frequency elimination value SN is updated, wherein SN=(1-A) × S+A × S*+B × dT, wherein the first adjustment coefficient A is less than or equal to 1.
4. time correction circuit according to claim 2, wherein the computing circuit is periodically received by external host
The system time.
5. time correction circuit according to claim 4, wherein the computing circuit is in period first time according to described in
Frequency elimination value is updated to update the frequency elimination value, and when second time period after period first time updates the output
Between.
6. time correction circuit according to claim 2, wherein the computing circuit also to:
Init flag, stable state flag and previous time difference are set；
Comparison result is generated according to the previous time difference and the time difference；
Adjust the stable state frequency elimination value and the init flag according to the comparison result, and according to the comparison result,
And changing the previous time difference is the time difference；
Judge whether the time difference is equal to 0 to adjust the stable state flag；And
According to the stable state flag to decide whether according to the update frequency elimination value to adjust the frequency elimination value.
7. time correction circuit according to claim 6, wherein the computing circuit in the previous time difference and
When the time difference is equal, the init flag is removed, and the stable state frequency elimination value is made to be equal to the current frequency elimination value.
8. time correction circuit according to claim 7, wherein when the init flag is by removing state, if must adjust
The whole frequency elimination value, then without reference to the current frequency elimination value when adjusting.
9. time correction circuit according to claim 6, wherein the computing circuit is not equal to 0 in the time difference
When, the stable state flag is removed, and when the time difference is equal to 0, set the stable state flag.
10. time correction circuit according to claim 9, wherein the computing circuit is to be removed in the stable state flag
When state, the frequency elimination value is adjusted according to the update frequency elimination value.
11. time correction circuit according to claim 9, wherein the computing circuit is to be set in the stable state flag
When state, the system time in next period to be received is waited.
12. time correction circuit according to claim 1, wherein the frequency eliminator includes:
First frequency eliminating circuit, according to the frequency elimination value to carry out frequency elimination for the clock signal to generate the first clock signal；
And
Second frequency eliminating circuit couples first frequency eliminating circuit, be directed to according to frequency elimination value is preset first clock signal into
Row frequency elimination is to generate the frequency elimination clock signal.
13. a kind of time-correcting method, comprising:
Clock signal and frequency elimination value are received, according to the frequency elimination value to generate frequency elimination clock signal；
According to the frequency elimination clock signal to carry out counting action, and use the generation output time；And
According to the output time and the time difference of system time, to adjust the frequency elimination value.
14. time-correcting method according to claim 13, wherein according to the output time and the system time
The time difference, include: the step of the frequency elimination value to adjust
Stable state frequency elimination value is set, and is selectively depending on the stable state frequency elimination value, current frequency elimination value and the time difference and comes
It generates and updates frequency elimination value, and adjust the frequency elimination value according to the update frequency elimination value.
15. time-correcting method according to claim 14, further includes:
The first adjustment coefficient A and second adjustment coefficient B are set, and is selectively depending on the stable state frequency elimination value S*, removes at present
Frequency value S and time difference dT generates update frequency elimination value SN, wherein SN=(1-A) × S+A × S*+B × dT, wherein described the
One regulation coefficient A is less than or equal to 1, when the stable state frequency elimination value S* is considered the source synchronous with the system time, enables
The first adjustment coefficient A is equal to 1.
16. time-correcting method according to claim 14 wherein setting the stable state frequency elimination value, and is selectively depending on
The stable state frequency elimination value, the current frequency elimination value and the time difference generate the update frequency elimination value, and according to described
Update frequency elimination value to adjust includes: the step of the frequency elimination value
Init flag, stable state flag and previous time difference are set；
Comparison result is generated according to the previous time difference and the time difference；
Adjust the stable state frequency elimination value and the init flag according to the comparison result, and according to the comparison result,
And changing the previous time difference is the time difference；
Judge whether the time difference is equal to 0 to adjust the stable state flag；And
According to the stable state flag to decide whether according to the update frequency elimination value to adjust the frequency elimination value.
17. time-correcting method according to claim 16 removes wherein adjusting the stable state according to the comparison result
Frequency value and the step of init flag include:
In the previous time difference and the equal time difference, the init flag is removed, and removes the stable state
Frequency value is equal to the current frequency elimination value.
18. time-correcting method according to claim 16, wherein judging whether the time difference is equal to 0 to adjust
The step of stating stable state flag include:
When the time difference is not equal to 0, the stable state flag is removed, and when the time difference is equal to 0, described in setting
Stable state flag.
19. time-correcting method according to claim 16, wherein according to the stable state flag to decide whether according to institute
Update frequency elimination value is stated to adjust includes: the step of the frequency elimination value
When the stable state flag is by removing state, the frequency elimination value is adjusted according to the update frequency elimination value.
20. time-correcting method according to claim 16, further includes:
When the stable state flag is to be set state, the system time in next period to be received is waited.
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