CN110190119A - Semiconductor device and electronic equipment - Google Patents
Semiconductor device and electronic equipment Download PDFInfo
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- CN110190119A CN110190119A CN201810153683.2A CN201810153683A CN110190119A CN 110190119 A CN110190119 A CN 110190119A CN 201810153683 A CN201810153683 A CN 201810153683A CN 110190119 A CN110190119 A CN 110190119A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 103
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004020 conductor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 230000005611 electricity Effects 0.000 description 4
- 239000000203 mixture Substances 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
- 230000001755 vocal effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
It includes: semiconductor substrate that the embodiment of the present application, which provides a kind of semiconductor device and electronic equipment, the semiconductor device,；First doped region extends along the length direction all vertical with the width direction of groove and depth direction being formed in the semiconductor substrate；And second doped region, it is formed in first doped region, second doped region is vertical with the length direction, is disposed separately.According to the application, in semiconductor devices, emitter region is disposed separately, to reduce the carrier for the base region for being injected into semiconductor device from emitter region, therefore, the locked situation of semiconductor device can be slowed down, also, improve the load short circuits margin characteristic of semiconductor device.
Description
Technical field
This application involves technical field of semiconductors more particularly to a kind of semiconductor devices and electronic equipment.
Background technique
Currently, the construction of semiconductor device in the prior art can be realized simultaneously the reduction of conducting voltage and can turn off electricity
The increase of stream.Fig. 1 is the section signal of semiconductor device disclosed in patent document 1 (Japanese Unexamined Patent Publication 8-316479)
Figure.
As shown in Figure 1, semiconductor device 100 can have groove 1, first electrode 49 is arranged in groove 1, the first electricity
There is the first insulating layer 48, the surface of the first insulating layer 48 and first electrode 49 is covered between pole 49 and the bottom and side wall of groove 1
Second electrode 51 is arranged on the surface of second insulating layer 50 in lid second insulating layer 50, the second electrode 51 and adjacent groove 1 it
Between semiconductor layer 44 exposure face contact.In Fig. 1, third electrode 52 is additionally provided at the back side of semiconductor layer 41.
Semiconductor device shown in FIG. 1 can be used as trench-type insulated gate bipolar transistor (Insulated Gate
Bipolar Transistor, IGBT), wherein first electrode 49 can be used as grid (gate) electrode, and second electrode 51 can be made
It is connect for emitter electrode with emitter (emitter) 40, third electrode 52 can be used as collector (collector) electrode.
It should be noted that the above description of the technical background be intended merely to it is convenient to the technical solution of the application carry out it is clear,
Complete explanation, and facilitate the understanding of those skilled in the art and illustrate.Cannot merely because these schemes the application's
Background technology part is expounded and thinks that above-mentioned technical proposal is known to those skilled in the art.
Summary of the invention
The inventors of the present application found that trench-type insulated gate bipolar transistor the width of groove can be arranged
Wider, the wide trench IGBT of formation is obtained, to make that there is lower saturation voltage Vcesat between emitter and collector.But
Inventor, due to there is remaining carrier in the semiconductor substrate, is easy to happen half it has furthermore been found that in wide trench IGBT
The locked situation of conductor device；In addition, Vcesat and load short circuits tolerance are the relationships taken into account, lower Vcesat be will lead to
The load short circuits margin characteristic of wide trench IGBT is deteriorated.
The application provides a kind of semiconductor device and electronic equipment, in semiconductor devices, interruption setting emitter region, from
And therefore the carrier for reducing the base region that semiconductor device is injected into from emitter region can slow down semiconductor device and be locked
Fixed situation, also, the carrier quantity due to being injected into base region is reduced, the load short circuits electricity that semiconductor device is able to bear
Stream increases, so that load short circuits margin characteristic is elevated.
According to the embodiment of the present application in a first aspect, providing a kind of semiconductor device, comprising: semiconductor substrate；First mixes
Miscellaneous area prolongs along the length direction all vertical with the width direction of groove and depth direction being formed in the semiconductor substrate
It stretches；And second doped region, it being formed in first doped region, second doped region is vertical with the length direction,
It is disposed separately.
According to the second aspect of the embodiment of the present application, wherein in the length direction, the width of second doped region
The ratio of spacing distance between adjacent second doped region is 1:2~1:9.
According to the third aspect of the embodiment of the present application, wherein the semiconductor device also includes
Third doped region is formed in first doped region, also, the third doped region is along the length direction
Extend and second doped region intersects.
According to the fourth aspect of the embodiment of the present application, wherein the doping type of first doped region and the second doped region
Difference, first doped region are identical with the doping type of third doped region.
According to the 5th of the embodiment of the present application the aspect, wherein the doping concentration of the third doped region is higher than described first
The doping concentration of doped region.
According to the 6th of the embodiment of the present application the aspect, wherein the semiconductor device also includes
Electrode is located at the side wall of the groove.
According to the 7th of the embodiment of the present application the aspect, wherein between the opening width of the groove and the adjacent groove
Distance ratio be 10:1~2:1.
According to the eighth aspect of the embodiment of the present application, wherein the ratio of the depth and width of first doped region is 4:1
~4:5.
According to the 9th of the embodiment of the present application the aspect, wherein the depth of the depth of the groove and first doped region
Ratio be 7:1~2:1.
According to the tenth of the embodiment of the present application the aspect, a kind of electronic equipment is provided, is had in terms of such as above-mentioned first-the nine
Semiconductor device described in middle either side.
The beneficial effects of the present application are as follows: in semiconductor devices, interruption setting emitter region, to reduce from emitter
Area is injected into the carrier of the base region of semiconductor device, therefore, can slow down the locked situation of semiconductor device, also,
Improve the load short circuits margin characteristic of semiconductor device.
Referring to following description and accompanying drawings, specific implementations of the present application are disclosed in detail, specify the original of the application
Reason can be in a manner of adopted.It should be understood that presently filed embodiment is not so limited in range.In appended power
In the range of the spirit and terms that benefit requires, presently filed embodiment includes many changes, modifications and is equal.
Detailed description of the invention
Included attached drawing is used to provide that a further understanding of the embodiments of the present application, and which constitute one of specification
Point, for illustrating presently filed embodiment, and with verbal description come together to illustrate the principle of the application.Under it should be evident that
Attached drawing in the description of face is only some embodiments of the present application, for those of ordinary skill in the art, is not paying wound
Under the premise of the property made is laborious, it is also possible to obtain other drawings based on these drawings.In the accompanying drawings:
Fig. 1 is a schematic cross-section of semiconductor device disclosed in patent document；
It includes the stereoscopic schematic diagram in section that Fig. 2, which is one of the semiconductor device of the embodiment of the present application 1,；
Fig. 3 is a schematic cross-section of the position A-A of Fig. 2；
Fig. 4 is a schematic diagram of influence of the interval rate of the embodiment of the present application 1 to short-circuit tolerance.
Specific embodiment
Referring to attached drawing, by following specification, the aforementioned and other feature of the application be will be apparent.In specification
In attached drawing, specific implementations of the present application are specifically disclosed, which show wherein can be using the portion of the principle of the application
Divide embodiment, it will thus be appreciated that the application is not limited to described embodiment, on the contrary, the application includes falling into appended power
Whole modifications, modification and equivalent in the range of benefit requirement.
In addition, in the following the description of the application, it is for convenience of description, the formation of semiconductor substrate is fluted
Surface is known as " upper surface ", the surface opposite with " upper surface " of the semiconductor substrate is known as " back side ", from " upper surface "
The direction for being directed toward " back side " is known as "lower" direction, and the direction contrary with "lower" is known as "upper" direction.Along semiconductor substrate
The size of upper surface be referred to as width or length, the size along the "upper" direction is known as thickness.
Embodiment 1
The embodiment of the present application provides a kind of semiconductor device.
It includes the stereoscopic schematic diagram in section that Fig. 2, which is one of the semiconductor device of the present embodiment,.As shown in Fig. 2, semiconductor
Device 2 can have semiconductor substrate 20, groove 21, the first doped region 23 and the second doped region 24.
In the present embodiment, as shown in Fig. 2, groove 21 can be formed in the semiconductor substrate 20, also, groove 21 can be with
Extend along the length direction L all vertical with the width direction W of the groove 21 and depth direction D.In the present embodiment, adjacent
Semiconductor substrate between groove 21 can be formed as semiconductor column 22.
In the present embodiment, the first doped region 23 can be formed in semiconductor column 22, also, the first doped region 23 can be with
L extends along its length.
In the present embodiment, the second doped region 24 can be formed in the first doped region 23, also, the second doped region 24 with
Length direction is vertical, is disposed separately, that is, the second doped region 24 can be discontinuously arranged in the length directionl.
According to the present embodiment, the second doped region 24 is arranged by interruption, can reduce being injected into first from the second doped region and mix
Therefore the carrier in miscellaneous area 23 can slow down the locked situation of semiconductor device, also, due to being injected into the first doped region
23 carrier quantity is reduced, and the load short circuit current that semiconductor device is able to bear increases, thus load short circuits margin characteristic
It is enhanced.
In the present embodiment, as shown in Fig. 2, the second doped region 24 can be considered as W extension in the width direction.In length side
To on L, the ratio L1:L2 of the spacing distance L2 between the width L1 of the second doped region 24 and the second adjacent doped region 24 is 1:
2~1:9, thereby, it is possible to realize to be positioned apart from the second doped region 24 in the length directionl.
In the present embodiment, ratio L1:L2 is smaller, then interval rate is higher, the load short circuits margin characteristic of semiconductor device 2
It is better, wherein interval rate is defined as L2/ (L1+L2), for example, L1 is 0.5 micron (μm), L2 is 1.5 microns (μm), interval
Rate is 75%.
Fig. 4 is a schematic diagram of influence of the interval rate of the present embodiment to short-circuit tolerance.In Fig. 4, horizontal axis be this half
The threshold voltage of the grid Vth of conductor device 2, unit are V；The longitudinal axis is short-circuit tolerance, and unit is microsecond (μ s), for indicating short circuit
Electric current makes semiconductor device 2 fail the time used, and the time is longer, shows that short-circuit margin characteristic is better.As shown in figure 4, bent
Line 401,402,403 respectively indicates in the case of interval rate is 75%, 77.3%, 80% short-circuit tolerance with the change of threshold voltage of the grid
Change relationship, wherein in the identical situation of threshold voltage, interval rate is higher, and the short-circuit margin characteristic of semiconductor device 2 is better.
In the present embodiment, as shown in Fig. 2, semiconductor device 2 can also have third doped region 25.Third doped region 25
It can be formed in the first doped region 23, also, L extends along its length.As a result, along the table perpendicular to semiconductor substrate 20
When the direction observation in face, third doped region 25 can be considered as and the second doped region 24 intersects in the first doped region 13.
In the present embodiment, the doping type of the first doped region 23 and the second doped region 24 can be different, the first doped region
23 and the doping type of third doped region 25 can be identical, also, the doping concentration of third doped region 25 can be higher than first and mix
The doping concentration in miscellaneous area 23, for example, the first doped region 23 can be the doping of p-type intermediate concentration, the second doped region 24 can be N+
Type adulterates (that is, N-type heavy doping), and third doped region 25 can be P+ type doping (that is, p-type heavy doping), wherein intermediate concentration is mixed
The corresponding doping concentration of miscellaneous and heavy doping can refer to the prior art, and it will not be described for the present embodiment.
In the present embodiment, the first doped region 23, the second doped region 24, third doped region 25 can pass through diffusion or ion
The modes such as injection are formed, and specific generation type can refer to the prior art, and it will not be described the present embodiment.
Fig. 3 is a schematic cross-section of the position A-A of Fig. 2, it is shown that is provided with cutting for the position of the second doped region 24
Face schematic diagram.As shown in figure 3, the first doped region 23 can be located in semiconductor column 22, the second doped region 24 can be located at first
In doped region 23, third doped region 25 can be located in the second doped region 24.In addition, also supplement is shown in Fig. 2 in Fig. 3
In the first electrode 26 that is not shown, the material of first electrode 26 can be aluminium or other conductive materials.
In the present embodiment, as shown in figure 3, the third doped region 25 can be contacted with first electrode 26, to make second
Doped region 24 is electrically connected via third doped region 25 with first electrode 26；In addition, as shown in figure 3, first electrode 26 and semiconductor
There can also be the first insulating layer 31 between the upper surface of substrate 20, position shape of first insulating layer 31 in third doped region 25
At there is opening, first electrode 26 can be contacted via the opening with third doped region 25 as a result,；In addition, as shown in figure 3,
The upper surface of one electrode 26 can cover second insulating layer 32, for protecting to first electrode 26.
In the present embodiment, as shown in Figures 2 and 3, semiconductor device 2 can also have second electrode 27, be located at ditch
The side wall 211 of slot 21.Between second electrode 27 and side wall 211, it is also provided with third insulating layer 28.In the present embodiment
In, second electrode 27 can be DOPOS doped polycrystalline silicon, in addition, second electrode 27 is also possible to other conductive materials.
In the present embodiment, as shown in Figures 2 and 3, semiconductor device 2 can also have third electrode 29.Third electrode
29 can be located at the back side of semiconductor substrate 20.The material of third electrode 29 can be aluminium or other conductive materials.
In the present embodiment, as shown in Figures 2 and 3, semiconductor device 2 can also have the 4th insulating layer 30.4th absolutely
Edge layer 30 can fill groove 21, and second electrode 27 and third insulating layer 28 in covering groove 21.
In the present embodiment, as shown in figure 3, the first doped region 23 can be used as area base stage (base) of semiconductor device 2,
Second doped region 24 can be used as area emitter (emitter) of semiconductor device 2, and third doped region 25 can be used as semiconductor
Area contact (contact) of device 2.
In the present embodiment, as shown in figure 3, in semiconductor device 2, first electrode 26 can connect with third doped region 25
Touching, so that first electrode 26 can play a role as emitter (emitter) electrode；Second electrode 27 can be used as grid
(gate) electrode can be turned on and off by adjacent two for example, by the voltage that is applied in second electrode 27 of control
Current channel (channel) in semiconductor column 22 clamped by two electrodes 27；Third electrode 29 can be used as collector
(collector) electrode.Semiconductor device 2 can become trench-type insulated gate bipolar transistor (Insulated as a result,
Gate Bipolar Transistor, IGBT), wherein in the state that current channel in semiconductor column 22 is opened, the
Electric current is flowed through between three electrodes 29 and first electrode 26.
In the present embodiment, as shown in figure 3, the substrate 20 of semiconductor device 2 may include dopant species and/or doping is dense
Spend different multiple layers, for example, can with the dopant species of each layer in Fig. 1 from semiconductor layer 41 into semiconductor layer 44 and/
Or doping concentration is identical, wherein in Fig. 1, N indicates the doping of N-type intermediate concentration, and N- indicates that N-type is lightly doped, and N+ indicates N-type weight
Doping, P indicate the doping of p-type intermediate concentration, and P+ indicates p-type heavy doping, about intermediate concentration doping, are lightly doped and heavy doping
Corresponding doping concentration can refer to the prior art, and it will not be described for the present embodiment.
In the present embodiment, as shown in figure 3, in the semiconductor substrate 20, the quantity of groove 21 can be at least two, ditch
The opening width Wa of slot 21 can be greater than the distance Wb at the interval between adjacent groove 21, and distance Wb can be semiconductor column
22 width, for example, the ratio of Wa and Wb can be 10:1~2:1.It is exhausted can to become wide groove for the semiconductor device 2 as a result,
Edge grid bipolar junction transistor (IGBT), to have lower saturation voltage between emitter electrode and passive electrode
Vcesat。
According to the present embodiment, by the way that the second doped region is discontinuously arranged, it can reduce from the second doped region and be injected into first
Therefore the carrier of doped region 23 can slow down the locked situation of wide insulated trench gate electrode bipolar type transistor (IGBT)；And
And the carrier quantity due to being injected into the first doped region 23 is reduced, the load short circuit current that semiconductor device is able to bear increases
Add, therefore, load short circuits margin characteristic can be obtained and be enhanced, and the lower wide insulated trench gate of saturation voltage Vcesat is double
Bipolar transistor.
It in the present embodiment, can be by the way that the ratio and/or ditch of the depth and width of the first doped region 23 be reasonably arranged
The ratio of the depth of slot 21 and the depth of the first doped region 23 makes semiconductor device 2 have good electrology characteristic.For example, such as
Shown in Fig. 2, the ratio of the depth D1 and width W1 of the first doped region 23 can be the depth of 4:1~4:5 etc. and/or groove 21
The ratio of the depth D1 of D2 and the first doped region 23 can be 7:1~2:1 etc..
In addition, the semiconductor device 2 of the present embodiment can be not limited to IGBT, such as: the substrate 20 of semiconductor device 2 it is each
Layer can have other doping types and concentration, alternatively, semiconductor device 2 can not have second electrode 27 and/or third electricity
Pole 29, alternatively, the first electrode 26 of semiconductor device 2, second electrode 27 and third electrode 29 can form other electrical connections
Mode etc., semiconductor device 2 can not also play the function as IGBT as a result, and play other function.
In addition, in the present embodiment, the substrate 20 of semiconductor device 2 can be common substrate, example in semiconductor field
Such as silicon, germanium silicon, germanium, gallium nitride (Gallium Nitride), silicon carbide (SiC), the present embodiment is not intended to limit this.
According to the present embodiment, the second doped region 24 is arranged by interruption, can reduce being injected into first from the second doped region and mix
Therefore the carrier in miscellaneous area 23 can slow down the locked situation of semiconductor device, also, due to being injected into the first doped region
23 carrier quantity is reduced, and the load short circuit current that semiconductor device is able to bear increases, thus load short circuits margin characteristic
It is enhanced.
Embodiment 2
The present embodiment provides a kind of electronic equipment, with semiconductor device described in embodiment 1.Due in embodiment 1
In, the structure of the semiconductor device is described in detail, content is incorporated in this, omits the description herein.
In the electronic equipment of the present embodiment, the second doped region of semiconductor device is arranged by interruption, can reduce from the
Two doped regions are injected into the carrier of the first doped region, therefore, can slow down the locked situation of semiconductor device, also, by
It being reduced in the carrier quantity for being injected into the first doped region, the load short circuit current that semiconductor device is able to bear increases, thus
Load short circuits margin characteristic is enhanced.
Combine specific embodiment that the application is described above, it will be appreciated by those skilled in the art that this
A little descriptions are all exemplary, and are not the limitation to the application protection scope.Those skilled in the art can be according to the application
Spirit and principle various variants and modifications are made to the application, these variants and modifications are also within the scope of application.
Claims (10)
1. a kind of semiconductor device, comprising:
Semiconductor substrate；
First doped region, along all vertical with the width direction of groove and depth direction being formed in the semiconductor substrate
Length direction extends；And
Second doped region is formed in first doped region, and second doped region is vertical with the length direction, is divided
Liftoff setting.
2. semiconductor device as described in claim 1, wherein
In the length direction, the spacing distance between the width of second doped region and adjacent second doped region
Ratio be 1:2~1:9.
3. semiconductor device as described in claim 1, wherein the semiconductor device also includes
Third doped region is formed in first doped region, also, the third doped region prolongs along the length direction
It stretches and second doped region intersects.
4. semiconductor device as claimed in claim 3, wherein
The doping type of first doped region and the second doped region is different,
First doped region is identical with the doping type of third doped region.
5. semiconductor device as claimed in claim 4, wherein
The doping concentration of the third doped region is higher than the doping concentration of first doped region.
6. semiconductor device as described in claim 1, wherein the semiconductor device also includes
Electrode is located at the side wall of the groove.
7. semiconductor device as described in claim 1, wherein
The ratio of distance between the opening width of the groove and the adjacent groove is 10:1~2:1.
8. semiconductor device as described in claim 1, wherein
The ratio of the depth and width of first doped region is 4:1~4:5.
9. semiconductor device as described in claim 1, wherein
The ratio of the depth of the groove and the depth of first doped region is 7:1~2:1.
10. a kind of electronic equipment, with semiconductor device as claimed in any one of claims 1-9 wherein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810153683.2A CN110190119A (en) | 2018-02-22 | 2018-02-22 | Semiconductor device and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810153683.2A CN110190119A (en) | 2018-02-22 | 2018-02-22 | Semiconductor device and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110190119A true CN110190119A (en) | 2019-08-30 |
Family
ID=67704626
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810153683.2A Withdrawn CN110190119A (en) | 2018-02-22 | 2018-02-22 | Semiconductor device and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110190119A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311121A (en) * | 2012-03-09 | 2013-09-18 | 三菱电机株式会社 | Vertical trench IGBT and method for manufacturing the same |
| CN104124271A (en) * | 2013-04-28 | 2014-10-29 | 三垦电气株式会社 | Semiconductor device |
| CN105321997A (en) * | 2014-08-05 | 2016-02-10 | 株式会社东芝 | Semiconductor device |
-
2018
- 2018-02-22 CN CN201810153683.2A patent/CN110190119A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103311121A (en) * | 2012-03-09 | 2013-09-18 | 三菱电机株式会社 | Vertical trench IGBT and method for manufacturing the same |
| CN104124271A (en) * | 2013-04-28 | 2014-10-29 | 三垦电气株式会社 | Semiconductor device |
| CN105321997A (en) * | 2014-08-05 | 2016-02-10 | 株式会社东芝 | Semiconductor device |
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Application publication date: 20190830 |