CN110176490A - A kind of semiconductor devices and its manufacturing method - Google Patents
A kind of semiconductor devices and its manufacturing method Download PDFInfo
- Publication number
- CN110176490A CN110176490A CN201910502096.4A CN201910502096A CN110176490A CN 110176490 A CN110176490 A CN 110176490A CN 201910502096 A CN201910502096 A CN 201910502096A CN 110176490 A CN110176490 A CN 110176490A
- Authority
- CN
- China
- Prior art keywords
- active area
- doped region
- area
- source
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 238000002955 isolation Methods 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 15
- 239000002245 particle Substances 0.000 abstract description 24
- 230000000694 effects Effects 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000008569 process Effects 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000750 progressive effect Effects 0.000 description 1
- 230000035755 proliferation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The embodiment of the present application provides a kind of semiconductor devices and its manufacturing method, semiconductor devices may include substrate, the first active area and the second active area of isolation structure isolation are formed through on substrate, the source-drain area of grid and grid two sides is wherein formed in the first active area, doped region is formed in second active area, doped region is consistent with the doping type of source-drain area, the doping particle in doped region in such second active area can make compensation for source-drain area, reduce the depleted region in substrate, improve the bulk effect of device, improves device performance.
Description
Technical field
This application involves semiconductor field, in particular to a kind of semiconductor devices and its manufacturing method.
Background technique
With the continuous development of semiconductor technology, MOS device gradually tends to high speed and high-performance, however in MOS device, lining
Bottom can generate certain influence (bulk effect) to the performance of device, such as the concentration that trap adulterates in substrate will affect the consumption in device
Slice width degree to the greatest extent, influences the cut-in voltage of device.
Usually, doping particle in the substrate can be spread, and cause the doping concentration of substrate to be declined, therefore
Depletion layer in metal-oxide-semiconductor broadens, and the cut-in voltage of device also increases with it, and effective voltage is relatively low, causes unnecessary power consumption.
Summary of the invention
In view of this, the application's is designed to provide a kind of semiconductor devices and its manufacturing method, device is improved
Bulk effect improves device performance.
To achieve the above object, the application has following technical solution:
The embodiment of the present application provides a kind of semiconductor devices, comprising:
Substrate；
The first active area and the second active area being isolated on the substrate by isolation structure；Shape in first active area
At the source-drain area for having grid and the grid two sides；Doped region, the doped region and institute are formed in second active area
The doping type for stating source-drain area is consistent.
Optionally, the doped region is identical as the doping concentration of the source-drain area.
Optionally, the doped region is connect by contact plug with external circuit.
Optionally, the doped region is located at the opposite two sides of first active area.
Optionally, the doped region constitutes the closed hoop for surrounding first active area.
Optionally, the doped region is polygon ring, annulus or elliptical ring.
Optionally, the width range of the doped region is 0.1~0.3um.
The embodiment of the present application provides a kind of manufacturing method of semiconductor devices, comprising:
Substrate is provided, is formed with isolation structure on the substrate, the isolation structure is for being isolated the first active area and the
Two active areas；
The source-drain area that grid and the grid two sides are formed in first active area, in second active area
Doped region is formed, the doped region is consistent with the doping type of the source-drain area.
Optionally, the source-drain area that grid and the grid two sides are formed in first active area, described
Doped region is formed in second active area, comprising:
Grid is formed in first active area；
The substrate of substrate and second active area to the grid two sides is doped, and forms the source-drain area
With the doped region.
Optionally, second active area constitutes the closed hoop for surrounding first active area.
It may include substrate that the embodiment of the present application, which provides a kind of semiconductor devices and its manufacturing method, semiconductor devices,
The first active area and the second active area of isolation structure isolation are formed through on substrate, wherein being formed with grid in the first active area
The source-drain area of pole and grid two sides is formed with doped region in the second active area, and doped region is consistent with the doping type of source-drain area,
The doping particle in doped region in such second active area can make compensation for source-drain area, reduce the depletion region in substrate
Domain improves the bulk effect of device, improves device performance.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the application
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 show a kind of schematic top plan view of semiconductor devices provided by the embodiments of the present application；
Fig. 2 show diagrammatic cross-section of the device in Fig. 1 on the direction AA；
Fig. 3 show the performance schematic diagram of the semiconductor devices provided in the embodiment of the present application；
Fig. 4 show doped region and the first active area relative position schematic diagram in the embodiment of the present application；
Fig. 5 show a kind of flow diagram of the manufacturing method of semiconductor devices provided by the embodiments of the present application；
Fig. 6-9 shows the structural representation formed during semiconductor devices according to the manufacturing method of the embodiment of the present application
Figure.
Specific embodiment
In order to make the above objects, features, and advantages of the present application more apparent, with reference to the accompanying drawing to the application
Specific embodiment be described in detail.
Many details are explained in the following description in order to fully understand the application, but the application can be with
It is different from other way described herein using other and implements, those skilled in the art can be without prejudice to the application intension
In the case of do similar popularization, therefore the application is not limited by the specific embodiments disclosed below.
Secondly, the application combination schematic diagram is described in detail, when the embodiment of the present application is described in detail, for purposes of illustration only, table
Show that the sectional view of device architecture can disobey general proportion and make partial enlargement, and the schematic diagram is example, is not answered herein
Limit the range of the application protection.In addition, the three-dimensional space of length, width and depth should be included in actual fabrication.
As the description in background technique, substrate can generate certain influence to the performance of device, usually, in substrate
Doping particle can spread, cause the doping concentration of substrate to be declined, consumption under the action of bulk effect, in metal-oxide-semiconductor
To the greatest extent layer can broaden, the cut-in voltage of device with increase with it, the effective voltage in device is relatively low, causes unnecessary power consumption.Mesh
Before can be carried out again after forming gate dielectric layer substrate trap doping, avoid the doping of the substrate in the forming process of gate dielectric layer
Concentration generates variation, however this mode affects to the quality of gate dielectric layer.
Based on the above technical problem, the embodiment of the present application provides a kind of semiconductor devices and its manufacturing method, semiconductor
Device may include substrate, and the first active area and the second active area of isolation structure isolation are formed through on substrate, wherein the
It is formed with the source-drain area of grid and grid two sides in one active area, doped region, doped region and source are formed in the second active area
The doping type in drain region is consistent, and the doping particle in doped region in such second active area can make compensation for source-drain area,
The depleted region in substrate is reduced, the bulk effect of device is improved, improves device performance.
In order to better understand the technical solution and technical effect of the application, below with reference to attached drawing to specific embodiment
It is described in detail.
Refering to what is shown in Fig. 1, being a kind of schematic top plan view of semiconductor devices provided by the embodiments of the present application, Fig. 2 is in Fig. 1
Diagrammatic cross-section of the device on the direction AA.Wherein, semiconductor devices includes: first on substrate 100 and substrate 100
Active area 110 and the second active area 130, the second active area 130 are isolated with the first active area 110 by isolation structure 131, and first
It is formed with the source-drain area 122 of 112 two sides of grid 112 and grid in active area 110, is formed with doped region in the second active area 130
132, doped region 132 is consistent with the doping type of source-drain area 122.
In the embodiment of the present application, substrate 100 can be semiconductor substrate, semiconductor substrate for example can for Si substrate,
Ge substrate, SiGe substrate etc., can also be includes the substrate of other elements semiconductor or compound semiconductor, such as GaAs, InP
Or SiC etc., it can also be laminated construction, such as Si/SiGe etc..In the present embodiment, which can be silicon substrate.
Isolation structure (not shown go out) can be already formed in substrate 100, isolation structure may include silica
Or the material of other active areas that can separate device, isolation structure for example can be shallow trench isolation (STI, Shallow
Trench Isolation), the substrate area around isolation structure is active area, and active area here may include first
Active area 110 and the second active area 130, isolation structure 131 between the first active area 110 and the second active area 130 can also be with
It is shallow trench isolation.
Grid 112 is formed on the substrate 100 of the first active area 110, it can be with shape between grid 112 and substrate 100
At there is gate dielectric layer 111.Gate dielectric layer 111 for example can be thermal oxide layer or other suitable dielectric materials, such as silica
Or high K medium material, high K medium grid material such as hafnium base oxide, HFO2, in HfSiO, HfSiON, HfTaO, HfTiO etc.
A kind of or in which several combination.Grid 112 can be single or multi-layer structure, such as can be polysilicon, amorphous silicon or gold
Belong to electrode material or their combination, metal electrode material can be the one or more combinations of TiN, TiAl, Al, TaN, TaC, W.
It could be formed with side wall 113 on the side wall of grid 112, side wall 113 can be laminated construction, may include oxidation
Silicon, silicon nitride, silicon oxynitride or their combination, in the embodiment of the present application, side wall 113 may include successively layer from inside to outside
Folded silica, silicon nitride, silica lamination.
It could be formed with source-drain area in 112 two sides of grid, for different MOS devices, such as (high pressure is double to expand DDD MOS
Dissipate leakage metal-oxide semiconductor (MOS), Double Diffused Drain MOSFET) device and LD MOS (horizontal proliferation metal oxygen
Compound semiconductor, Lateral Diffused MOS) device etc., the shape and forming process of source-drain area can be different.Below
By taking DDD MOS device as an example, the formation of the source-drain area of grid two sides is illustrated.
It could be formed with shallow doped region 121 in the substrate 100 of 112 two sides of grid, shallow doped region 121 can be used as device
Buffer area, can have the doping particle of N-type or p-type in shallow doped region 121, the concentration for adulterating particle is lower, and n-type doping is mixed
Foreign particle for example can be N, P, As, Sb etc., and the doping particle of p-type doping can be for example B, Al, Ga or In etc..
Source-drain area 122 can be formed in shallow doped region 121, and the doping particle concentration of source-drain area 122 is greater than shallow doped region
121 doping particle concentration, and the doping particle of source-drain area 122 is identical as the doping type of particle of shallow doped region 121.Shallowly mix
When the doping particle in miscellaneous area 121 is N-type, the doping particle of source-drain area 122 is N-type, and source-drain area 122 can be considered as N-type heavy doping
The area (N plus, NP)；When the doping particle of shallow doped region 121 is p-type, the doping particle of source-drain area 122 is p-type, source-drain area 122
The area p-type heavy doping (P plus, PP) can be considered as.
Specifically, source-drain area 122 can be located in shallow trench region 121 in the plane for being parallel to 100 surface of substrate
The heart, and the area of source-drain area 122 is significantly less than the area of shallow trench region 121, refering to what is shown in Fig. 1, in this way can with source-drain area 122 with
There is a certain distance, convenient for the normal work of DDD MOS device under high pressure between grid 112.The doping of source-drain area 122 is deep
Degree can be less than the doping depth of shallow doped region 121, with reference to shown in Fig. 2.
The second active area 130 can also be formed in the embodiment of the present application, on substrate 100, the second active area 130 and first have
It can be isolated by isolation structure 131 between source region 110.Wherein, that the second active area 130 characterizes is one on substrate 100
Subregion is doped the substrate 100 in the region, available doped region 132.Doped region 132 is mixed with source-drain area 122
Miscellany type is consistent, such as the doping particle of source-drain area 122 is N-type, then the doping particle of doped region 132 is also N-type, source-drain area
122 doping particle is p-type, then the doping particle of doped region 132 is also p-type.
The doping concentration of doped region 132 and source-drain area 122 can be identical, can be in this way while forming source-drain area 122
The substrate 100 of second active area 130 is doped, doped region 132 is obtained, as long as carrying out a doping process, thus
It can simplify manufacturing process；The doping concentration of doped region 132 can also according to the actual situation depending on, the doping with source-drain area 122
Concentration is different, in this way by doping process twice, can be respectively formed the source-drain area 122 for meeting practical doping concentration demand and mix
Miscellaneous area 132.When it is implemented, the doping concentration range of doped region 132 can be 1e13~1e16cm-2。
The depth of doped region 132 can according to the actual situation depending on, such as can be consistent with the depth of shallow doped region 121,
It can also be consistent with the depth of source-drain area.
Doping particle in second active area 130 can make compensation when device works for source-drain area 122, reduce lining
Depleted region in bottom improves the bulk effect of device.Refering to what is shown in Fig. 3, for the semiconductor devices provided in the embodiment of the present application
Performance schematic diagram, wherein voltage difference of the abscissa Vbs between substrate and source electrode, VTB is device under corresponding body-bias
Cut-in voltage includes the curve for being provided with the second active area 130 and not set second active area 130 in figure.It can be seen that
When Vbs is -20V, after being provided with the second active area, VTB can be enabled to reduce 0.8V or so, effectively increase device performance.
In the embodiment of the present application, doped region 132 can be located at at least side of the first active area 110.With the of rectangle
For one active area 110, can boundary using source-drain area 122 far from grid 112 as the first boundary of the first active area 110,
The side that first active area 110 is vertical with the first boundary is as the second boundary of the first active area 110.
Specifically, refering to what is shown in Fig. 4, showing for doped region 132 in the embodiment of the present application with 110 relative position of the first active area
It is intended to.Wherein, in Fig. 4 (a) doped region 132 be located at the first active area 110 the first boundary outside, and it is active to be present in first
The side in area 110；Doped region 132 is located at the outside on the first boundary of the first active area 110 in Fig. 4 (b), and is present in first and has
The two sides of source region 110.
Doped region 132 can be rectangular area, be also possible to the region of other shapes, such as border circular areas, oval area
Domain, polygonal region etc.., can be parallel with the first boundary close to the side on the first boundary in doped region 132, it can not also be with first
Boundary is parallel.It is understood that ruler diameter of the doped region 132 on the first boundary direction can be with the length phase on the first boundary
Together, the length on the first boundary, or the length less than the first boundary can also be greater than.Side of the doped region 132 on vertical first boundary
Upward ruler diameter can be a definite value, be also possible to the different values being set according to actual conditions.
Doped region 132 is located at the outside of the second boundary of the first active area 110 in Fig. 4 (c) and Fig. 4 (d), and is present in the
The side of one active area 110；Doped region 132 is located at the outside of the second boundary of the first active area 110 in Fig. 4 (e), and is present in
The two sides of first active area 110.
Doped region 132 can be rectangular area, be also possible to the region of other shapes.Close to the second side in doped region 132
The side on boundary, can be parallel with the second boundary, can not also be parallel with the second boundary.It is understood that doped region 132 is second
Ruler diameter on the direction on boundary can be identical as ruler diameter of the grid 112 on the direction of the second boundary, with reference to shown in Fig. 4 (c),
Ruler diameter of the grid 112 on the direction of the second boundary can be less than；Ruler diameter of the doped region 132 on the direction of the second boundary can also
With identical as the ruler diameter of the second boundary, with reference to shown in Fig. 4 (d) and Fig. 4 (e), the ruler diameter of the second boundary can also be more than or less than.
Ruler diameter of the doped region 132 on the direction of vertical the second boundary can be a definite value, be also possible to be set according to actual conditions
Different values.
In addition, doped region 132 can also be located at the first boundary of the first active area 110 and the outside of the second boundary simultaneously,
Such as can reside in three sides (not shown go out) of the first active area 110, it can also exist on the surrounding of the first active area 110,
It is shown in Figure 1.
When doped region 132 surrounds the surrounding of the first active area 110, doped region 132 be may be constructed around the first active area
110 closed hoop, such as can be polygon ring, annulus, elliptical ring etc., doped region 132 shown in FIG. 1 is straight-flanked ring.It mixes
The width in miscellaneous area 132 can be equal on different location, convenient for simplifying the technique for forming doped region 132, such as square shown in FIG. 1
In shape ring, the width on each side is all equal.When it is implemented, the width range of doped region 132 can be 0.1~0.3um.
Later, other processing technologys that can continue device may include: to form interlayer dielectric layer, and penetrate through interlayer
Contact plug of the dielectric layer to source-drain area 122, the contact plug of perforation interlayer dielectric layer to doped region 132, and in grid 112 be more
Interlayer dielectric layer is penetrated through when crystal silicon or amorphous silicon to the contact plug of grid 112 etc. (not shown go out), these contact plugs are respectively used to
Source and drain 122, doped region 132 and grid 112 are connect with external circuit, and then supplied for source and drain 122, doped region 132 and grid 112
Electricity.
The embodiment of the present application provides a kind of semiconductor devices, and semiconductor devices may include substrate, is formed on substrate
The first active area and the second active area being isolated by isolation structure, wherein being formed with grid and grid two in the first active area
The source-drain area of side is formed with doped region in the second active area, and doped region is consistent with the doping type of source-drain area, and such second is active
Doping particle in doped region in area can make compensation for source-drain area, reduce the depleted region in substrate, improve device
Bulk effect improves device performance.
Refering to what is shown in Fig. 5, be a kind of flow diagram of the manufacturing method of semiconductor devices provided by the embodiments of the present application,
This method may comprise steps of:
S101 provides substrate 100, is formed with isolation structure on substrate 100, for the first active area 110 and second to be isolated
Active area 130, with reference to shown in Fig. 6.
In the embodiment of the present application, substrate 100 can be semiconductor substrate, semiconductor substrate for example can for Si substrate,
Ge substrate, SiGe substrate etc., can also be includes the substrate of other elements semiconductor or compound semiconductor, such as GaAs, InP
Or SiC etc., it can also be laminated construction, such as Si/SiGe etc..In the present embodiment, which can be silicon substrate.
First active area 110 and the second active area 130 can be isolated by isolation structure 131, and isolation structure 131 for example may be used
To be shallow trench isolation.In the embodiment of the present application, the second active area 130 can be located at at least side of the first active area 110.
By taking the first active area 110 of rectangle as an example, can boundary using source-drain area 122 far from grid 112 as the first active area 110
First boundary, the side that the first active area 110 is vertical with the first boundary is as the second boundary of the first active area 110.
Specifically, with reference to shown in Fig. 4 (a) and Fig. 4 (b), the second active area 130 can be positioned at the of the first active area 110
The outside on one boundary, such as the second active area 130 are located at the side of the first active area 110, can also be located at the first active area 110
Two sides.Wherein, the second active area 130 can be rectangular area, be also possible to the region of other shapes, such as border circular areas,
Elliptical region, polygonal region, streamlined region etc..Second active area 130 is close to the side of the first active area 110, Ke Yiyu
First boundary of the first active area 110 is parallel, can not also be parallel with the first boundary of the first active area 110.
Specifically, the second active area 130 can be located at the first active area with reference to shown in Fig. 4 (c), Fig. 4 (d) and Fig. 4 (e)
The outside of 110 the second boundary, such as the second active area 130 can be located at the side of the first active area 110, can also be located at the
The two sides of one active area 110.Wherein, the second active area 130 can be rectangular area, be also possible to the region of other shapes, the
Two active areas 130 can be identical as ruler diameter of the grid 112 on the direction of the second boundary in the ruler diameter on the direction of the second boundary,
Can also be identical as the ruler diameter of the second boundary, it can also be other values.
Specifically, the second active area 130 can also be simultaneously positioned at the first boundary of first active area 110 and the second boundary
Outside, such as three sides (not shown go out) of the first active area 110 can be surrounded, it can also exist on the four of the first active area 110
It is week, shown in Figure 1.
Refering to what is shown in Fig. 6, Fig. 6 (a) is a kind of schematic top plan view of semiconductor devices provided by the embodiments of the present application, Fig. 6
(b) diagrammatic cross-section for the device in Fig. 6 (a) on the direction AA.The first active area 110 is surrounded in the second active area 130
When surrounding, the second active area 130 may be constructed the closed hoop around the first active area 110, which is closed rectangular ring.
S102 forms the source-drain area 122 of grid 112 and grid two sides, in the second active area in the first active area 110
Doped region 132 is formed in 130, doped region 132 is consistent with the doping type of source-drain area 122.
In the embodiment of the present application, gate dielectric layer 111 can also be formed before grid 112 and substrate 100.In grid 112
Formation process in, can growth gate dielectric material and grid material after, be patterned, to form gate dielectric layer
111 and grid 112 thereon, refering to what is shown in Fig. 7, Fig. 7 (a) is a kind of vertical view of semiconductor devices provided by the embodiments of the present application
Schematic diagram, Fig. 7 (b) are diagrammatic cross-section of the device on the direction AA in Fig. 7 (a).
After forming grid 112, source-drain area 122 can be formed in 112 two sides of grid.Specifically, can be 112 liang to grid
The substrate 100 of side is doped, to form source-drain area 122.It, can be first in the lining of 112 two sides of grid by taking DDD MOS device as an example
Shallow doped region 121 is formed in bottom 100, refering to what is shown in Fig. 8, side wall 113 is then formed on 112 side wall of grid, with reference to Fig. 9 institute
Show, then form source-drain area 122 in shallow doped region 121, with reference to shown in Fig. 1.Fig. 8 (a) and Fig. 9 (a) mention for the embodiment of the present application
A kind of schematic top plan view of the semiconductor devices supplied, Fig. 8 (b) and Fig. 9 (b) are respectively device in Fig. 8 (a) and Fig. 9 (a) in AA
Diagrammatic cross-section on direction.Wherein, the doping type of shallow doped region 121 is consistent with the doping type of source-drain area 122, and source and drain
The doping concentration in area 122 is greater than the doping concentration of shallow doped region 121.Form the doping process of shallow doped region 121 and source-drain area 122
Can there are many, such as ion implanting, diffusion etc..
After forming grid 112, doped region 132 can also be formed in the second active area 130.Specifically, can be to second
The substrate 100 of active area 130 is doped, to form doped region 132.The doping type one of doped region 132 and source-drain area 122
It causes, doped region 132 and the doping concentration of source-drain area 122 may be the same or different.It is understood that if doped region 132
It is identical as the doping concentration of source-drain area 122, can substrate 100 and the second active area 130 to 112 two sides of grid substrate 100
It is doped simultaneously, will pass through a doping process, is formed simultaneously source-drain area 122 and doped region 132.
The embodiment of the present application provides a kind of manufacturing method of semiconductor devices, provides substrate, isolation is formed on substrate
Structure forms the source and drain of grid and grid two sides for the first active area and the second active area to be isolated in the first active area
Area forms doped region in the second active area, and doped region is consistent with the doping type of source-drain area, mixing in such second active area
Doping particle in miscellaneous area can make compensation for source-drain area, reduce the depleted region in substrate, improve the bulk effect of device, mention
High device performance.
All the embodiments in this specification are described in a progressive manner, same and similar portion between each embodiment
Dividing may refer to each other, and the highlights of each of the examples are differences from other embodiments.
The above is only the preferred embodiment of the application, although the application has been disclosed in the preferred embodiments as above, so
And it is not limited to the application.Anyone skilled in the art is not departing from technical scheme ambit
Under, many possible changes and modifications all are made to technical scheme using the methods and technical content of the disclosure above,
Or equivalent example modified to equivalent change.Therefore, all contents without departing from technical scheme, according to the application's
Technical spirit any simple modification, equivalent variation and modification made to the above embodiment, still fall within present techniques side
In the range of case protection.
Claims (10)
1. a kind of semiconductor devices characterized by comprising
Substrate；
The first active area and the second active area being isolated on the substrate by isolation structure；It is formed in first active area
Grid and the source-drain area of the grid two sides；Doped region, the doped region and the source are formed in second active area
The doping type in drain region is consistent.
2. device according to claim 1, which is characterized in that the doping concentration phase of the doped region and the source-drain area
Together.
3. device according to claim 1, which is characterized in that the doped region is connect by contact plug with external circuit.
4. device according to claim 1 to 3, which is characterized in that it is active that the doped region is located at described first
The opposite two sides in area.
5. device according to claim 1 to 3, which is characterized in that the doped region, which is constituted, surrounds described first
The closed hoop of active area.
6. device according to claim 5, which is characterized in that the doped region is polygon ring, annulus or elliptical ring.
7. device according to claim 5, which is characterized in that the width range of the doped region is 0.1~0.3um.
8. a kind of manufacturing method of semiconductor devices characterized by comprising
Substrate is provided, isolation structure is formed on the substrate, the isolation structure has for the first active area and second to be isolated
Source region；
The source-drain area that grid and the grid two sides are formed in first active area, forms in second active area
Doped region, the doped region are consistent with the doping type of the source-drain area.
9. according to the method described in claim 8, it is characterized in that, described form grid and institute in first active area
The source-drain area for stating grid two sides forms doped region in second active area, comprising:
Grid is formed in first active area；
The substrate of substrate and second active area to the grid two sides is doped, and forms the source-drain area and institute
State doped region.
10. according to the method described in claim 8, it is characterized in that, second active area composition is active around described first
The closed hoop in area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910502096.4A CN110176490B (en) | 2019-06-11 | 2019-06-11 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910502096.4A CN110176490B (en) | 2019-06-11 | 2019-06-11 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110176490A true CN110176490A (en) | 2019-08-27 |
| CN110176490B CN110176490B (en) | 2020-04-21 |
Family
ID=67698091
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910502096.4A Active CN110176490B (en) | 2019-06-11 | 2019-06-11 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110176490B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1096135A (en) * | 1993-03-03 | 1994-12-07 | 松下电器产业株式会社 | Semiconductor device and manufacture method thereof |
| CN1841738A (en) * | 2005-03-29 | 2006-10-04 | 富士通株式会社 | Semiconductor device and fabrication process thereof |
| US20080173915A1 (en) * | 2006-04-14 | 2008-07-24 | Hsin-Chang Lin | Single-gate non-volatile memory and operation method thereof |
| CN101969072A (en) * | 2010-08-27 | 2011-02-09 | 东南大学 | Consumption type N-type lateral double-diffusion metal-oxide semiconductor for reducing voltage |
| CN201853710U (en) * | 2010-08-27 | 2011-06-01 | 东南大学 | Depletion N-type transversely double-diffused metal oxide semiconductor transistor for voltage reduction |
-
2019
- 2019-06-11 CN CN201910502096.4A patent/CN110176490B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1096135A (en) * | 1993-03-03 | 1994-12-07 | 松下电器产业株式会社 | Semiconductor device and manufacture method thereof |
| CN1841738A (en) * | 2005-03-29 | 2006-10-04 | 富士通株式会社 | Semiconductor device and fabrication process thereof |
| US20080173915A1 (en) * | 2006-04-14 | 2008-07-24 | Hsin-Chang Lin | Single-gate non-volatile memory and operation method thereof |
| CN101969072A (en) * | 2010-08-27 | 2011-02-09 | 东南大学 | Consumption type N-type lateral double-diffusion metal-oxide semiconductor for reducing voltage |
| CN201853710U (en) * | 2010-08-27 | 2011-06-01 | 东南大学 | Depletion N-type transversely double-diffused metal oxide semiconductor transistor for voltage reduction |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110176490B (en) | 2020-04-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7491988B2 (en) | Transistors with increased mobility in the channel zone and method of fabrication | |
| US10211309B2 (en) | Method and device for metal gate stacks | |
| US9159795B2 (en) | High side DMOS and the method for forming thereof | |
| KR101294917B1 (en) | Semiconductor devices containing trench mosfet with superjunctions | |
| JP2017005140A (en) | Insulated gate switching device and manufacturing method of the same | |
| US9679962B2 (en) | FinFET and method of manufacturing the same | |
| TWI585979B (en) | Simplified charge balance in a semiconductor device | |
| US20170288047A1 (en) | Shallow-Trench Semi-Super-Junction VDMOS Device and Manufacturing Method Therefor | |
| WO2019192243A1 (en) | Semiconductor device | |
| US20200052116A1 (en) | Semiconductor device | |
| TWI612661B (en) | Metal oxide semiconductor device having mitigated threshold voltage roll-off and threshold voltage roll-off mitigation method thereof | |
| US20150295070A1 (en) | Finfet and method for manufacturing the same | |
| CN105826360B (en) | Groove-shaped half super junction power device and preparation method thereof | |
| TWI633670B (en) | Power mosfets and methods for manufacturing the same | |
| US9543188B2 (en) | Isolation structure, method for manufacturing the same, and semiconductor device having the structure | |
| TW201403676A (en) | High voltage semiconductor device and the associated method of manufacturing | |
| TWI624065B (en) | Double diffused metal oxide semiconductor device and manufacturing method thereof | |
| CN110176490A (en) | A kind of semiconductor devices and its manufacturing method | |
| CN103794501B (en) | Transistor and forming method thereof | |
| US20150129925A1 (en) | Semiconductor device | |
| TWI703675B (en) | Semiconductor device and manufacturing method thereof | |
| CN105244375B (en) | PNIN/NPIP type SSOI TFET and preparation method with mutation tunnel junctions | |
| US11195947B2 (en) | Semiconductor device with doped region adjacent isolation structure in extension region | |
| JP2014504008A (en) | CMOS device and manufacturing method thereof | |
| TW201824558A (en) | Semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |