CN110175135B

CN110175135B - Memory device

Info

Publication number: CN110175135B
Application number: CN201910128529.4A
Authority: CN
Inventors: 李汉埈; 郭东勳; 李耀翰
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2018-02-19
Filing date: 2019-02-19
Publication date: 2024-01-30
Anticipated expiration: 2039-02-19
Also published as: US10600453B2; KR20190099624A; CN110175135A; US20190259430A1; KR102443031B1

Abstract

A memory device is disclosed. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer unit including a plurality of page buffers; and a driving determining unit determining whether to perform at least one of a precharge operation, a development operation, and a latch operation of a page buffer connected to the memory cell to which the read voltage is supplied.

Description

Memory device

The present application claims the benefit of priority of korean patent application No. 10-2018-0019276, which was filed on date 19 of 2 nd month 2018, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

Example embodiments of the inventive concepts relate to a memory device and/or a data processing method.

Background

Semiconductor memory devices may be classified as volatile semiconductor memory devices or nonvolatile semiconductor memory devices. Volatile semiconductor memory devices may have drawbacks in that: although the reading and writing speed is fast, the stored contents disappear when its power is cut off. On the other hand, even if the power supply of the nonvolatile semiconductor memory device is turned off, the nonvolatile semiconductor memory device can retain its contents. Accordingly, such a nonvolatile semiconductor memory device is used for storing contents to be saved regardless of whether or not power is supplied thereto.

A representative example of a non-volatile memory device is a flash memory device. Such flash memory devices are widely used as storage media for audio and video data in information technology devices such as computers, mobile phones, smart phones, personal digital assistants PDAs, digital cameras, camcorders, audio recorders, MP3 players, hand-held PCs, game consoles, facsimile machines, and scanners. Recently, in order to reduce the burden on mobile devices such as smart phones, high-capacity, high-speed input/output and low-power consumption technologies have been actively studied.

Disclosure of Invention

In one or more example embodiments of the inventive concepts, a non-volatile memory device and/or a data processing method may perform data processing operations that may significantly reduce the occurrence of erroneous bits in the device.

Example embodiments of the inventive concepts provide a memory device in which a remaining page buffer is not driven in synchronization with a sampling operation of data stored in a portion of the page buffer.

According to an example embodiment of the inventive concepts, a memory device includes: a memory cell array including a plurality of memory cells; a plurality of page buffers configured to store data associated with memory cells of the plurality of memory cells to which a read voltage is supplied; a processing circuit configured to determine whether to perform at least one of a precharge operation, a development operation, and a latch operation of a page buffer connected to a memory cell to which a read voltage is supplied.

The processing circuitry may be configured to select some of the plurality of page buffers as selected page buffers.

The processing circuit may be configured to select some of the plurality of page buffers such that bit lines connected to the selected page buffers are arranged in succession.

The processing circuit may be configured to select some of the plurality of page buffers such that bit lines connected to the selected page buffers are spaced apart from one another by an interval.

The processing circuitry may be configured to select some of the plurality of page buffers such that the processing circuitry is configured to precharge bit lines connected to selected page buffers and terminate precharging bit lines connected to unselected page buffers of the plurality of page buffers.

The processing circuit may be configured to develop the sense node associated with the selected page buffer and terminate the development of the sense node associated with the unselected page buffer of the plurality of page buffers.

The processing circuit may be configured to provide a latch control signal to a latch associated with a selected page buffer and terminate the latch providing the latch control signal to an unselected page buffer of the plurality of page buffers.

The processing circuitry may be configured to sample data stored in the selected page buffer.

According to an example embodiment of the inventive concepts, a memory device includes: a plurality of page buffers configured to store data associated with a memory cell to which a read voltage is supplied among a plurality of memory cells, and output the data stored in the plurality of page buffers; processing circuitry configured to: at least one of the on unit and the off unit of the memory unit is counted based on data output from a page buffer of the plurality of page buffers, which of the plurality of page buffers is a selected page buffer is determined, and the selected page buffer is driven.

The plurality of page buffers may be configured to sequentially output data stored therein.

The processing circuit is configured to count data output from the selected page buffer.

The selected page buffer may be configured to perform one or more of a precharge operation, a develop operation, and a latch operation.

The unselected ones of the plurality of page buffers are configured to: terminating execution of at least one of the precharge operation, the develop operation, and the latch operation.

According to an example embodiment of the inventive concepts, a memory device includes: a memory cell array including a plurality of memory cells; a plurality of page buffers configured to store data associated with a memory cell to which a read voltage is supplied among the plurality of memory cells, and sample data stored in a selected page buffer among the plurality of page buffers such that an unselected page buffer among the plurality of page buffers is not driven in synchronization with the sampling of the data.

The memory device may be configured to terminate a precharge operation on bit lines connected to the unselected page buffers.

The memory device may be configured to terminate a developing operation of the sense node associated with the unselected page buffer.

The memory device may be configured to terminate a latching operation of latches provided in the unselected page buffers.

The memory device may be configured to sequentially sample the selected page buffers.

The memory may further include: and a processing circuit configured to count at least one of an on unit and an off unit of the memory cell based on data output from the selected page buffer.

The processing circuit may be configured to calculate the bit fail value by counting at least one of the on cells or the off cells.

Explanation of the drawings

The above and other aspects, features and advantages of the exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:

fig. 1 is a block diagram schematically illustrating a memory system according to an example embodiment of the inventive concepts;

FIG. 2 is a detailed block diagram illustrating a memory device included in the memory system of FIG. 1;

fig. 3 is a circuit diagram showing an example of a memory block included in the memory cell array of fig. 1 and 2;

FIG. 4 is a cross-sectional view showing an example of memory cells included in the memory block of FIG. 3;

FIG. 5 is a graph indicating a voltage distribution based on threshold voltages when the memory cell of FIG. 3 is a multi-level cell;

FIG. 6 is a graph indicating a condition in which a threshold voltage of a memory cell in the graph of FIG. 5 is changed;

FIG. 7 is a graph indicating a read operation per page if the memory cell is a 3-bit multi-level cell;

FIG. 8 is a detailed block diagram illustrating an example of a memory device included in the memory system of FIG. 1;

Fig. 9A is a diagram illustrating a read operation of a memory cell according to an example embodiment of the inventive concepts;

fig. 9B is a diagram for explaining a read operation of a memory cell according to another example embodiment of the inventive concepts;

FIG. 10A is a schematic block diagram of a page buffer applicable to the example embodiment of FIG. 9A;

FIG. 10B is a schematic block diagram of a page buffer applicable to the example embodiment of FIG. 9B;

FIG. 11 is a block diagram indicating a memory system according to an example embodiment of the inventive concepts;

fig. 12 is a detailed block diagram of a driving determining unit according to an exemplary embodiment of the inventive concept;

fig. 13 to 16 are diagrams illustrating examples of selected page buffers according to example embodiments of the inventive concept;

fig. 17 is a detailed block diagram of a driving determining unit according to another exemplary embodiment of the inventive concept;

fig. 18 is a detailed block diagram of a driving determining unit according to another exemplary embodiment of the inventive concept;

fig. 19 is a block diagram indicating a computing system according to an example embodiment of the inventive concepts.

Detailed Description

Hereinafter, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

Fig. 1 is a block diagram schematically illustrating a memory system according to an example embodiment.

Referring to fig. 1, a memory system 1 may include a memory controller 10A and a memory device 20A. The memory device 20A may include a memory cell array 21, a page buffer unit 22, and a count unit 23.

The memory controller 10A may include an Error Correction Circuit (ECC) processing unit 11. The memory controller 10A controls the memory device 20A. The memory controller 10A may control programming, reading, and erasing operations with respect to the memory device 20A by providing an address ADDR, a command CMD, and a control signal CTRL to the memory device 20A.

The memory cell array 21 may include a plurality of memory blocks BLK0 to BLKa-1, where a is an integer of 2 or more, and each of the memory blocks BLK0 to BLKa-1 may include a plurality of pages. Each of the memory blocks BLK0 to BLKa-1 may include a plurality of memory cells arranged in an area where a plurality of word lines and a plurality of bit lines cross. In one example embodiment, the plurality of memory cells may be flash memory cells, and the memory cell array 21 may be a NAND flash memory cell array or a NOR flash memory cell array. Hereinafter, example embodiments of the inventive concept are described taking a case where a plurality of memory cells are flash memory cells as an example. However, the example embodiments are not limited thereto. According to example embodiments, the plurality of memory cells may be resistive memory cells, such as Resistive Random Access Memory (RRAM), phase change RAM (PRAM), or Magnetic RAM (MRAM).

The page buffer unit 22 may store data to be recorded in the memory cell array 21 or data read from the memory cell array 21. In an example embodiment, the page buffer unit 22 includes a plurality of page buffer groups PBG0 to PBGa-1, each of which may include a plurality of page buffers. The number of page buffer groups PBG0 to PBGa-1 may correspond to the number of memory blocks BLK0 to BLKa-1, and the number of the plurality of page buffers included in each of the plurality of page buffer groups PBG0 to PBGa-1 may correspond to the number of the plurality of bit lines included in each of the memory blocks BLK0 to BLKa-1.

For example, when a read operation for the memory device 20A is performed, the plurality of page buffers may store data of memory cells selected from the plurality of memory cells included in the memory cell array 21. As an example, each of the plurality of page buffers includes at least one latch to which a latch signal is sent to latch data about the memory cell.

For example, when a read operation is performed on the memory device 20A, the plurality of page buffers may read and store data regarding the selected memory cells by the read voltage. Further, in a different manner therefrom, the plurality of page buffers may read and store data regarding the selected memory cells by read voltages having different levels and perform logic operations on the stored data, respectively. In this case, the plurality of page buffers may respectively perform exclusive or (XOR) logical sum on two pieces of data respectively read from two adjacent voltage levels among different voltage levels.

Memory device 20A may include processing circuitry (not shown). The processing circuitry may be, but is not limited to: a processor, central Processing Unit (CPU), controller, arithmetic Logic Unit (ALU), digital signal processor, microcomputer, field Programmable Gate Array (FPGA), application Specific Integrated Circuit (ASIC), system on a chip (SoC), programmable logic unit, microprocessor, or any other device capable of executing operations in a defined manner.

The processing circuit may be configured as a special purpose computer by layout design or execution of computer readable instructions stored in a memory (not shown) to implement the counting unit 23, the counting unit 23 being used to count the number of memory cells from data stored in a plurality of page buffers.

As an example, when the read voltage is supplied, the counting unit 23 may count an off-cell (off-cell) or an on-cell (on-cell) of the memory cell from the data stored in each of the plurality of page buffers. Further, in another example, when a plurality of read voltages having different levels are provided, the counting unit 23 may count the number of on cells of the memory cells existing in each of a plurality of intervals separated by different voltage levels from data of a logic operation stored in each of a plurality of page buffers.

During a read operation of the memory cell, the counting unit 23 may count fail bits (fail bits) of data stored in the page buffer unit 22 from the calculated data. The counting unit 23 may count fail bits, calculate fail bits (hereinafter, also referred to as calculation fail bit values) and provide the calculated fail bit values to the memory controller 10A.

According to example embodiments, the counting unit 23 may count fail bits from data read by a dummy voltage supplied to the memory cell at the time of a pass/fail discrimination operation. For example, when the memory cell performs a read operation, the counting unit 23 may count not only data calculated from the supplied read voltage, but also failed bits from data calculated from the supplied dummy voltage during a separate pass/fail discrimination operation. In this case, the dummy voltage may have a voltage level different from that of the read voltage, and the dummy voltage may be configured to have one voltage level or a plurality of different voltage levels similar to the number of read voltages. Hereinafter, for convenience of explanation, a hypothetical case in which the count unit 23 calculates a failed bit value from the calculated data at the time of a read operation of the memory cell is taken as an example. However, the counting unit 23 according to an example embodiment of the inventive concept may calculate a fail bit from data calculated by the supplied dummy voltage at the time of a separate pass/fail discriminating operation.

The ECC processing unit 11 may determine whether there are errors in the data read from the memory device 20A and correct any errors. The ECC processing unit 11 may detect error bits of data read from the memory device 20A by comparing parity generated at the time of reading with parity stored at the time of programming the data, and correct the detected error bits.

Fig. 2 is a detailed block diagram illustrating a memory device included in the memory system of fig. 1.

Referring to fig. 2, the memory device 20A may include a memory cell array 21, a page buffer unit 22, a counting unit 23, control logic CL, a voltage generator VG, and a row decoder RD.

As described above, memory device 20A may include processing circuitry. The processing circuit may be configured as a special purpose computer by layout design or execution of computer readable instructions stored in a memory (not shown) to implement the counting unit 23 and the control logic CL.

The control logic CL may write data to the memory cell array 21 or output various control signals for reading data from the memory cell array 21 according to the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 10A. The control logic CL may write data to the memory cell array 21 or output various control signals for reading data. Various control signals from the control logic CL may be transmitted to the voltage generator VG, the row decoder RD, the page buffer unit 22, and the counting unit 23.

The voltage generator VG may generate a driving voltage VWL for driving the plurality of word lines WL based on a control signal received from the control logic CL. The driving voltage VWL may be a program voltage, a read voltage, or a pass voltage. The row decoder RD may activate some of the plurality of word lines WL based on the row address. During a read operation, the row decoder RD may apply a read voltage to a selected word line and a pass voltage to unselected word lines. Meanwhile, during a write operation, the row decoder RD may apply a program voltage to a selected word line and a pass voltage to unselected word lines. The plurality of page buffers included in the page buffer unit 22 may be connected to the memory cell array 21 through a plurality of bit lines BL, respectively. During a read operation, the plurality of page buffers may output stored data in the memory cell array 21 operated by the sense amplifier. Meanwhile, during a write operation, a plurality of page buffers may input data to be stored in the memory cell array 21 as operated by a write driver. The plurality of page buffers may be connected to the data input/output circuit through a plurality of data lines, respectively.

The counting unit 23 may count the number of memory cells from data stored in a plurality of page buffers. As described above, if one read voltage is supplied, the off cells or on cells of the memory cells may be counted, and if a plurality of read voltages having different levels are supplied, the number of memory cells existing in each of a plurality of intervals divided by the different voltage levels may be counted. Further, the counting unit 23 may calculate a fail bit value, and provide the calculated fail bit value to the control logic CL.

The control logic CL may determine whether programming passes or fails according to the fail bit value supplied from the counting unit 23. According to an example embodiment, if the fail bit value is below a desired (or, alternatively, a preset) threshold value, the memory device 20A may determine to skip a verify operation to be performed after additionally applying a program voltage, terminate a program operation, or perform programming with respect to a state of next programming.

Fig. 3 is a circuit diagram showing an example of a memory block included in the memory cell array of fig. 2. In fig. 3, for convenience of explanation, only the structure of a memory block (hereinafter, also referred to as a block) BLK0 is shown; however, the other blocks BLK1 to BLKa-1 may have the same configuration as the block BLK 0.

Referring to fig. 3, the memory cell array 21 may be a memory cell array of a NAND flash memory. Along the bit lines BL0 through BLd-1, the block BLK0 may include d strings (where d is an integer of 2 or more), where eight memory cells MCEL are connected in series in the string. Each string STR may include a drain select transistor STR1 and a source select transistor STR2 connected to both ends of the memory cells MCEL connected in series. The NAND flash memory device having the same configuration as fig. 3 performs erase on a block-by-block basis and performs programming by performing program on the basis of page PAGs corresponding to word lines WL0 to WL 7. Fig. 3 shows a case where eight pages PAGs for eight word lines WL0 to WL7 are provided in one block as an example. However, the block BLK0 of the memory cell array 21 according to an example embodiment of the inventive concept may have a different number of memory cells and pages from the number of memory cells MCEL and pages PAGs shown in fig. 3. Further, the memory device 20A of fig. 1 and 2 may include a plurality of memory cell arrays having the same configuration as the memory cell array 21 described above, which perform the same operation.

Fig. 4 is a cross-sectional view showing an example of memory cells included in the memory block of fig. 3.

Referring to fig. 4, a source S and a drain D are formed on a substrate SUB, and a channel region is formed between the source S and the drain D. A floating gate FG is formed on an upper portion of the channel region, and an insulating layer such as a tunnel insulating layer may be disposed between the channel region and the floating gate FG. A control gate CG is formed on top of the floating gate FG, and an insulating layer, such as a blocking insulating layer, is arranged between the floating gate FG and the control gate CG. Voltages required for programming, erasing and reading operations with respect to the memory cell MCEL may be applied in SUB, the source S and the control gate CG. The data stored in the memory cell MCEL can be read by discriminating the threshold voltage of the memory cell in the flash memory device. Then, the threshold voltage Vth of the memory cell is determined according to the amount of electrons stored in the floating gate FG. As more electrons are stored in the floating gate FG, the threshold voltage of the memory cell may be higher. Electrons stored in the floating gate FG of the memory cell MCEL may leak in the arrow direction for various reasons, and thus, the threshold voltage of the memory cell MCEL may be changed. For example, electrons stored in floating gate FG may leak due to wear of the memory cell. If programming of the memory cell MCEL is repeated and access operations (such as erasing and reading) are performed, an insulating film between the channel region and the floating gate FG may wear, and then electrons stored in the floating gate FG may leak. As another example, electrons stored in the floating gate FG may leak due to high temperature stress or temperature difference at the time of programming or reading.

Fig. 5 is a graph showing a distribution based on threshold voltages in the case where the memory cell MCEL of fig. 3 is a three-level cell TLC capable of storing 3-bit data per cell. Hereinafter, although an operation will be described taking a case where the memory cell is a three-level cell TLC as an example, a method to be described later is a four-level cell QLC capable of storing 4-bit data per cell, and it is determined that: it can be applied to multi-level cells capable of storing more than 4 bits of data.

Referring to fig. 5, the horizontal axis represents the threshold voltage Vth, and the vertical axis represents the number of memory cells MCEL. In the case where the memory cell MCEL is a 3-bit multi-level cell, the memory cell MCEL has one of the following states: an erase state E, a first program state P1, a second program state P2, a third program state P3, a fourth program state P4, a fifth program state P5, a sixth program state P6, and a seventh program state P7. In the case of a multi-level cell, since the interval between the distributions of threshold voltages is relatively narrow as compared to a single-level cell, the read reliability may be reduced in response to a minute change in the threshold voltage Vth in the multi-level cell. The first read voltage Vr1 has a voltage level between distributions of the memory cells MCEL having the erase state E and the first program state P1. The second read voltage Vr2 has a voltage level between distributions of the memory cells MCEL having the first program state P1 and the second program state P2. The third read voltage Vr3 has a voltage level between distributions of the memory cells MCEL having the second program state P2 and the third program state P3. The fourth read voltage Vr4 has a voltage level between distributions of the memory cells MCEL having the third program state P3 and the fourth program state P4. The fifth read voltage Vr5 has a voltage level between distributions of the memory cells MCEL having the fourth program state P4 and the fifth program state P5. The sixth read voltage Vr6 has a voltage level between distributions of the memory cells MCEL having the fifth program state P5 and the sixth program state P6. The seventh read voltage Vr7 has a voltage level between distributions of the memory cells MCEL having the sixth and seventh program states P6 and P7.

If the first read voltage Vr1 is applied to the control gate CG of the memory cell MCEL, the memory cell MCEL in the first programmed state P1 is turned off, and the memory cell MCEL in the erased state E is turned on.

If the first read voltage Vr1 is applied and the memory cell MCEL is turned on, a current flows through the memory cell MCEL, and if the memory cell MCEL is turned off, no current flows through the memory cell MCEL. Accordingly, the data stored in the memory cell MCEL can be distinguished based on whether the memory cell MCEL is turned on or not. In this way, the allocation of logical levels of data may vary according to example embodiments.

Fig. 6 is a graph showing a case where the threshold voltage of the memory cell MCEL is changed in the graph of fig. 5.

Referring to fig. 6, the memory cells MCEL respectively programmed in the erase state E and the first to seventh program states P1 to P7 may have a distribution changed by external stimulus and/or wear as shown in fig. 6. In fig. 6, the memory cell MCEL belonging to the hatched portion may cause a read error, and then, the reliability of the memory device 20A may be deteriorated. For example, when a read operation is performed on the memory device 20A by using the first read voltage Vr1, although the memory cell MCEL belonging to the hatched portion is programmed in the first programmed state P1, it may be determined to be in the erased state E by a decrease in the threshold voltage Vth. That is, among the memory cells programmed in the first program state P1, a memory cell having a threshold voltage Vth lower than the first read voltage Vr1 may be determined as a failed bit for the first program state P1.

Fig. 7 is a graph showing a read operation per page in the case where the memory cell is a 3-bit multi-level cell. The page of the 3-bit multi-level cell may include a plurality of bit pages, which may include a least significant bit LSB page, a center significant bit CSB page, and a most significant bit MSB page.

Referring to fig. 7, in case that the memory cell MCEL is a 3-bit multi-level cell, a read operation of the memory cell MCEL may be performed three times, and eight-bar information may be divided into three bit pages and output. In one example embodiment, the erase state E is assigned data "111", the first program state P1 is assigned data "110", the second program state P2 is assigned data "100", the third program state P3 is assigned data "000", the fourth program state P4 is assigned data "010", the fifth program state P5 is assigned data "011", the sixth program state P6 is assigned data "001", and the seventh program state P7 may be assigned data "101". However, according to example embodiments, the data assigned to each programmed state may be changed. The first bit page read corresponding to the least significant bit LSB page includes a read for a first valley VA1 between the erased state E and the first programmed state P1, and a read for a fifth valley VA5 between the fourth programmed state P4 and the fifth programmed state P5. The second bit page read corresponding to the center valid bit CSB page includes a read for a second valley VA2 between the first program state P1 and the second program state P2, a read for a fourth valley VA4 between the third program state P3 and the fourth program state P4, and a read for a sixth valley VA6 between the fifth program state P5 and the sixth program state P6. The third bit page read corresponding to the most significant bit MSB page includes a read for a third valley VA3 between the second program state P2 and the third program state P3, and a read for a seventh valley VA7 between the sixth program state P6 and the seventh program state P7.

In the stage of the first bit page reading, when a reading operation is performed on the first and fifth valleys VA1 and VA5, if it is an "off cell" in the first valley VA1 and an "on cell" in the fifth valley VA5, the first bit page data is "0". If not, the first bit page data may be output as "1". Next, in the stage of the second bit page reading, when a reading operation is performed on the second, fourth, and sixth valleys VA2, VA4, and VA6, if it is an "off cell" in the second valley VA2 and an "on cell" in the fourth valley VA4, the second bit page data is "0", and if it is an "off cell" in the sixth valley, the second bit page data is "0". If not, the second bit page data may be output as "1". Next, in the stage of the third-bit page reading, when a reading operation is performed on the third and seventh valleys VA3 and VA7, if it is an "off-cell" in the third valley VA3 and an "on-cell" in the seventh valley VA7, the third-bit page data is "0". If not, the third bit page data may be output as "1".

Fig. 8 is a detailed block diagram showing an example of the memory device 20A included in the memory system of fig. 1. In fig. 8, for convenience of explanation, it shows only the connection relationship between the memory block BLK0 and the page buffer group PBG 0. However, other memory blocks BLK1 to BLKa-1 and page buffer groups PBG1 to PBGa-1 may have similar connection relations.

Referring to fig. 8, the memory device 20A may include a memory block BLK0, a page buffer group PBG0, and a counting unit 23A (hereinafter, also referred to as a counting unit 23A).

The memory block BLK0 may include a page PAG, which may include d memory cells MC0, MC1, MC2, MC3, … …, MCd-1. Although only one page PAG included in the memory block BLK0 is shown in fig. 8, the memory block BLK0 may include a plurality of pages. The page buffer group PBG0 may include a plurality of page buffers PB0, PB1, PB2, PB3, … …, PBd-1, and the plurality of page buffers PB0, PB1, PB2, PB3, … …, PBd-1 may be connected to the memory cells MC0, MC1, MC2, MC3, … …, MCd-1 through the corresponding bit lines BL0, BL1, BL2, BL3, … …, BLd-1, respectively. The plurality of page buffers PB0, PB1, PB2, PB3, … …, PBd-1 may store data read from data to be recorded in the memory cell array 21 or data read from the memory cell array 21. The data stored in the plurality of page buffers PB0, PB1, PB2, PB3, … …, PBd-1 may be sequentially supplied to the counting unit 23A through the data output unit I/O.

Fig. 9A is a diagram illustrating a read operation of a memory cell according to an example embodiment of the inventive concepts.

Referring to fig. 9A, a read operation of a memory cell according to an example embodiment may be calculated by providing a read voltage to a word line of the memory cell. The memory controller 10A reads data from the memory cell MCEL by supplying two adjacent states (e.g., a read voltage between the sixth program state P6 and the seventh program state P7) of the memory cell MCEL to the memory cell MCEL. Then, the memory cell having the threshold voltage lower than the seventh read voltage Vr7 is read as "1", and the memory cell MCEL having the threshold voltage higher than the seventh read voltage Vr7 is read as "0". The read data is stored in the page buffer unit 22A, and the data stored in the page buffer unit 22 may be counted in the counting unit 23A.

The counting unit 23A may count the number of memory cells determined to be turned-off cells from the number of "0" s among the data read by the seventh read voltage Vr7, and count the number of memory cells determined to be turned-on cells from the number of "1" s among the data read by the seventh read voltage Vr 7.

On the other hand, when the count unit 23A performs the pass/fail discriminating operation, a fail bit may be calculated from the data read by the seventh read voltage Vr 7. As an example, the counting unit 23A counts the number of "0" s of the data read by the seventh read voltage Vr7 (e.g., the number of memory cells determined as the off-cell), operates on the difference of the counted number of the off-cell and the number of the memory cells in the seventh program state P7, and calculates the fail bit.

Fig. 9B is a diagram illustrating a read operation of a memory cell according to another example embodiment of the inventive concepts.

Referring to fig. 9B, a read operation of a memory cell according to an example embodiment may be performed by providing a plurality of read voltages having different levels to a word line of the memory cell. The memory controller 10A has two adjacent states of the memory cell MCEL. For example, the memory controller 10A supplies a plurality of read voltages Vr2_1, vr2_2, vr2_3 having different levels between the first program state P1 and the second program state P2 to the memory cell MCEL, and then reads data from the memory cell MCEL. The plurality of read voltages vr2_1, vr2_2, and vr2_3 correspond to set voltages for identifying the first program state P1 and the second program state P2. As an example, the read voltage Vr2_1 may correspond to the read voltage Vr2 in fig. 5 and 6, and the read voltages Vr2_2 and Vr2_3 may correspond to voltages distributed around the read voltage Vr 2_1. The memory device 20A performs a logical operation on data read from each of two adjacent read voltages among the plurality of read voltage levels, and may count the number of memory cells MCEL present in the plurality of sections based on the result of the logical operation. As a result of the counting, the memory controller 10A may detect a read voltage corresponding to a section where the number of memory cells is smallest among a plurality of sections, and determine the level of the detected read voltage as an optimal voltage level. Such a read voltage determination operation may be referred to as an on-chip valley search (hereinafter, OCVS) operation.

According to example embodiments, although the number of the plurality of read voltages vr2_1, vr2_2, vr2_3 having different levels is 3, example embodiments of the inventive concept are not limited thereto, the number of the plurality of voltage levels may be differently changed, and the read direction may be changed.

In the first step (step 1), the read voltage Vr2_1 is supplied to the word line to read data from the memory cell MCEL. Then, the memory cell MCEL having the threshold voltage Vth lower than the read voltage vr2_1 is read as "1", and the memory cell MCEL having the threshold voltage Vth higher than the read voltage vr2_1 is read as "0". In this way, the first data read from the first step (step 1) can be stored in the page buffer unit 22. In the second step (step 2), data is read from the memory cell MCEL at the read voltage vr2_2. Then, the memory cell MCEL having the threshold voltage Vth lower than the read voltage vr2_2 is read as "1", and the memory cell MCEL having the threshold voltage Vth higher than the read voltage vr2_2 is read as "0". In this way, the second data read in the second step can be stored in the page buffer unit 22. In the third step (step 3), each of the plurality of page buffers included in the page buffer unit 22 performs a logical operation on the first data read by the read voltage vr2_1 and the second data read by the read voltage vr2_2. In one example embodiment, each of the plurality of page buffers may perform an exclusive or (XOR) logical sum operation on the first data and the second data. The result of exclusive or (XOR) logical sum operation of the first data and the second data is "0" in the case of the memory cell MCEL in which the threshold voltage Vth is lower than the read voltage vr2_2, the result of exclusive or (XOR) logical sum operation of the first data and the second data is "1" in the case of the memory cell MCEL in which the threshold voltage Vth is between the voltage vr2_1 and the read voltage vr2_2, and the result of exclusive or (XOR) logical sum operation is "0" in the case of the memory cell MCEL in which the threshold voltage Vth is higher than the read voltage vr2_1. Accordingly, it may be determined whether the memory cell is included in a section divided by two adjacent read voltages vr2_1, vr2_2 based on the result of an exclusive or (XOR) logical sum operation of the first data and the second data. It can be seen that the memory cells are included in the interval where the result of the exclusive-or (XOR) logical sum operation is "1". In the fourth step (step 4), the counting unit 23 may count the number of "1" s in the result of exclusive or (XOR) logical sum operation performed in the page buffer unit 22. In this way, the counting unit 23 can count the number of memory cells present in each of the plurality of sections. The memory controller 10A may detect a read voltage corresponding to a section where the number of memory cells is smallest among a plurality of sections, and determine the level of the detected read voltage as an optimal voltage level.

On the other hand, when the count unit 23 performs the pass/fail discriminating operation, the fail bit may be calculated from the data read by the read voltages vr2_1, vr2_2, vr2_3. As one example, the count unit 23A may calculate the fail bit from the number of memory cells present in each of the plurality of intervals.

FIG. 10A is a schematic block diagram of a page buffer to be applied to the embodiment of FIG. 9A.

Referring to fig. 10A, a page buffer PB0 connected to a bit line BL0 may be connected to memory cells of a cell string STR. The page buffer PB0 includes a sense node SO connected to the bit line BL0. The page buffer PB0 may include at least one latch lt_1 connected to each sense node SO. During a read operation of the memory cell, bit line BL0 is precharged by the control logic. As an example, if the LOAD signal LOAD and the control signal BLSHF are activated, the bit line BL0 may be precharged to a specific level VBL. At this time, the high voltage transistor HNM1 may be kept turned on by the bit line selection signal BLSLT. Subsequently, if the load signal is deactivated, the charge charged in the sensing node SO flows to the bit line BL0 through the control signal BLSHF via the transistor NM 1. That is, a development (development) operation in which the potential change of the sense node SO occurs is performed. When the selected memory cell is an on cell, the charge charged in the sensing node SO may be discharged to the common source line CSL via the bit line BL0 and the channel of the string. In this case, since the current flowing from the sense node SO to the bit line BL0 is relatively high, the speed of the voltage dip of the sense node is relatively fast. In contrast, if the selected memory cell is an off cell, the charge charged in the sensing node SO is difficult to discharge to the common source line CSL via the bit line BL0. The latch lt_1 may be provided with a latch control signal ltch_1 that latches the state of development of the sense node SO. According to the latch control signal ltch_1, at least one latch lt_1 may latch data about the memory cell.

Referring to fig. 9A, in the case where the read voltage Vr7 is supplied to the word line of the memory cell, the latch control signal ltch_1 is applied to the latch lt_1, and the first latch lt_1 may latch data according to the application of the read voltage Vr 7. Although not shown in fig. 10A, the page buffer PB0 may include a switching element (e.g., an ENMOS transistor). The switching element may have an output terminal (e.g., a source) connected to a control terminal (e.g., a gate) and a counting unit 23A to which an output value of the page buffer is applied. Therefore, if the output value of the page buffer is "1", the switching element is turned on and may supply a small current to the counting unit 23A, and if the output value of the page buffer is "0", the switching element is turned off and may not supply a small current to the counting unit 23A. The counting unit 23A may count on units or off units of the memory cells based on the output data from the page buffer unit 22.

FIG. 10B is a schematic block diagram of a page buffer applicable to the example embodiment of FIG. 9B. Since the page buffer according to the embodiment of fig. 10B is similar to that according to the exemplary embodiment of fig. 10A, the repetitive description will be omitted, and differences will be mainly described.

Referring to fig. 10B, a page buffer PB0 connected to a bit line BL0 may be connected to memory cells of the cell string STR. The page buffer PB0 includes a sense node SO connected to the bit line BL0. The page buffer PB0 may include a plurality of latches lt_1, lt_2 connected to the sensing node SO, respectively. The bit line BL0 may be precharged by control logic when a read operation of the memory cell. As an example, if the load signal and the control signal are activated, the bit line BL0 may be precharged to a specific level VBL. At this time, the high voltage transistor HNM1 may be kept turned on by the bit line selection signal BLSLT. Subsequently, if the LOAD signal LOAD is deactivated, the charge charged in the sensing node SO flows to the bit line BL0 through the transistor turned on by the control signal BLSHF. That is, a developing operation in which a potential change of the sense node SO occurs is performed. The plurality of latches lt_1, lt_2 may be provided with latch control signals ltch_1, ltch_2 that latch the state of development of the sense node SO. The plurality of latches lt_1, lt_2 may latch data about the memory cell according to the latch control signals ltch_1, ltch_2. As an example, the latch control signals ltch_1, ltch_2 may be sequentially provided. The latches lt_1, lt_2 may perform a plurality of latch operations in a consecutive order for calculating memory cells existing in a section among read voltages having different levels.

Referring to fig. 9B, when the read voltage vr2_1 is supplied to the word line of the memory cell, the latch control signal ltch_1 is applied to the first latch lt_1, and the first latch lt_1 may latch the first data according to the application of the read voltage vr2_1. Subsequently, when the read voltage vr2_2 is applied to the word line of the memory cell, the second latch lt_2 may latch the second data according to the application of the read voltage vr2_2. Accordingly, the latches lt_1 and lt_2 can sequentially latch data according to a plurality of read voltages.

The page buffer PB0 may perform exclusive or (XOR) logical sum operation on the data stored in the latches lt_1 and lt_2, and calculate a logical result corresponding to a section between a plurality of read voltages. The counting unit 23A may output a count result by counting the number of memory cells existing in each of the plurality of sections based on the result of the logical operation output in the page buffer unit 23A. The counting unit 23A may count the number of memory cells present in each of the plurality of sections by counting the number of "1" present in each of the plurality of sections among the results of exclusive or (XOR) logical sum operations output from the page buffer unit 22A.

On the other hand, assuming that the data stored in the page buffers PB0 to PBd-1 included in one page buffer group are uniformly distributed, the number of memory cells may be counted by sampling the data stored in a part of the page buffers PB0 to PBd-1 included in one page buffer group. This sampling scheme may be suitable for counting the number of multi-level memory cells (such as four-level cells QLC) storing more data than three-level cells TLC, or for counting failed bits.

Specifically, considering that the page buffers PB0 to PBd-1 are connected to the counting unit via one data output unit, by sampling some stored data among the page buffers PB0 to PBd-1 and counting the number of memory cells, the time required to count the memory cells can be effectively reduced. However, when the remaining page buffers that are not sampled are operated, unnecessary power may be consumed according to the operation of the remaining page buffers.

Fig. 11 is a block diagram illustrating a memory system according to an exemplary embodiment of the inventive concept.

Referring to fig. 11, the memory system 2 may include a memory controller 10B and a memory device 20B.

Since the memory system 2 according to the example embodiment of fig. 11 is similar to the memory system 1 according to the example embodiment of fig. 1, the repetitive description will be omitted, and differences will be mainly described. In comparison to the memory system 1 according to the example embodiment of fig. 1, the memory system 2 according to the example embodiment of fig. 11 may further include a drive determination unit 24.

Memory device 20B may include processing circuitry (not shown). The processing circuitry may be, but is not limited to: a processor, central Processing Unit (CPU), controller, arithmetic Logic Unit (ALU), digital signal processor, microcomputer, field Programmable Gate Array (FPGA), application Specific Integrated Circuit (ASIC), system on a chip (SoC), programmable logic unit, microprocessor, or any other device capable of executing operations in a defined manner.

The processing circuit may be configured as a dedicated computer by layout design or execution of computer-readable instructions stored in a memory (not shown) to implement the drive determination unit 24, the drive determination unit 24 being for determining page buffers to be driven and not driven among page buffers of the page buffer groups PBG0 to PBGa-1 included in the page buffer unit 22.

As one example, the driving determination unit 24 is synchronized with the sampling operation determined by the mode, and may determine page buffers to be driven and not driven. The driving determination unit 24 may control a precharge operation, a development operation, and a latch operation.

Fig. 12 is a detailed block diagram of a driving determining unit according to an exemplary embodiment of the inventive concept.

Referring to fig. 12, the driving determining unit 24A according to an example embodiment of the inventive concept may include a page buffer selecting unit 241a, a precharge determining unit 242a, and a sampling determining unit 243a.

As described above, memory device 20B may include processing circuitry. The processing circuit may be configured as a special purpose computer by layout design or execution of computer-readable instructions stored in a memory (not shown) to implement the drive determination unit 24A including the page buffer selection unit 241a and the precharge determination unit 242a and the sampling determination unit 243a.

The page buffer selection unit 241a may select some of the page buffers included in the page buffer 22. The page buffer selection unit 241a may select N (a natural number smaller than d) page buffers among d (an integer greater than 1) page buffers PB0, PB1, PB2, PB3, … …, PBd-1 included in the page buffer unit 22.

Fig. 13 to 16 are diagrams illustrating examples of page buffers according to example embodiments of the inventive concepts.

Referring to fig. 13 to 16, the page buffer unit 22 may include 16 page buffers PB0, PB1, PB2, PB3, … …, PB15, and the page buffer selecting unit 241a may select N (N is a natural number smaller than 15) among the 16 page buffers PB0, PB1, PB2, PB3, … …, PB 15.

Referring to fig. 13, the page buffer selecting unit 241a may select 8 page buffers PB0, PB1, PB2, PB3, … …, PB7 connected to bit lines arranged in succession among 16 page buffers PB0, PB1, PB2, PB3, … …, PB15, and referring to fig. 14, the page buffer selecting unit 241a may select 4 page buffers PB0, PB1, PB2, PB3 connected to bit lines arranged in succession among 16 page buffers PB0, PB1, PB2, PB3, … …, PB 15. Further, referring to fig. 15, the page buffer selection unit 241a may select 4 page buffers PB0, PB4, PB8, PB12 connected to bit lines sequentially arranged to be spaced at a desired (or, alternatively, predetermined) interval among 16 page buffers PB0, PB1, PB2, PB3, … …, PB 15. Further, referring to fig. 16, the page buffer selection unit 241a may select a total of 8 page buffers PB0, PB1, PB4, PB5, PB8, PB9, PB12, PB13 by selecting 2 page buffers connected to bit lines arranged to be spaced at a desired (or, alternatively, predetermined) interval. Fig. 13 to 16 are merely examples indicating a selected page buffer, and the method of selecting a page buffer may be variously applied.

Referring again to fig. 12, the precharge determining unit 242a may determine a precharge operation of charging the bit lines connected to the page buffer. The precharge determining unit 242a may precharge bit lines connected to the N page buffers selected by the page buffer selecting unit 241a, and terminate the precharge of bit lines connected to the remaining (d-N) page buffers. Thus, the power consumption of the memory core may be reduced from the precharge termination.

The sampling determination unit 243a may sample the data stored in the page buffer to supply the data to the counting unit 23. As an example, the sampling operation may be performed by outputting units of data connected to a plurality of page buffers. The sampling determination unit 243a may sample data stored in the N page buffers selected in the page buffer selection unit 241a, and provide the sampled data to the counting unit 23.

The counting unit 23 may count the read results or the logical operation results stored in the selected N page buffers.

Fig. 17 is a detailed block diagram of a driving determining unit according to another exemplary embodiment of the inventive concept.

The drive determination unit 24B according to the exemplary embodiment of fig. 17 is similar to the drive determination unit 24A according to the exemplary embodiment of fig. 12, and thus, duplicate description will be omitted, and differences therebetween will be mainly described.

Referring to fig. 17, the driving determining unit 24B may include a page buffer selecting unit 241B, a development determining unit 242B, and a sampling determining unit 243B.

As described above, memory device 20B may include processing circuitry. The processing circuit may be configured as a special purpose computer by layout design or execution of computer-readable instructions stored in a memory (not shown) to implement the drive determination unit 24B including the development determination unit 242B.

The development determining unit 242b may determine a development operation in which a potential change occurs in the sensing node SO. The development determining unit 242b develops the sensing nodes SO of the N page buffers selected in the page buffer selecting unit 241b, and the development of the sensing nodes SO of the remaining (d-N) page buffers may be terminated. Thus, the power consumption of the memory core may be reduced from the termination of the development operation.

Fig. 18 is a detailed block diagram of a driving determining unit of another exemplary embodiment of the inventive concept.

Since the drive determination unit 24C according to the embodiment of fig. 18 is similar to the drive determination unit 24A according to the exemplary embodiment of fig. 12, the duplicate description will be omitted, and the differences will be mainly described.

Referring to fig. 18, the driving determining unit 24C may include a page buffer selecting unit 241C, a latch determining unit 242C, and a sampling determining unit 243C.

As described above, memory device 20B may include processing circuitry. The processing circuit may be configured as a special purpose computer by layout design or execution of computer-readable instructions stored in a memory (not shown) to implement the drive determination unit 24C including the latch determination unit 242C.

The latch determining unit 242c may determine whether to provide a latch signal to a latch of each of the plurality of page buffers. The latch determining unit 242a may supply a latch signal for latching data about the memory cell to the latch included in each of the N page buffers selected in the buffer selecting unit 241c, and terminate the supply of the latch signal to the latch included in each of the remaining (d-N) page buffers. Accordingly, the power consumption of the memory core may be reduced from the termination of the latch operation.

Fig. 19 is a block diagram illustrating a computing system according to an example embodiment of the inventive concepts.

Referring to fig. 19, a computing system 1000 may include a processor 1100, a RAM 1200, an input/output device 1300, a power device 1400, and a memory system 1 (or 2). Meanwhile, although not shown in fig. 19, the computing system 1000 may communicate with a video card, a sound card, a memory card, a USB device, or further include ports capable of communicating with other electronic devices. The computing system 1000 may be implemented as a personal computer or portable electronic device, such as a notebook computer, a mobile telephone, a personal digital assistant PDA, and a camera. The processor 1100 may perform specific calculations or tasks. According to an example embodiment, the processor 1100 may be a microprocessor, a central processing unit CPU. The processor 1100 may communicate with the RAM 1200, the input/output device 1300, and the memory system 1 through a bus 1500 such as an address bus, a control bus, and a data bus. According to an example embodiment, the processor 1100 may be connected to an expansion bus such as a peripheral component interconnect PCI.

RAM 1200 may store data required for the operation of computing system 1000. For example, RAM 1200 may be implemented as DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and/or MRAM.

Input/output devices 1300 may include input devices (such as keyboards, keypads, mice) and output devices (such as printers, displays).

The power supply device 1400 may provide an operating voltage required for operation of the computing system 1000.

Although not disclosed, the memory system 1 according to the present exemplary embodiment may be provided to a storage device of an information processing device capable of exchanging a large amount of data in combination with an application chipset, a camera image processor, and a mobile DRAM.

The memory devices 20A and 20B and the memory systems 1 and 2 according to example embodiments of the inventive concepts may be implemented by using various types of packages. For example, memory devices 20A and 20B and memory systems 1 and 2 may be implemented using packages such as package on package (PoP), ball Grid Array (BGA), chip Scale Package (CSP), leaded plastic chip carrier (PLCC), plastic dual in line package (PDIP), wafer die package, die in wafer form, chip On Board (COB), ceramic dual in line package (CERDIP), plastic Metric Quad Flat Package (MQFP), thin Quad Flat Package (TQFP), small Outline Integrated Circuit (SOIC), shrink Small Outline Package (SSOP), thin Small Outline Package (TSOP), thin Quad Flat Package (TQFP), system In Package (SIP), multi-chip package (MCP), wafer level fabrication package (WFP), wafer level process stack package (WSP)).

According to one or more example embodiments, the above-described units and/or devices including the elements of the memory device 20A, 20B (such as, for example, the counting unit 23 and the drive determining unit 24 and sub-elements thereof) may be implemented using hardware, a combination of hardware and software, or a non-transitory storage medium storing software that may perform the functions of the units and/or devices.

The hardware may be implemented using processing circuitry, such as, but not limited to, one or more processors, one or more Central Processing Units (CPUs), one or more controllers, one or more Arithmetic Logic Units (ALUs), one or more Digital Signal Processors (DSPs), one or more microcomputers, one or more Field Programmable Gate Arrays (FPGAs), one or more systems on chip (socs), one or more Programmable Logic Units (PLUs), one or more microprocessors, one or more Application Specific Integrated Circuits (ASICs), or any other devices capable of responding to and executing instructions in a defined manner.

The software may include a computer program, program code, instructions, or some combination thereof, for individually or collectively instructing or configuring a hardware device to operate as desired. The computer program and/or program code may comprise a program or computer readable instructions, software components, software modules, data files, data structures, etc. that are capable of being implemented by one or more hardware devices, such as one or more of the hardware devices mentioned above. Examples of program code include both machine code, generated by a compiler, and higher level program code, executed using an interpreter.

For example, when the hardware device is a computer processing device (e.g., one or more processors, CPUs, controllers, ALUs, DSPs, microcomputers, microprocessors, etc.), the computer processing device may be configured to execute program code by performing arithmetic, logic, and input/output operations according to the program code. Once the program code is loaded into the computer processing means, the computer processing means may be programmed to execute the program code, thereby converting the computer processing means into special purpose computer processing means. In a more specific example, when program code is loaded into a processor, the processor becomes programmed to execute the program code and operations corresponding thereto, transforming the processor into a special purpose processor. In another example, the hardware device may be an integrated circuit (e.g., an ASIC) customized to a dedicated processing circuit.

A hardware device, such as a computer processing device, may run an Operating System (OS) and one or more software applications running on the OS. The computer processing apparatus may also access, store, manipulate, process, and create data in response to execution of the software. For simplicity, one or more example embodiments may be illustrated as one computer processing device, however, those skilled in the art will appreciate that a hardware device may include multiple processing elements as well as multiple types of processing elements. For example, a hardware device may include multiple processors or one processor and controller. Furthermore, other processing configurations are possible, such as parallel processors.

The software and/or data may be implemented permanently or temporarily in any type of storage medium including, but not limited to, any machine, component, physical or virtual device, or computer storage medium or apparatus capable of providing instructions or data to or for explanation by hardware devices. The software may also be distributed over network-connected computer systems so that the software is stored and executed in a distributed fashion. In particular, for example, software and data may be stored by one or more computer-readable recording media including an tangible or non-transitory computer-readable storage medium as discussed herein.

According to one or more example embodiments, the storage medium may also include one or more storage devices in units and/or devices. The one or more storage devices may be tangible or non-transitory computer-readable storage media, such as Random Access Memory (RAM), read Only Memory (ROM), persistent mass storage devices, such as disk drives, and/or any other similar data storage mechanism capable of storing and recording data. The one or more storage devices may be configured to store computer programs, program code, instructions, or some combination thereof for one or more operating systems and/or for implementing the example embodiments described herein. The computer program, program code, instructions, or some combination thereof, may also be loaded into the one or more storage devices and/or the one or more computer processing devices from a separate computer-readable storage medium using a drive mechanism. Such separate computer-readable storage media may include Universal Serial Bus (USB) flash drives, memory sticks, blu-ray/DVD/CD-ROM drives, memory cards, and/or other similar computer-readable storage media. The computer program, program code, instructions, or some combination thereof, may be loaded from a remote data storage device into one or more storage devices and/or one or more computer processing devices via a network interface, rather than via a computer readable storage medium. Furthermore, the computer program, program code, instructions, or some combination thereof, may be loaded into the one or more storage devices and/or the one or more processors from a remote computing system configured to communicate and/or distribute the computer program, program code, instructions, or some combination thereof over a network. The remote computing system may communicate and/or distribute computer programs, program code, instructions, or some combination thereof via a wired interface, an air interface, and/or any other similar medium.

For the purposes of the exemplary embodiments, one or more hardware devices, storage media, computer programs, program code, instructions, or some combination thereof, may be specially designed and constructed, or they may be well known devices that are altered and/or modified for the purposes of the exemplary embodiments.

Although example embodiments of the inventive concept have been described with reference to the example embodiments illustrated in the drawings, it is only by way of example, and it will be understood by those skilled in the art that various modifications and equivalent example embodiments may be made. Accordingly, the true scope of the disclosure should be determined by the following claims.

As described above, according to example embodiments of the inventive concepts, the remaining page buffers may not be driven in synchronization with a sampling operation of data stored in portions of the page buffers, thereby reducing power consumption in the page buffers and shortening a read time.

While exemplary embodiments have been shown and described, it will be apparent to those skilled in the art that changes and modifications may be made without departing from the scope of the exemplary embodiments of the inventive concept as defined by the following claims.

Claims

1. A memory device, comprising:

a memory cell array including a plurality of memory cells;

A plurality of page buffers configured to store data associated with memory cells of the plurality of memory cells to which a read voltage is supplied;

a processing circuit configured to determine whether to perform at least one of a precharge operation, a development operation, and a latch operation of a page buffer connected to a memory cell to which a read voltage is supplied,

wherein the processing circuit is configured to: selecting some of the plurality of page buffers as selected page buffers and driving the selected page buffers, wherein unselected page buffers among the plurality of page buffers are not driven.

2. The memory device of claim 1, wherein the processing circuit is configured to: some of the plurality of page buffers are selected such that bit lines connected to the selected page buffers are arranged consecutively.

3. The memory device of claim 1, wherein the processing circuit is configured to: some of the plurality of page buffers are selected such that bit lines connected to the selected page buffers are spaced apart from each other by an interval.

4. The memory device of claim 1, wherein the processing circuit is configured to: some of the plurality of page buffers are selected such that the processing circuitry is configured to precharge bit lines connected to selected page buffers and terminate precharging bit lines connected to unselected page buffers of the plurality of page buffers.

5. The memory device of claim 1, wherein the processing circuit is configured to: the development of the sense node associated with the selected page buffer is performed and the development of the sense node associated with the unselected page buffer of the plurality of page buffers is terminated.

6. The memory device of claim 1, wherein the processing circuit is configured to: providing a latch control signal to a latch of a selected page buffer and terminating the providing of the latch control signal to a latch of an unselected page buffer of the plurality of page buffers.

7. The memory device of claim 1, wherein the processing circuit is configured to: the data stored in the selected page buffer is sampled.

8. A memory device, comprising:

a plurality of page buffers configured to store data associated with a memory cell to which a read voltage is supplied among a plurality of memory cells, and output the data stored in the plurality of page buffers;

processing circuitry configured to:

counting at least one of an on unit and an off unit of the memory cell based on data output from one or more page buffers among the plurality of page buffers,

Determining which page buffers of the plurality of page buffers are selected page buffers,

the selected page buffer is driven and the page buffer is selected,

wherein an unselected page buffer among the plurality of page buffers is not driven.

9. The memory device of claim 8, wherein the plurality of page buffers are configured to: the data stored therein is sequentially output.

10. The memory device of claim 9, wherein the processing circuit is configured to: the data output from the selected page buffer is counted.

11. The memory device of claim 9, wherein the selected page buffer is configured to: one or more of a precharge operation, a develop operation, and a latch operation are performed.

12. The memory device of claim 11, wherein an unselected one of the plurality of page buffers is configured to: terminating execution of at least one of the precharge operation, the develop operation, and the latch operation.

13. A memory device, comprising:

a memory cell array including a plurality of memory cells;

a plurality of page buffers configured to store data associated with a memory cell to which a read voltage is supplied among the plurality of memory cells, and sample data stored in a selected page buffer among the plurality of page buffers such that an unselected page buffer among the plurality of page buffers is not driven in synchronization with the sampling of the data.

14. The memory device of claim 13, wherein the memory device is configured to: the precharge operation on the bit lines connected to the unselected page buffers is terminated.

15. The memory device of claim 13, wherein the memory device is configured to: the developing operation of the sense node associated with the unselected page buffer is terminated.

16. The memory device of claim 13, wherein the memory device is configured to: the latch operation of the latches provided in the unselected page buffers is terminated.

17. The memory device of claim 13, wherein the memory device is configured to: the data stored in the selected page buffer is sequentially sampled.

18. The memory device of claim 13, further comprising:

and a processing circuit configured to count at least one of an on unit and an off unit of the memory cell based on data output from the selected page buffer.

19. The memory device of claim 18, wherein the processing circuit is configured to: the fail bit value is calculated by counting at least one of the on cell and the off cell.