CN110174870A - PLC timing method, PLC timer and PLC controller - Google Patents
PLC timing method, PLC timer and PLC controller Download PDFInfo
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- CN110174870A CN110174870A CN201910414532.2A CN201910414532A CN110174870A CN 110174870 A CN110174870 A CN 110174870A CN 201910414532 A CN201910414532 A CN 201910414532A CN 110174870 A CN110174870 A CN 110174870A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/056—Programming the PLC
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Abstract
The invention provides a PLC timing method, a PLC controller and a computer readable storage medium, wherein the timing method comprises the steps of obtaining a set timer period and a set timer duration, and calculating a timing count value according to the timer duration and the set timer period; receiving a timing enable signal, changing the number of timing cycles once when one timing cycle is ended in the period of the timing enable signal, and outputting a timing end signal when the number of changes of the number of timing cycles reaches a timing count value. The PLC controller and the computer readable storage medium are used for realizing the PLC timing method. The invention can enable a user to freely set the timing period of the timer, the setting of the timer is very simple, and the precision of the timer is improved.
Description
Technical field
The present invention relates to logic programmable controller fields, specifically, being related to a kind of PLC timing method, realizing this side
The PLC timer and computer readable storage medium of method.
Background technique
In industrial control field, PLC's (Programmable Logic Controller, programmable logic controller (PLC))
It is very widely used, and timer is the important component of PLC.In general, the setting of the timer of PLC needs the mistake in programming
The timing cycle of timer internal is selected in journey and preset value is set, to determine that timing, such as setting need to select one
A or multiple timer internals, and determine the access times of each timer internal.It was run in the program of timer
Will be primary by refreshing after each timing cycle of Cheng Zhong, PLC timer internal, and count once, then by count value and in advance
Value to be set to be compared, when count value and equal preset value, the output state position of timer will be set to 1, i.e. output high level signal,
Indicate that timing terminates.
The PLC of different manufacturers slightly has difference in the design of timer, in general, being provided in a set of PLC system more
The timing cycle of a timer internal, multiple timer internals is not exactly the same, commonly in a kind of PLC system, multiple inside
The timing cycle of timer is respectively 1ms, 10ms, 100ms, and another common PLC is provided with high speed timer (timing week
Phase is 0.01s) and general timer (timing cycle 0.1s), there are also a kind of timing cycles of multiple timer internals of PLC
It is 8ms and 50ms respectively.
For example, the programmed range of the timer internal of existing a PLC be T0~T255, wherein timer internal T0,
The timing cycle of T64 be 1ms, timer internal T1~T4, T65~T68 timing cycle be 10ms, timer internal T5~
The timing cycle of T31, T69, T95 are 100ms.As can be seen that the quantity of the timer internal of this PLC only has 256, inside
The limited amount of timer, and timing cycle be 1ms timer internal quantity only there are two, for apply timing cycle
It is then the requirement for being unable to satisfy application for a fairly large number of occasion of timer internal of 1ms.
Due to being needed using multiple timer internals with fixed timing cycle when needing to set PLC timing length
Timing length is set by the way of the timer internal and preset value for selecting different timing cycles, this method is for PLC
Timer setting value calculating it is complex, calculation formula is as follows:
Wherein, T is total timing length, and PT is timer internal preset value, and S is the timing cycle of timer internal, and i is
I-th of timer internal, n are the total number of timer internal.When user carries out quadratic programming using PLC, need to pass through inside
Timer model corresponds to timing cycle, also needs setting preset value, increases user memory capacitance and calculation amount, and usage experience is poor,
And multiple timer internals are realized with total timing length.For example, for a PLC above-mentioned, it is assumed that total
Timing length is 183ms, needs the timer internal that a timing cycle is 100ms to execute 1 time, a timing cycle is 10ms
Timer internal execute 8 times, the timer internal that timing cycle is 1ms executes 3 times, not only execute often, but also
It needs the timer internal in three different timing periods to be used cooperatively, increases the workload of user's quadratic programming.
Referring to Fig. 1, the ladder diagram for the timer programming that existing PLC is used includes two ports, wherein IN is enabled letter
Number input terminal, programmed range T0 to T255, PT are setting value input terminal, maximum preset value 32767.When enable signal input terminal
When inputting effectively (connection), timer starts timing, and the current value of timer count is incremented by since 0, be greater than when count value or
When equal to setting value (PT), timer output state position is 1, that is, exports the signal that timing terminates, the maximum of timer count
Value is 32767.When enable signal input terminal invalid (disconnection), the count value of timer is kept, enable signal input terminal (IN)
When being again switched on effective, it is incremented by timing on the basis of the count value originally recorded.
Therefore, when being timed operation using this PLC timer, operating process is as shown in Fig. 2, be first carried out step
S1 needs the timer internal using which timing cycle according to total timing length setting and determines each internal timing
Then the access times of device execute step S2, the model of multiple timer internals, example are successively selected according to multiple timing cycles
It such as selects timing cycle for the timer internal of 100ms, 10ms and 1ms, then executes step S3, successively determine that multiple inside are fixed
When device timing number, finally execute step S4, write the PLC control logic of multiple timer internals.Set timer
It, will be according to the program of the control logic run timing device set when PLC run timing device after control logic.
Although the timing accuracy of the timer internal of existing PLC is very high, such as timing cycle can reach 1ms, its
Timing length is limited, and timing length it is longer or design in using timer internal quantity it is more when, timer internal is not
Disconnected is refreshed, other programs, which are executed, has cumulative influence, so that executing efficiency be made to decline, or even generates journey
Sequence executes the fatal error overflowed.
Such as needing to set total timing length as 50s, in multiple timer internals of PLC, timing cycle is longest interior
The timing cycle of portion's timer is 100ms, then needs this timer internal to execute 500 fixed cycle operators, that is, internal
Timer needs to refresh 500 times, and the count value that refreshing will be timed device every time adds the behaviour being compared together with preset value
Make, that is, executes the dependent instruction of program, and the execution instructed needs the time, it is assumed that 20 μ s of time-consuming are executed instruction each time,
Timing error after then refreshing 500 times is 10ms, and accumulative error is larger, and error is tired out step by step with the increase of refreshing frequency
Add.
In addition, interfering with each other between timer also can't be ignored, such as PLC when the timer that programming uses is more
After programming there are three set timings, three timings distinguish 5s, 7s, 8s, then need using three timers point
It is not timed operation, it is assumed that the timer internal that all selection timing cycle is 100ms is timed, and every 100ms that crosses needs to locate
Manage the processing function of three timers, it is assumed that a processing function 20 μ s of time-consuming, then 60 μ of processing function time-consuming of three timers
S, the timing error that timer internal refreshes every time increase three times.Timing accuracy substantially reduces, and with timer number
Increase and the increase of refreshing frequency, timing error increase in geometric multiple.
Summary of the invention
The first object of the present invention is to provide the PLC that a kind of timer setting is simple and timer internal refreshing frequency is few
Timing method.
The second object of the present invention is to provide a kind of PLC controller for realizing above-mentioned PLC timing method.
The third object of the present invention is to provide a kind of computer readable storage medium for realizing above-mentioned PLC timing method.
The first purpose to realize the present invention, PLC timing method provided by the invention include obtaining the timer set to determine
When period and timing length time counter value calculated according to timing length and timing cycle；Timing enable signal is received,
The timing enable signal duration, at the end of a timing cycle, the variation of timing cycle number is primary, in timing cycle number
When change frequency reaches time counter value, timing end signal is exported.
By above scheme as it can be seen that user is when setting timer, it is only necessary to timing cycle and timing length are set, by fixed
When device voluntarily calculate timing cycle number, in this way, timer only needs to calculate primary timing when each timing cycle reaches
Number of cycles, when the timing cycle number currently calculated reaches time counter value, completion timing is operated.Since user can be certainly
Row setting timing cycle, for longer timing length, timing cycle can be arranged it is longer, such timing cycle number compared with
It is few, it can effectively avoid timer internal from frequently being executed the time of dependent instruction by refreshing, accumulative error is less, and it is fixed to improve
When precision.
On the other hand, when user sets timer, the timer internal for selecting multiple timing cycles different is not needed,
It does not need to calculate the access times of multiple timer internals, therefore does not need to remember the model of each timer internal and fixed
When the period, it is only necessary to set timing cycle and total timing length, time set operation is very simple.
One Preferable scheme is that, after obtaining timing cycle, set the timing value of PLC timer internal, timing cycle is
The integral multiple of the timing value of PLC timer internal.
It can be seen that the timing value of timer internal is determined according to the timing cycle of setting, it is preferred that timer internal
Timing value can be equal to setting timing cycle, that is, timer internal timing value reach when, that is, complete one timing week
The number that phase, in this way reduction timer internal execute fixed cycle operator, also reduces the instruction execution number after the completion of fixed cycle operator.
Further embodiment is that timing length is the integral multiple of timing cycle.In this way, executing the last one timing cycle
When, it can avoid the occurrence of and need to be implemented the problem of less than one timing cycle reaches timing length, be conducive to improve timing
Precision.
Further scheme is that timing length is whole less than or equal to preset threshold divided by the pre- quotient of timing cycle
Number.
It can be seen that timing length is the several times of timing cycle, and less than one preset threshold value of multiple, it is, for example, less than
5 or less than 8, the number of timing cycle can be reduced in this way, to reduce the comparison algorithm executed after timing cycle
Performed number.
Further scheme is after receiving timing enable signal and starting timing, before the output of timing end signal,
If timing enable signal is interrupted, then time out operates, and after the recovery of timing enable signal, continues Clocked operation.
As it can be seen that timer has timing memory function, i.e., it is not to reset timer at once after enable signal interruption,
But the timing numerical value that recording timer is current, the fixed cycle operator of remaining time is continued to execute after the recovery of timing enable signal,
To improve the flexibility of timing, various fixed cycle operators are carried out convenient for user.
Further scheme is that time out operation includes: the fixed cycle operator for suspending PLC timer internal, and is recorded
The internal timing value of current timing cycle number change frequency and PLC timer internal；Continuing Clocked operation includes: from note
The timing cycle number change frequency of record and the internal timing value of PLC timer internal start to continue timing.
In this way, timer can accurately record current timing, avoid timing after enable signal interruption
Error can continue fixed cycle operator after enable signal recovery at once.
One optional scheme is, after calculating time counter value, sets the initial value of timing cycle number as 0；One fixed
When end cycle when, timing cycle number increases primary, and when timing cycle number reaches time counter value, output timing terminates
Signal.
One optional scheme is after calculating time counter value, to set the initial value of timing cycle number as timer counter
Value；At the end of one timing cycle, timing cycle number reduces once, and when timing cycle number is reduced to 0, output timing is tied
Beam signal.
It can be seen that the timing week that incremental mode calculates timer can be used after calculating time counter value
Phase number, also can be used the number that the mode successively decreased calculates timing cycle, and two ways can accurately calculate timing cycle
Number, and thus accurately calculate timing.
To realize that the second purpose for being, PLC controller provided by the invention have processor and memory, memory
It is stored with computer program, each step of above-mentioned PLC timing method is realized when computer program is executed by processor, or is held
Each step of the above-mentioned PLC timing method of row.
To realize that the third purpose for being, the present invention provide and be stored with computer program on computer readable storage medium,
Each step of above-mentioned PLC timing method is realized when computer program is executed by processor, or executes above-mentioned PLC timing method
Each step.
Detailed description of the invention
Fig. 1 is the ladder diagram of existing PLC timer.
Fig. 2 is the method flow diagram for setting existing PLC timer.
Fig. 3 is the ladder diagram of PLC timer applied by PLC timing method embodiment of the present invention.
Fig. 4 is the flow chart of PLC timing method embodiment of the present invention.
Fig. 5 is the schematic diagram of PLC timing method embodiment timing of the present invention.
Fig. 6 is using the flow chart for setting timer when PLC timing method embodiment of the present invention.
The invention will be further described with reference to the accompanying drawings and embodiments.
Specific embodiment
PLC timing method of the invention is applied in PLC controller, it is preferred that it applies on digital control system PLC software,
This method allows user freely to set the timing cycle of timer, improves PLC software fortune by improving timer underlying programs
Capable stability.PLC controller of the invention can apply the control in the equipment of industrial product, such as control the dynamic of mechanical arm
Work, running of numerically-controlled machine tool etc., the PLC controller have processor and memory, are stored with computer program on memory,
Processor realizes the PLC timing method by executing the computer program.
PLC timing method embodiment:
The present embodiment is applied to the control of industrial equipment, especially applies in PLC controller.Referring to Fig. 3, the present embodiment
The ladder diagram of applied timer includes four ports, is enable signal input terminal IN, timing end signal output end respectively
OUT, timing input terminal T and timing cycle input terminal S.When the signal of enable signal input terminal (IN) input is effective
When (connection), timer starts timing, and the timing cycle of timer is numerical value received by timing cycle input terminal S, when reaching
To timing length setting value, i.e. when numerical value received by timing input terminal T, the timing end signal output end of timer
(OUT) state changes, and becomes 1 from 0, i.e. output contact is effective.Preferably, when enable signal input terminal interrupts, timing
The timing pause TP of device, when enable signal input terminal is again switched on, i.e., after timing enable signal is restored, timing continues.
The workflow of the present embodiment is introduced below with reference to Fig. 4.Firstly, executing step S11, the timer of setting is obtained
Timing cycle and timing length.For example, when user needs to set a timer of PLC, it is first determined the timer is determined
Shi Shichang, such as 3s or 5s, then, user can set suitable timing cycle according to set timing length.Due to
It is not to realize timing using the fixed timer internal of several timing cycles, therefore, user can be free in the present embodiment
Set timing cycle.
Certainly, when the timing cycle of timer is set, need to consider following several factors.First, the timing cycle of setting
Duration cannot be greater than total timing length, such as timing length is 3s, and timing cycle is no more than 3s, if timing cycle is super
3s is crossed, as soon as then a timing cycle is not over, timing length is had arrived at, and is needed to export timing end signal, is set in this way
Fixed timing cycle just seems nonsensical.Second, the timing length of the timer of setting should be the integral multiple of timing cycle,
If the timing length of setting is not the integral multiple of timing cycle, the practical timing length of timer has error, error size
It is timing length divided by the remainder of timing cycle.Therefore, it in order to improve the timing accuracy of timer, needs to set timing length
It can since timing cycle S can freely be set by user, thus when user's setting timing cycle for the integral multiple of timing cycle
Using select timing length integer point one as timing cycle, in this way it is possible to prevente effectively from causing because timing cycle is unreasonable
Timing error.Third, even if timing length to be set as to the integral multiple of timing cycle, but if timing length is divided by timing week
The numerical value of the quotient of phase is excessive, indicates the timing length for needing just to reach setting after the multiple timing period.Due to the inside of PLC
After the every execution of timer is primary, the judgement skip operation of meeting once has certain delay, if the number executed is excessive,
Delay is also just accumulative, and actual timing length can increase to accumulation property, therefore timing error will increase, and influence PLC other
The execution efficiency of program even results in program and executes overflow error.Therefore, the multiple of the timing length of timer and timing cycle
Range should in a certain range, do not answer it is excessive, such as by the multiple be arranged in 5 or 10 integers below.For example, when setting
Timing length be 3s, timing cycle can be set as to 1s or 0.5s.
After user determines timing length and determines timing cycle according to timing length, the trapezoidal of timer is edited
Figure, as shown in Figure 3, by the set timing length of timing length input terminal T input, such as 3s, and pass through timing cycle
The timing cycle of input terminal S input setting, such as 0.5s.
Then, step S12 is executed, timer calculates timer counter according to acquired timing length and timing cycle
Value.The time counter value of the present embodiment is quotient of the timing length divided by timing cycle.Since the timing length of setting is timing week
The integral multiple of phase, therefore, time counter value are an integers, it is preferred that time counter value is one no more than preset threshold
Integer, such as no more than 5 or no more than 10.
In this way, after timer starts timing, of every timing cycle for passing through record by a timing cycle
Number, when the number of timing cycle reaches time counter value, expression timing terminates.Therefore, in the present embodiment, timer is set
Initial timing cycle number is 0, and every after a timing cycle, and timing cycle number increases by 1 time.
Then, step S13 is executed, the timing value of PLC timer internal is set.It sets the timing length of timer and determines
When the period after, by PLC timer internal execute timing cycle timing.In the present embodiment, PLC timer internal is by software
The timer of program setting, therefore the timing value of timer internal can according to need setting.Preferably, in step S13 setting
When the parameter of portion's timer, the value indirect assignment of timing cycle acquired in step S11 to timer internal, that is, it is internal
The timing value of timer is exactly the value of timing cycle.
Certainly, the timing value of timer internal is also not necessarily just equal to the timing cycle of timer, is also possible to timing
The one of the integer in period point, that is, timing cycle is the integral multiple of the timing value of PLC timer internal.In this way, when internal fixed
When device reach timing value once or several times after, just reach a timing cycle of timer.
Then, step S14 is executed, whether effective judges timing enable signal, that is, judge enable signal input terminal IN
Whether effective level signal, such as high level signal are received, if receiving effective level signal, confirmation receives fixed
When enable signal, otherwise, continue waiting for receive timing enable signal.
After confirmation receives timing enable signal, step S15 is executed, PLC timer internal starts timing, and executes step
Rapid S16 judges whether to reach a timing cycle.Since step S11 has set the timing cycle of timer, inside PLC
After timer starts timing, it can reach after or preset number primary in timing value that PLC timer internal reaches setting
One timing cycle.If not reaching a timing cycle, PLC timer internal continues timing.
When a timing cycle reaches, timer executes step S17, and timing cycle number increases primary.Then, it executes
Step S18, judges whether current timing cycle number reaches the time counter value of step S12 calculating.If current record
Timing cycle number reaches time counter value not yet, then it represents that timing reaches not yet, returns to step S15, PLC
Timer internal continues timing, if the timing cycle number of the timer of current record reaches time counter value, executes step
Rapid S19 exports timing end signal, i.e. the level letter of end signal output end OUT output by timing end signal output end OUT
Number become high level from low level, that is, end signal output end OUT output signal is 1.
Certainly, after step S12 calculates time counter value, can directly be by the initial value of the timing cycle number of timer
The time counter value, in this way, the timing cycle number that timer calculates reduces once at the end of a timing cycle, in this way,
When timing cycle number is reduced to 0, timing terminates, and timer exports timing end signal.It namely can be used and pass
The mode subtracted calculates timing cycle, equally can be realized method of the invention.
Preferably, there is memory function using the timer of the present embodiment, i.e., does not reach in the timing of timer
Before, if timing enable signal is interrupted, the timing that not will lead to timer is reset, but records current timing,
Timing enable signal continues timing after restoring.As shown in Figure 5, it is assumed that timing enable signal is at the beginning of the T1 period
Become high level from low level, i.e., from becoming effectively interrupting in the finish time of T1 period, but timing is also at this time in vain
Do not reach, then timer will not export timing end signal.At this point, timer grasps the timing for suspending PLC timer internal
Make, and records the internal timing value of current timing cycle number change frequency and PLC timer internal.
In T2 start time period, timing enable signal is restored, i.e., from becoming effective in vain, timer will continue at this time
Timing, that is, the timing cycle number change frequency that is recorded from T1 finish time period and PLC timer internal
Internal timing value starts to continue timing.Since in T2 finish time period, timing enable signal becomes wirelessly, but when timing again
Between still without reaching, therefore continue to execute the operation of timing pause TP, after timing enable signal is restored again, continue
Clocked operation.After reaching timing, timer will export timing end signal.As it can be seen that timing section shown in fig. 5
Interior, the timing length of timer is the temporal summation of three periods T1, T2, T3.
Since the present embodiment allows user's sets itself timing length and timing cycle, the use of timer is very
It is convenient, it only needs to set timing length and timing cycle in PLC programming.Referring to Fig. 6, when user sets timer,
Step S21 is first carried out, inputs the timing length and timing cycle of setting, such as the timing length of setting is 3s, setting
Timing cycle is 1s.Then, step S12 is executed, after the program of PLC executes, timer executes timing behaviour when meeting condition
Make, i.e., when the timing enable signal that enabled signal input part IN is received is effective, timer starts timing.
As it can be seen that operation is very easy for the timing method of the present embodiment, since the present embodiment is by improving timer bottom
Program makes user freely set the timing cycle of timer, and user does not need to remember the timing cycle of each timer internal,
It does not need to select multiple timer internals and determines the access times of each timer internal, the use for reducing timer is multiple yet
Miscellaneous degree improves the property easy to use of user.
In addition, timer internal refreshing frequency is excessive, causes program during the existing PLC fixed cycle operator of the present embodiment solution
Execution efficiency, which lowers, even leads to the problem of overflow error, improves the stability of PLC software operation.Also, due to internal timing
Device refreshing frequency is less, can reduce the error of timer, and then solves the problems, such as that existing timer timing accuracy is not high, mentions
The accuracy of high PLC timing.
In addition, the side that the present embodiment is combined using the timing cycle and high-precision bottom timing driving function of setting timer
Formula is realized, the precision of PLC timer is improved.
PLC controller embodiment:
The PLC controller of the present embodiment is applied to industrial control field, it is preferred that timing may be implemented in the PLC controller
Function, the PLC controller are equipped with processor and memory, are stored with the computer journey that can be run on a processor in memory
Sequence, and each step of above-mentioned PLC timing method is realized when processor execution computer program.
For example, computer program can be divided into one or more modules, one or more module, which is stored in, is deposited
It in reservoir, and is executed by processor, to complete modules of the invention.One or more modules can be can complete it is specific
The series of computation machine program instruction section of function, the instruction segment is for describing execution of the computer program in terminal device
Journey.
Processor alleged by the present invention can be central processing unit (Central Processing Unit, CPU), may be used also
To be other general processors, digital signal processor (Digital Signal Processor, DSP), specific integrated circuit
(Application Specific Integrated Circuit, ASIC), ready-made programmable gate array (Field-
Programmable Gate Array, FPGA) either other programmable logic device, discrete gate or transistor logic,
Discrete hardware components etc..General processor can be microprocessor or the processor is also possible to any conventional processor
Deng processor is the control centre of electric appliance, utilizes the various pieces of various interfaces and the entire electric appliance of connection.
Memory can be used for storing computer program and/or module, and processor is stored in memory by operation or execution
Interior computer program and/or module, and the data being stored in memory are called, realize the various functions of electric appliance.Storage
Device can mainly include storing program area and storage data area, wherein storing program area can storage program area, at least one function
Required application program (such as sound-playing function, image player function etc.) etc.；Storage data area can be stored according to electric appliance
Use created data (such as audio data, phone directory etc.) etc..In addition, memory may include high random access storage
Device can also include nonvolatile memory, such as hard disk, memory, plug-in type hard disk, intelligent memory card (Smart Media
Card, SMC), secure digital (Secure Digital, SD) card, flash card (Flash Card), at least one magnetic disk storage
Part, flush memory device or other volatile solid-state parts.
Computer readable storage medium:
If the computer program that the memory of PLC controller is stored is realized in the form of SFU software functional unit and conduct
Independent product when selling or using, can store in a computer readable storage medium.Based on this understanding, originally
The all or part of the process in above-described embodiment method is realized in invention, and relevant hardware can also be instructed by computer program
It completes, which can be stored in a computer readable storage medium, which is being executed by processor
When, it can be achieved that above-mentioned PLC timing method each step.
Wherein, computer program includes computer program code, and computer program code can be source code form, object
Code form, executable file or certain intermediate forms etc..Computer-readable medium may include: that can carry computer program
Any entity or device of code, recording medium, USB flash disk, mobile hard disk, magnetic disk, CD, computer storage, read-only memory
(ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electric carrier signal, electricity
Believe signal and software distribution medium etc..It should be noted that the content that computer-readable medium includes can be managed according to the administration of justice
Local legislation and the requirement of patent practice carry out increase and decrease appropriate, such as in certain jurisdictions, according to legislation and patent
Practice, computer-readable medium does not include electric carrier signal and telecommunication signal.
Finally it is emphasized that the present invention is not limited to the above embodiments, such as variation of the timing cycle of setting, or
The variation etc. of timer ladder diagram specific structure, it also should include within the scope of the invention as claimed that these, which change,.
Claims (10)
1.PLC timing method characterized by comprising
The timer timing cycle and timing length for obtaining setting are calculated according to the timing length and the timing cycle
Time counter value；
Timing enable signal is received, in the timing enable signal duration, at the end of a timing cycle, timing
Number of cycles variation is primary, and when the timing cycle number change frequency reaches the time counter value, output timing terminates
Signal.
2. PLC timing method according to claim 1, it is characterised in that:
After obtaining the timing cycle, the timing value of PLC timer internal is set, the timing cycle is fixed inside the PLC
When device timing value integral multiple.
3. PLC timing method according to claim 1 or 2, it is characterised in that:
The timing length is the integral multiple of the timing cycle.
4. PLC timing method according to claim 3, it is characterised in that:
The timing length is divided by the integer that the pre- quotient of the timing cycle is less than or equal to preset threshold.
5. PLC timing method according to claim 2, it is characterised in that:
After receiving the timing enable signal and starting timing, before timing end signal output, such as timing makes
Energy signal interruption, then time out operates, and after timing enable signal recovery, continues Clocked operation.
6. PLC timing method according to claim 5, it is characterised in that:
The time out operation includes: to suspend the Clocked operation of the PLC timer internal, and record current timing cycle
The internal timing value of number change frequency and the PLC timer internal；
The continuation Clocked operation includes: self-recording timing cycle number change frequency and the PLC timer internal
Internal timing value starts to continue timing.
7. PLC timing method according to claim 1 or 2, it is characterised in that:
After calculating the time counter value, the initial value of the timing cycle number is set as 0；
At the end of one timing cycle, the timing cycle number increases once, reaches institute in the timing cycle number
When stating time counter value, the timing end signal is exported.
8. PLC timing method according to claim 1 or 2, it is characterised in that:
After calculating the time counter value, the initial value of the timing cycle number is set as the time counter value；
At the end of one timing cycle, the timing cycle number reduces once, is reduced to 0 in the timing cycle number
When, export the timing end signal.
9.PLC controller, which is characterized in that including processor and memory, the memory is stored with computer program, described
Computer program realizes each step of PLC timing method as claimed in any one of claims 1 to 8 when being executed by the processor
Suddenly.
10. computer readable storage medium is stored thereon with computer program, it is characterised in that: the computer program is located
Reason device realizes each step of PLC timing method as claimed in any one of claims 1 to 8 when executing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910414532.2A CN110174870B (en) | 2019-05-17 | 2019-05-17 | PLC timing method, PLC timer and PLC controller |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110740552A (en) * | 2019-10-20 | 2020-01-31 | 北京芯思电子有限公司 | Timing electronic switch circuit and timing control method |
| CN111078190A (en) * | 2019-11-13 | 2020-04-28 | 珠海格力电器股份有限公司 | Single-precision floating-point number arithmetic operation control system and method of small PLC |
| CN116527737A (en) * | 2023-07-05 | 2023-08-01 | 英孚康（浙江）工业技术有限公司 | Multi-input single-output network connection control method for PLC single-threaded system in industrial control environment |
| CN117667235A (en) * | 2023-12-06 | 2024-03-08 | 广东保伦电子股份有限公司 | Event time period signal processing method, device, terminal equipment and medium |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008059105A (en) * | 2006-08-30 | 2008-03-13 | Okuma Corp | Data trace device for programmable logic controller |
| CN201464879U (en) * | 2009-06-30 | 2010-05-12 | 上海电器科学研究所（集团）有限公司 | Programmable controller with multi-circuit high-speed pulse output and high-speed counting functions |
| CN102323786A (en) * | 2011-07-01 | 2012-01-18 | 广西工学院 | Timer device comprising advanced reduced instruction set computer machine (ARM) and field programmable gate array (FPGA) and implementation method thereof |
| CN102789375A (en) * | 2012-07-25 | 2012-11-21 | 河南中烟工业有限责任公司 | Method for realizing timing by using adder and comparator |
| CN102914992A (en) * | 2011-08-03 | 2013-02-06 | 欧姆龙株式会社 | Synchronous control apparatus |
| CN103257670A (en) * | 2012-02-21 | 2013-08-21 | 北京国微集成技术有限公司 | Embedded system and timing method thereof |
| CN103425058A (en) * | 2012-05-15 | 2013-12-04 | 安凯(广州)微电子技术有限公司 | Timing method, central processing unit and electronic device |
| CN105183930A (en) * | 2015-06-16 | 2015-12-23 | 北京天诚盛业科技有限公司 | Methods and devices for setting and using hardware timer |
| JP2019016326A (en) * | 2017-07-11 | 2019-01-31 | 株式会社キーエンス | Programmable logic controller and data collection device |
-
2019
- 2019-05-17 CN CN201910414532.2A patent/CN110174870B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008059105A (en) * | 2006-08-30 | 2008-03-13 | Okuma Corp | Data trace device for programmable logic controller |
| CN201464879U (en) * | 2009-06-30 | 2010-05-12 | 上海电器科学研究所（集团）有限公司 | Programmable controller with multi-circuit high-speed pulse output and high-speed counting functions |
| CN102323786A (en) * | 2011-07-01 | 2012-01-18 | 广西工学院 | Timer device comprising advanced reduced instruction set computer machine (ARM) and field programmable gate array (FPGA) and implementation method thereof |
| CN102914992A (en) * | 2011-08-03 | 2013-02-06 | 欧姆龙株式会社 | Synchronous control apparatus |
| CN103257670A (en) * | 2012-02-21 | 2013-08-21 | 北京国微集成技术有限公司 | Embedded system and timing method thereof |
| CN103425058A (en) * | 2012-05-15 | 2013-12-04 | 安凯(广州)微电子技术有限公司 | Timing method, central processing unit and electronic device |
| CN102789375A (en) * | 2012-07-25 | 2012-11-21 | 河南中烟工业有限责任公司 | Method for realizing timing by using adder and comparator |
| CN105183930A (en) * | 2015-06-16 | 2015-12-23 | 北京天诚盛业科技有限公司 | Methods and devices for setting and using hardware timer |
| JP2019016326A (en) * | 2017-07-11 | 2019-01-31 | 株式会社キーエンス | Programmable logic controller and data collection device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110740552A (en) * | 2019-10-20 | 2020-01-31 | 北京芯思电子有限公司 | Timing electronic switch circuit and timing control method |
| CN111078190A (en) * | 2019-11-13 | 2020-04-28 | 珠海格力电器股份有限公司 | Single-precision floating-point number arithmetic operation control system and method of small PLC |
| CN111078190B (en) * | 2019-11-13 | 2021-06-18 | 珠海格力电器股份有限公司 | Single-precision floating-point number arithmetic operation control system and method of small PLC |
| CN116527737A (en) * | 2023-07-05 | 2023-08-01 | 英孚康（浙江）工业技术有限公司 | Multi-input single-output network connection control method for PLC single-threaded system in industrial control environment |
| CN116527737B (en) * | 2023-07-05 | 2023-09-22 | 英孚康（浙江）工业技术有限公司 | Multi-input single-output network connection control method for PLC single-threaded system in industrial control environment |
| CN117667235A (en) * | 2023-12-06 | 2024-03-08 | 广东保伦电子股份有限公司 | Event time period signal processing method, device, terminal equipment and medium |
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