CN110164488A - A kind of memory for supporting polynary storage configuration - Google Patents
A kind of memory for supporting polynary storage configuration Download PDFInfo
- Publication number
- CN110164488A CN110164488A CN201910275320.0A CN201910275320A CN110164488A CN 110164488 A CN110164488 A CN 110164488A CN 201910275320 A CN201910275320 A CN 201910275320A CN 110164488 A CN110164488 A CN 110164488A
- Authority
- CN
- China
- Prior art keywords
- input
- signal
- nand gate
- phase inverter
- option
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Dram (AREA)
Abstract
The present invention relates to a kind of memories, more specifically to a kind of memory for supporting polynary storage configuration.Purpose is to provide a kind of memory for supporting polynary storage configuration, comprising: polynary memory configuration mode；A kind of option selection logic is for selecting one of polynary storage configuration mode to operate memory.Bonding welding pad is input into the input terminal of option selection logic.Bonding welding pad can be configured to default selection mode, operate memory for selecting one of polynary storage configuration mode.Therefore, the present invention can support multiple memorizers configuration mode in the same system, without selecting different products.To which different systems need not be matched using various memories.
Description
Technical field
The present invention relates to a kind of memories, more specifically to a kind of memory for supporting polynary storage configuration.
Background technique
Synchronous Dynamic Random Access Memory (SDRAM) is the dynamic random access memory synchronous with computer system bus
Device (DRAM).In particular, the sync cap of SDRAM before responding input control, understands waiting system clock signal.Clock signal
For driving internal finite state machine to carry out pipeline to incoming order.Data storage areas is divided into several pieces,
Allow the multiple storage access commands of memory single treatment.This allows higher data access speed than asynchronous DRAM memory chip
Rate.
SDRAM is widely used in computer and mobile computing device, including mobile phone, tablet computer, global positioning system etc..
Several generations double data rate (DDR) SDRAM comes into general marketplace, including DDR1, DDR2, DDR3, DDR4.Joint electronics is set
Standby the engineering committee (JEDEC) is an independent semiconducter engineering trade organization and standardizing body, is every generation DDR
SDRAM issues code requirement.The specification of above-mentioned several generations and following DDR SDRAM, which are merged, to be hereby incorporated.
Mobile DDR (also referred to as mDDR, low-power consumption DDR or LPDDR) is a kind of double data rate synchronous dram, is suitable for
Intelligent movable mobile phone, tablet computer and other mobile computing devices.First generation low-power consumption DDR (sometimes referred to as " LPDDR1) it is DDR
A kind of form being modified slightly of SDRAM.It is modified by several places to reduce total power consumption.Most of all, supply voltage is from 2.5V
It is reduced to 1.2V.The power consumption additionally saved from temperature compensation refreshing, Partial Array Self Refresh and deep power down mode, (deposit by sacrifice
Store up content).LPDDR more of new generation, which has had, to be developed and sells, including LPDDR2, LPDDR3, LPDDR4 etc..Above-mentioned specification
The LPDDRn generation in the LPDDRn generation and any future, which is merged, to be hereby incorporated.
In order to use DDR SDRAM technology, terminal device has to pass through special designing, to use the configuration of DDR memory
One of.This may be for DDR SDRAM manufacturer it is expensive because different systems may use it is different types of
DDR SDRAM.For example, LPDDR2 can be used in a system, another system may use LPDDR3, can there are one system
LPDDR4 can be used.This means that DDR SDRAM manufacturer needs to manufacture the different system of various memory matcheds.
Summary of the invention
Based on the above, the object of the present invention is to provide a kind of memories for supporting polynary storage configuration, it supports more
Kind DDR SDRAM memory configuration mode.Additionally, it is necessary to which providing method selects a kind of storage configuration mode to operate storage
Device.
A kind of memory composition for supporting polynary storage configuration provided by the invention includes: polynary memory configuration mode；
A kind of option selection logic is for selecting one of polynary storage configuration mode to operate memory.Bonding welding pad is input into option
Select the input terminal of logic.Bonding welding pad can be configured to default selection mode, for selecting one of polynary storage configuration mode
Operate memory.Therefore, the present invention can support multiple memorizers configuration mode in the same system, to need not use each
Memory is planted to match different systems.
The embodiment of the present invention, which provides one kind, has polynary memory configuration memory, to solve or alleviate in the prior art
One or more technical problems.
The embodiment of the present invention provides option and selects logic, bonding welding pad, for selecting one of polynary storage configuration mode
Operate memory.
Polynary storage configuration mode includes low-power consumption double data rate 2(LPDDR2), low-power consumption double data rate 3
(LPDDR3), wherein polynary storage configuration mode has 32 input/output modes and 16 input/output modes.
Memory further comprises test pattern register, and test pattern register receives a certain test pattern register life
It enables, selects one of polynary storage configuration mode, one of polynary storage configuration mode originally selected is matched by another polynary storage
Set the covering of one of mode.
Bonding welding pad receives the first bonding welding pad signal, the second bonding welding pad signal and third bond pad signal, wherein
First OPTION signal, the second OPTION signal and third OPTION signal are generated, and wherein the polynary storage of option selection logic selection is matched
It sets one of mode and is used as the first bonding welding pad signal, the second bonding welding pad signal, third bond pad signal, the first option
The function of signal, the second OPTION signal and third OPTION signal.
It further comprises multiple latch to generate first, second, and third OPTION signal that option, which selects logic,.Wherein
Each latch include the first phase inverter, the second phase inverter, the first NAND gate, the second NAND gate, third NAND gate and the 4th with
NOT gate, wherein the second NAND gate of each latch generates first selection signal and the second selection signal.
For each latch,
The output of first phase inverter is input into the second NAND gate and third NAND gate,
The output of second phase inverter is input into the first NAND gate and the 4th NAND gate,
The operation code for carrying out self-testing mode register (TMR) order is input into the first NAND gate,
TMR order is input to the first NAND gate and third NAND gate,
Order reset signal is input to the second phase inverter,
The output of first NAND gate is input into the second NAND gate and third NAND gate,
The output of third NAND gate is input to the 4th NAND gate, wherein the output of the second NAND gate is input to the 4th NAND gate, the
The output of four NAND gates is input into the second NAND gate.
Wherein option selection logic further comprises the first nor gate, the second nor gate, the first phase inverter, the second reverse phase
Device, third phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, wherein the first nor gate, the first phase inverter, second
Phase inverter, third phase inverter serial connection, wherein the second nor gate, the 4th phase inverter, the 5th phase inverter, hex inverter are serial
Connection.Wherein the first OPTION signal is input to the first nor gate, wherein the first bonding welding pad signal is input to the first nor gate,
In the second OPTION signal be input to the second nor gate, wherein the second bonding welding pad signal is input to the second nor gate, wherein third
Phase inverter output is low-power consumption double data rate 2(LPDDR2) indicator that whether is activated of mode, wherein hex inverter is defeated
It is the indicator whether 16 input/output modes are activated out.
A kind of memory for supporting polynary storage configuration, it is characterized in that including:
Polynary storage configuration mode operates memory for selecting the option of one of multiple storage configurations to select logic；
And bonding welding pad, wherein bonding welding pad is input into the input terminal of option selection logic.
The bonding welding pad is configurable, and the function of the bonding welding pad is the institute in the polynary storage configuration mode
One kind of choosing.
The memory further comprises test pattern register, and wherein test pattern register receives a certain test mould
Formula register command, wherein function of one of the selected polynary storage configuration mode as the test pattern register command.
The memory, wherein a certain test pattern register command is input to option selection logic, as test mould
The function of formula register command, one of polynary storage configuration mode originally selected is by one of another polynary storage configuration mode
Covering.
The polynary storage configuration mode includes low-power consumption double data rate 2(LPDDR2), low-power consumption double data rate 3
(LPDDR3) and low-power consumption double data rate 4(LPDDR4), wherein polynary storage configuration mode have 32 input/output moulds
Formula and 16 input/output modes.
The bonding welding pad receives the first bonding welding pad signal, the second bonding welding pad signal and third bond pad letter
Number, wherein the first OPTION signal, the second OPTION signal and third OPTION signal are generated, wherein the selection of option selection logic is polynary
One of storage configuration mode is as the first bonding welding pad signal, the second bonding welding pad signal, third bond pad signal, the
The function of one OPTION signal, the second OPTION signal and third OPTION signal.
The memory option selection logic further comprises multiple latch to generate first, second, and third choosing
Item signal.Wherein each latch include the first phase inverter, the second phase inverter, the first NAND gate, the second NAND gate, third with it is non-
Door and the 4th NAND gate, wherein the second NAND gate of each latch generates first selection signal and the second selection signal.
The output of first phase inverter of each latch is input into the second NAND gate and third NAND gate, and second is anti-
The output of phase device is input into the first NAND gate and the 4th NAND gate, carrys out the operation generation of self-testing mode register (TMR) order
Code is input into the first NAND gate, and TMR order is input to the first NAND gate and third NAND gate, and order reset signal is input to the
Two phase inverters, the output of the first NAND gate are input into the second NAND gate and third NAND gate, the output input of third NAND gate
To the 4th NAND gate, wherein the output of the second NAND gate is input to the 4th NAND gate, the output of the 4th NAND gate is input into
Two NAND gates.
The output of first phase inverter of each latch is input into the second NAND gate and third NAND gate, and second is anti-
The output of phase device is input into the first NAND gate and the 4th NAND gate, and the operation code for carrying out self-testing mode register command is defeated
Enter to the first NAND gate, test pattern register command is input to the first NAND gate and third NAND gate, and order reset signal is defeated
Enter to the second phase inverter, the output of the first NAND gate is input into the second NAND gate and third NAND gate, third NAND gate it is defeated
It is input to the 4th NAND gate out, wherein the output of the second NAND gate is input to the 4th NAND gate, the output of the 4th NAND gate is defeated
Enter to the second NAND gate.
The option selection logic further comprises the first nor gate, the second nor gate, the first phase inverter, the second reverse phase
Device, third phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter, wherein the first nor gate, the first phase inverter, second
Phase inverter, third phase inverter serial connection, wherein the second nor gate, the 4th phase inverter, the 5th phase inverter, hex inverter are serial
Connection.Wherein the first OPTION signal is input to the first nor gate, wherein the first bonding welding pad signal is input to the first nor gate,
In the second OPTION signal be input to the second nor gate, wherein the second bonding welding pad signal is input to the second nor gate, wherein third
Phase inverter output is low-power consumption double data rate 2(LPDDR2) indicator that whether is activated of mode, wherein hex inverter is defeated
It is the indicator whether 16 input/output modes are activated out.
The bonding welding pad of another invention receives the first bonding welding pad signal, the second bonding welding pad signal, third
Bonding welding pad signal, wherein the first OPTION signal, the second OPTION signal and third OPTION signal are received by option selection logic,
Wherein option selects logic to select one of polynary storage configuration mode as the first bonding welding pad signal, the second bonding welding pad
Signal, third bond pad signal, first selection signal, second selection signal, the third selection signal, and the 4th selection letter
Number function.
The described option selection logic includes XOR gate, the first phase inverter, the second phase inverter, the first multiple selector, the
Two multiple selector, third multiple selector, the 4th multiple selector, the first NAND gate, the second NAND gate, third NAND gate,
4th NAND gate, third NAND gate, the 4th NAND gate, third phase inverter, the 4th phase inverter, the first nor gate, the 5th phase inverter,
Wherein first OPTION signal, second OPTION signal are input to XOR gate, wherein XOR gate, the first phase inverter, the second reverse phase
Device serial connection, wherein the second phase inverter, the first multiple selector, the second multiple selector, third multiple selector, more than the 4th
Road selector is in parallel, wherein the output of the first NAND gate is input to third NAND gate and the 4th NAND gate, wherein the second NAND gate
Output be input to third NAND gate and the 4th NAND gate, wherein the output of the first multiple selector and the second multiple selector connects
It connects and is input to third NAND gate, wherein third multiple selector connects with the output of the 4th multiple selector and is input to the 4th
NAND gate, wherein the output of third NAND gate is input to third phase inverter, and wherein third phase inverter output is low-power consumption Double Data
Rate 2(LPDDR2) the indicator that whether selects of storage configuration, the output of the 4th NAND gate is the input of the 4th phase inverter,
In the output of the 4th phase inverter be low power double data rate 3 (LPDDR3) the indicator that whether selects of storage configuration, wherein the
One nor gate and the is connected in series without phase inverter, wherein the output of the 5th phase inverter is whether 16 input/output modes select
Indicator, wherein the first bonding welding pad signal is input to the first nor gate, wherein the second bonding welding pad signal is input to more than first
Road selector and the second NAND gate, wherein third bond pad signal is input to the second NAND gate and third multiple selector,
In the first OPTION signal be input to the first nor gate, wherein the second OPTION signal is input to XOR gate, the first NAND gate, more than the 4th
Road selector, wherein third OPTION signal is input to XOR gate, the second multiple selector and the first NAND gate.
First multiple selector, the second multiple selector, third multiple selector, the 4th multiple selector are respectively wrapped
A PMOS transistor and a NMOS transistor in parallel are included, wherein the PMOS grid of the first multiple selector, the choosing of the second multichannel
The NMOS grid of device, the PMOS grid of third multistage road selector are selected, the NMOS grid of the 4th multiple selector link together, wherein the
The NMOS grid of one multiple selector, the PMOS grid of the second multiple selector, the NMOS grid multiple selector of third multiple selector
It links together with the PMOS grid of the 4th multiple selector.
Another embodiment of the invention provides option selection logic, bonding welding pad, for selecting polynary storage configuration mould
One of formula operates memory.
Polynary storage configuration mode includes low-power consumption double data rate 2(LPDDR2), low-power consumption double data rate 3
(LPDDR3) and low-power consumption double data rate 4(LPDDR4), wherein polynary storage configuration mode have 32 input/output moulds
Formula and 16 input/output modes.
Bonding welding pad the first bonding welding pad signal of reception, the second bonding welding pad signal, third bond pad signal, wherein the
One OPTION signal, the second OPTION signal and third OPTION signal are received by option selection logic, wherein the selection of option selection logic
One of polynary storage configuration mode is used as the first bonding welding pad signal, the second bonding welding pad signal, third bond pad letter
Number, first selection signal, second selection signal, the third selection signal, and the function of the 4th selection signal.
It includes XOR gate, the first phase inverter, the second phase inverter, the first multiple selector, the second multichannel that option, which selects logic,
Selector, third multiple selector, the 4th multiple selector, the first NAND gate, the second NAND gate, third NAND gate, the 4th with
NOT gate, third NAND gate, the 4th NAND gate, third phase inverter, the 4th phase inverter, the first nor gate, the 5th phase inverter, second or
NOT gate, hex inverter.
First OPTION signal, second OPTION signal are input to XOR gate, wherein XOR gate, the first phase inverter, second
Phase inverter serial connection, wherein the second phase inverter, the first multiple selector, the second multiple selector, third multiple selector, the
Four multiple selector are in parallel, wherein the output of the first NAND gate is input to third NAND gate and the 4th NAND gate, wherein second with
The output of NOT gate is input to third NAND gate and the 4th NAND gate, wherein the first multiple selector and the second multiple selector is defeated
It connects out and is input to third NAND gate, wherein third multiple selector is connected and is input to the output of the 4th multiple selector
4th NAND gate, wherein the output of third NAND gate is input to third phase inverter, and wherein the output of third phase inverter is that low-power consumption is double
Data rate 2(LPDDR2) the indicator that whether selects of storage configuration, the output of the 4th NAND gate is the defeated of the 4th phase inverter
Enter, wherein the indicator whether storage configuration that the output of the 4th phase inverter is low power double data rate 3 (LPDDR3) selects,
Wherein the first nor gate and the 5th phase inverter serial connection, wherein the 5th phase inverter output be 16 input/output modes whether
The indicator of selection, wherein the first bonding welding pad signal is input to the first nor gate, wherein the second bonding welding pad signal is input to
First multiple selector and the second NAND gate, wherein third bond pad signal is input to the second NAND gate and third multi-path choice
Device, wherein the first OPTION signal is input to the first nor gate, wherein the second OPTION signal be input to XOR gate, the first NAND gate,
4th multiple selector, wherein third OPTION signal is input to XOR gate, the second multiple selector and the first NAND gate.
First multiple selector, the second multiple selector, third multiple selector, the 4th multiple selector respectively include one
PMOS transistor and a NMOS transistor in parallel, wherein the PMOS grid of the first multiple selector, the second multiple selector
NMOS grid, the PMOS grid of third multistage road selector, the NMOS grid of the 4th multiple selector link together, wherein the first multichannel
The NMOS grid of selector, the PMOS grid of the second multiple selector, the NMOS grid multiple selector and the 4th of third multiple selector
The PMOS grid of multiple selector link together.
Specific structure first is that a kind of memory for supporting polynary storage configuration, comprising:
The option of polynary storage configuration mode, one of storage configuration for selecting multiple storage operations selects logic；
And mode register, test pattern register and bonding welding pad, wherein bonding welding pad is configurable, wherein bonding weldering
Disk is input into the input of option selection logic, and wherein test pattern register receives certain test modes register command；
Selected polynary storage configuration mode first is that configuration bonding welding pad and test pattern register command function, wherein
Polynary storage configuration mode includes low-power consumption double data rate 2(LPDDR2) and low-power consumption double data rate 3(LPDDR3), wherein
Polynary storage configuration mode has 32 input/output modes and 16 input/output modes；
Bonding welding pad the reception first bonding welding pad signal, the second bonding welding pad signal, third bond pad signal, wherein
First OPTION signal, the second OPTION signal and third OPTION signal are generated；
Wherein option selection logic selects one in polynary storage configuration mode, as the first bonding welding pad signal, the second key
Close pad signal, third bond pad signal, the first OPTION signal, the function of the second OPTION signal and third OPTION signal；
Wherein option selection logic includes latch, for generating the first, the second and third OPTION signal, the first nor gate, the
Two nor gates, the first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter,
Wherein the first nor gate, the first phase inverter, the second phase inverter, the serial connection of third phase inverter,
Wherein the second nor gate, the 4th phase inverter, the 5th phase inverter, hex inverter serial connection,
Wherein the first OPTION signal is input to the first nor gate,
Wherein the first bonding welding pad signal is input to the first nor gate,
Wherein the second OPTION signal is input into the second nor gate
Wherein the second bonding welding pad signal is input to the second nor gate,
Wherein the output of third phase inverter is the indicator whether LPDDR2 mode activates,
Wherein hex inverter output is the indicator whether 16 input/output modes are activated.
The structure of another feature is a kind of memory for supporting polynary storage configuration, including；Polynary storage configuration mode,
The option of one of storage configuration for selecting multiple storage operations selects logic；
Mode register, test pattern register and bonding welding pad, wherein bonding welding pad is configurable, and bonding welding pad is defeated
Enter the input to option selection logic, test pattern register receives certain test modes register command, selected polynary to deposit
Store up configuration mode first is that configuration pad and test pattern register command function, polynary storage configuration mode includes low function
Consume double data rate 2(LPDDR2), low-power consumption double data rate 3(LPDDR3), low-power consumption double data rate 4(LPDDR4),
Polynary storage configuration mode has 32 input/output modes and 16 input/output modes；
Bonding welding pad the reception first bonding welding pad signal, the second bonding welding pad signal, third bond pad signal, wherein
First OPTION signal, the second OPTION signal, third OPTION signal, the 4th OPTION signal are generated, wherein the choosing of option selection logic
One in polynary storage configuration mode is selected, as the first bonding welding pad signal, the second bonding welding pad signal, third bond pad
Signal, the first OPTION signal, the second OPTION signal, the function of third OPTION signal；
The described option selection logic includes an XOR gate, the first phase inverter, the second phase inverter, the first multiple selector, the
Two multiple selector, third multiple selector, the 4th multiple selector, the first NAND gate, the second NAND gate, third NAND gate,
4th NAND gate, third phase inverter, the 4th phase inverter, the first nor gate, the 5th phase inverter, first OPTION signal and
Two OPTION signals are input into XOR gate, the XOR gate, first phase inverter, second inverter series；
Wherein the second phase inverter, the first multiple selector, the second multiple selector, third multiple selector, the 4th multi-path choice
Device is in parallel,
Wherein the output of the first NAND gate is input into third NAND gate and the 4th NAND gate,
Wherein the output of the second NAND gate is input into third NAND gate and the 4th NAND gate,
Wherein the first multiple selector connects with the output of the second multiple selector and is input to third NAND gate,
Wherein third multiple selector connects with the output of the 4th multiple selector and is input to the 4th NAND gate,
Wherein the output of third NAND gate is input to third phase inverter,
Wherein the output of third phase inverter is the indicator whether LPDDR2 storage configuration mode selects,
Wherein the output of the 4th NAND gate is input to the 4th phase inverter,
Wherein the output of the 4th phase inverter is the indicator whether LPDDR3 storage configuration mode selects,
Wherein the first nor gate and the 5th inverter series,
Wherein the second nor gate and hex inverter are connected in series,
Wherein the output of the 5th phase inverter is the indicator whether 16 input/output modes are chosen
Wherein the first bonding welding pad signal is input to the first nor gate,
Wherein the second bonding welding pad signal is input to the first multiple selector and the second NAND gate,
Wherein third bond pad signal is input to the second NAND gate and third multiple selector,
Wherein the first OPTION signal is input to the first nor gate,
Wherein the second OPTION signal is input to XOR gate, the first NAND gate and the 4th multiple selector
Wherein third OPTION signal is input to the second multiple selector, XOR gate, the first NAND gate,
Wherein the first multiple selector, the second multiple selector, third multiple selector, the 4th multiple selector, each multichannel
Selector includes the PMOS transistor and NMOS transistor of parallel connection,
The wherein PMOS grid of the first multiple selector, the NMOS grid of the second multiple selector, the PMOS grid of third multiple selector,
The NMOS grid of 4th multiple selector link together,
The wherein NMOS grid of the first multiple selector, the PMOS grid of the second multiple selector, third multiple selector NMOS grid,
The PMOS grid of 4th multiple selector link together.
The embodiment of the present invention by adopting the above technical scheme, supports a variety of DDR SDRAM memories to configure in the same system
Mode, without selecting different products.
Above-mentioned general introduction is merely to illustrate that the purpose of book, it is not intended to be limited in any way.Except foregoing description
Schematical aspect, except embodiment and feature, by reference to attached drawing and the following detailed description, the present invention is further
Aspect, embodiment and feature, which will be, to be readily apparent that.
Detailed description of the invention
In conjunction with the detailed description of attached drawing and following example, in terms of above and other of the invention may be better understood.
Fig. 1 illustrates the embodiment that the present invention has the memory of storage sub-block.
Fig. 2 illustrates another embodiment that the present invention has the memory of storage sub-block.
Fig. 3 illustrates the data path of memory of the present invention.
Fig. 4-6 illustrates the embodiment of the selection logical option of selection storage configuration mode of the invention.
Fig. 7-10 illustrates another embodiment of the selection logical option of selection storage configuration mode of the invention.
Figure 11 illustrates a table, wherein listing the command pin of memory of the invention.
Figure 12 illustrates the clock signal of memory of the invention and the figure of command signal.
Specific embodiment
In the detailed description of following embodiment, the attached drawing in this document is referred to, these attached drawings, which illustrate, specifically may be used
With the embodiment of practice.
The invention discloses a kind of high capacity, high-performance, low-power consumption synchronous dram memory, can be using same outer
Compatible different specification in the case where portion port, compatible multiple interface specifications (such as polynary storage configuration or mode).Such as it is low
Power consumption double data rate 2(LPDDR2), low-power consumption double data rate 3(LPDDR3), order control, data path logic, Gao Xing
The storage core of energy is combined to be used in same reservoir.When operating reservoir, input and output (I/O) interface and voltage swing
Width can be with real-time selection.Storage core can there are many unique characteristics, to allow the storage of low-power consumption and high-throughput to access.
The present invention can also provide design for Measurability (DFT) characteristic, it is possible to reduce the testing time provides test flexibility, and ensures to produce
The reliability of product.
A kind of semiconductor memory, such as DRAM, including the region with multiple memory blocks.The region of these memory blocks can be with
Referred to as store core.One typical DRAM may include eight or more memory block, such as block 0, block 1 etc..Memory core
The heart is made of 8 or 8 or more memory blocks.Each piece may include bit line, wordline, storage unit, bit line detection amplifier,
Part and global row decoder, column decoder etc..Each memory block can respond the data read/write order to the memory block.
Fig. 1 illustrates the memory block diagram that the present invention has storage sub-block.Memory of the invention includes a command block
10, store core 12, DQ (input/output) 14, reading and writing data channel 22 and 24.Command block 10 is defeated with address comprising ordering
Enter.Storing core 12 includes 8 block storages: memory block 0,1,2,3,4,5,6,7.Each memory block is divided into top half and lower half
Part.0-7 memory block is arranged by 4x4 array.The top half of 0-7 memory block is arranged in the top half of 4x4 array, i.e. array
The 1st row and the 2nd row.The lower half portion of 0-7 memory block is arranged in the lower half portion of 4x4 array, i.e. the 3rd row and the 4th of array
Row.Reading and writing data channel channel 22 is routed between the 1st row of 4x4 array and the 2nd row, connects the upper half height of memory block 0-7
Block is to DQ block 14.Reading and writing data channel channel 24 is routed between the 3rd row of 4x4 array and the 4th row, is connected to memory block 0-7
Lower half sub-block to DQ block 14.
Fig. 2 illustrates another embodiment of the memory with storage sub-block of the invention.Core is stored in LPDDR4
In, there are four different region 41a-41d for storage core.Storage core 41a-41d can be divided into two groups, one group of storage core
41a and 41b, another group of storage core 41c and 41d.For every group of storage core, there are DQ block and an order and address block,
For reading data to every group of storage core write-in data or from every group of storage core.Especially DQ block 44a passes through reading and writing data
43a reading in channel channel writes data to memory core 41a;DQ block 44b writes data to storage core by reading and writing data channel 43b reading
Heart 41b;Order and address block 46a are for controling and operating DQ block 44a and 44b and storage core 41a and 41b.In addition, DQ block
44c writes data to storage core 41c by reading and writing data channel 43c reading;DQ block 44d reads and writes number by reading and writing data channel 43d
According to arrive memory core 41d;Order and address block 46b control and operate DQ block 44c and 44d, store core 41c and 41d.Such as figure
Shown, the present invention can extend to any number of storage core, DQ block and command block.The present embodiment is only based on this
The example of the various configurations of the memory of invention.
Fig. 3 illustrates the data path of memory of the invention.Command block 10 includes order and address block 160, row address
Selector 162, block control logic 164, column address counter and latch blocks 166, mode register 168, test pattern register
(TMRs) 170 and the second test pattern register (the 2nd TMRs) 172.Order and address about data can be input to life
It enables and address block 160.The address of data is transferred to storage core 12, passes through row address selector 162, block control logic 164
From the retrieval of storage core 12 or data are written with column address counter/latch 166.Row address selector 162, block control are patrolled
Volumes 164 and column address counter/latch 166 can be by activating one of memory block 0-8 read come storing data or therefrom
Access evidence, to be operated to storage core 12.
Once command block 10 has activated storage core 12, so that it may read data to DQ block 14 from storage core 12.Or
Read command or write order whether are received according to command block 10, determine to read data from DQ block 14 or writes data to storage core
The heart 12.Order and address block 160 can also be used to write order to mode register 168, TMRs 170 and the 2nd TMR 172.It surveys
Trying mode register can be identical as normal mode register, in addition to TMR is enabled with mode register 9(MR9).MR9 exists
It defines and discusses in the file JESD209-3C for the LPDDR3 specification that JEDEC is provided.MR9 can be made by predefined OP code
With so that TMRs becomes available.In each TMRs mode, operation code (OP) can be used, additional register is written,
Such as OP0 to OP7, to decode and enable more test patterns.
Fig. 4 illustrates a table, bonding welding pad configuration and mode register command is listed, for selecting of the invention deposit
The storage configuration mode of reservoir.Following storage configuration mode: LPDDR3, LPDDR2 can be used in memory of the invention.These
Storage configuration mode can read and write the data word of 32 or 16.Therefore, there is the combination of 4 kinds of different storage configuration modes.
By bond memory pad to setting voltage value, a kind of storage configuration mode of memory can be chosen.Bonding
The configuration of pad can distribute to the AD HOC of storage configuration.Here voltage Vdd is defined as logically high or logic 1, electricity
Pressure Vss is defined as logic low or logical zero.For example, by by pad XOPTP2 and pad XOPT16 be bonded to voltage Vss (or
Person or logical zero), the selection logical option (not shown) of memory will select the storage of the LPDDR3 of 32 I/O to match
Set mode.
Other bonding welding pads can be connected setting memory to the other different number of storage output and input
Device configuration.Bonding welding pad XOPTP2 and/or XOPT16 can be used for for the storage configuration mode of different memory setting defaults.
If necessary to different storage configuration modes, then mode register (MR) order or test pattern deposit can be used
The storage configuration mode of the order covering default of device.For example, in an embodiment of the present invention, LPDDR3 and 32 input/output
Configuration mode is the initial default configuration by connection setting.If memory application in LPDDR2 system, must be used
The storage configuration mode of LPDDR2 covers current storage configuration mode.One predefined MR order can be input to storage
Storage configuration mode is changed to LPDDR2 from LPDDR3 by device.
For example, a mode register command 155(MR155), it is also possible to a test pattern register command 27
(TMR27), default storage configuration mode, can be covered another storage by the operation code (OP [5], OP [4]) for changing the 5th, 4
Configuration mode.If the 4th of op code be in logic high state, LPDDR2 can by the option of memory select logic into
Row selection.If the 5th of op code, in logic high state, selects 16 bit input and output modes.
The quantity of storage configuration mode can change according to different reservoir designs.The embodiments described herein is not
Mean that present invention is limited only to these specific embodiments, and only illustrates basic conception of the invention.In addition, specific mode is posted
Storage order can cover default storage configuration mode and only act is arranged in be bonded relevant with particular memory configuration mode
Example, can also be modified according to the design of memory.Therefore, the present invention includes being covered by bonding line options and MR order
The various combinations of storage configuration pattern count amount and type.
Fig. 5 illustrates option selection logic 100a of the invention and is used to select storage configuration mode.Option selects logic
100a can have following input: op code OP_I<4:5>;Mode register command TOPTSEL;One reset command OPTM_RST_
B;The pad signal BP_OPTP2 issued from bonding welding pad XOPTP2;And the pad signal BP_ from bonding welding pad XOPT16
OPT16.Option selection logic 100a can export following signals OPTP2 and OPT16, select one kind further according to table shown in Fig. 4
Storage configuration mode.
Fig. 6 illustrates the block diagram of memory option selection logic of the invention.It includes phase inverter that option, which selects logic 100a,
101,102,114,116,118,130,132,134, NAND gate 104-110, nor gate 112,128.It can be by additional setting
Signal S is input to phase inverter 101, which can be used as reset latch.In this case, signal S can connect
Ground.The output of phase inverter 101 is input into NAND gate 108 and 106.
Signal OP_I<4:5>is input to NAND gate 104.Signal TOPTSEL is input into NAND gate 104 and 108.Order and
Reset signal CMDRST is input to phase inverter 102, identical as reset signal OPTM_RST_B.Phase inverter 102 is output to NAND gate
104 and 110.The output of NAND gate 104 is input into NAND gate 106 and 108.Another input of NAND gate 106 be connected to
The output of NOT gate 110.The output signal of NAND gate 110 is TOB.One input of NAND gate 110 is connected to the defeated of NAND gate 106
Out.The output of NAND gate 106 produces output signal TMOPT<0:1>.The output of NAND gate 108 is connected to the defeated of NAND gate 110
Enter end.
Here there are 2 latch 138, they are respectively designated as latch IOPTMR<0>, IOPTMR<1>.For letter
Single latch cicuit is shown only for the sake of list, in figure, but outputs the output of all latch IOPTMR<0:1>.Each lock
The corresponding output signal of storage IOPTMR<0:1>is TMOPT<0>, TMOPT<1>, is respectively applied on nor gate 112,128.
TOB node does not use in this circuit arrangement, but can retain to future and use, and is specifically dependent upon setting for different memory framework
Meter.
Nor gate 112 and phase inverter 114,116,118 are connected.Nor gate 128 and phase inverter 130,132,134 are serially to connect
It connects.Input signal TMOPT<0>, BP_OPTP2 are connected to the input terminal of nor gate 112.The output of phase inverter 118 generates output
Signal OPTP2.TMOPT<1>and BP_OPT16 signal are connected as input to the nor gate 128 of serial connection, phase inverter 134
Output generates signal OPT16.
Fig. 7-9 illustrates the list of bonding welding pad configuration and mode register command, for for the another of memory of the present invention
One embodiment selects storage configuration mode.The memory configuration mode that memory of the invention uses may include LPDDR4,
LPDDR3,LPDDR2.The reading for the data word that can be further 32 or 16 by these storage configuration mode settings is write
Enter mode.One in LPDDRn configuration may be selected in the pad of bonding, regardless of whether selection 16 or 32 I/O modes.It is any
Connection configuration can be covered by mode register command or test pattern register command, to reset LPDDRn configuration, selection
16 I/O configurations or 32 I/O configurations.
The bonding welding pad of memory receives following signals BP_OPTP2, BP_OPTP3, BP_OPT16.Initial selected deposits
Storage configuration mode can be selected based on the signal of bonding welding pad.For example, if BP_OPTP2=1 and BP_OPTP3=0,
Then select LPDDR2 storage configuration mode.If BP_OPTP2=0, BP_OPTP3=0 then selects LPDDR4 storage configuration mould
Formula.If BP_OPT16=0,32 bit patterns are selected according to connectivity option.If BP_OPT16=1, selected according to connection
Item 16 bit patterns of selection.
The test mode command (TM) for providing following input signal TM_OPTP2, TM_OPTP3 and TM_OPT16 can cover
Selected connectivity option.The input signal of the configuration and TM order that currently connect can be input in option selection logic, with
Export selection signal OPTP2, OPTP3, OPT16.Output selection signal can cover it is any before using memory bonding welding pad
The storage configuration mode of selection.
For example, selecting LPDDR4 storage configuration mode if output signal OPTP2=0 and OPTP3=0.If defeated
Signal OPTP2=0 out, OPTP3=1 then select LPDDR3 storage configuration mode.If the He of output signal OPTP2=1
OPTP3=0 then selects LPDDR2 storage configuration mode.If output signal OPT16=0,32 are selected according to connectivity option
I/O mode.If output signal OPT16=1,16 I/O modes are used.
The option for selecting storage configuration mode that Figure 10 illustrates another embodiment of the invention selects logic.Choosing
Selection logic 100b includes multiple selector 146-152, XOR gate 140, phase inverter 142,144, and 158,160,172, and it is non-
Door 154,156,162,164 and nor gate 170.Select options logic 100b according to input signal TM_OPTP2, TM_OPTP3,
BP_OPTP2, BP_OPTP3, BP_OPT16, TM_OPT16 provide output signal OPTP2, OPTP3 and OPT16.It is shown in Fig. 7
Table lists the input value and output valve of option selection logic 100b.One has the people of common skill that can provide it in this respect
His equivalent implementation generates output signal based on input signal shown in Fig. 7.It is one illustrative that option, which selects logic 100b,
Example is not intended in office where limit in formula.
Each multiple selector 146-152 includes NMOS and PMOS transistor in parallel.PMOS gate is marked by symbol GP
Know, NMOS gate is identified by symbol GN.If TM_OPTP2 or TM_OPTP3 are logically high, i.e., 1, each multiple selector will select certainly
Body (i.e. TM_OPTP2 and TM_OPTP3), but it is unable to simultaneous selection, simultaneous selection is defined as illegal operation.
Input signal TM_OPTP2 and TM_OPTP3 are input to XOR gate 140.The output of XOR gate 140, which is connected to, serially to be connected
The phase inverter 142 and 144 connect.Block 146-152 is in parallel with phase inverter 144.The input of block 146 is signal BP_OPTP2.Block 146
A signal is exported to NAND gate 154.The input signal of block 148 is TM_OPTP3.Block 148 exports a signal to NAND gate
154.The input signal of block 150 is BP_OPTP3.Block 150 exports a signal to NAND gate 156.152 pieces of input is signal
TM_OPTP2.Block 152 exports a signal to NAND gate 156.
Input signal TM_OPTP2 and TM_OPTP3 are input to NAND gate 162.The output of NAND gate 162 be input into it is non-
Door 154 and 156.Input signal BP_OPTP2 and BP_OPTP3 are input to NAND gate 164.The output of NAND gate 164 be input to
NOT gate 154 and 156.The input terminal for being output to phase inverter 158 of NAND gate 154 generates output signal OPTP2.NAND gate 156 is defeated
The input terminal of phase inverter 160 is arrived out, generates output signal OPTP3.
Input signal BP_OPT16 and TM_OPT16 are input to the nor gate 170 and phase inverter 172 of serial connection, generated
Output signal OPT16.
Figure 11 illustrates a table, lists the pin of the mode register read write command for this memory.Forms data
Rate (SDR) command pin CK_t (n-1), CK_t (n), CS_N, when double data rate (DDR) command pin CA0-CA9 is based on
Clock edge and the voltage value detected in these command pins, are assigned to specific mode register.
The voltage value detected in command pin can be stored in the mode register of memory, it controls memory
Various operation modes.For example, mode register can be used for rewriting (CAS) delay of column access gating, addressing mode, burst length
Degree, test pattern, delay phase-locked loop (DLL) reset and the particular options of various suppliers, so that DDR SDRAM can be used in
Various application programs.The default value of mode register may be defined.Therefore after the power-up, command pin can be used and write
Enter mode register to obtain suitable DDR SDRAM operation.
Completion usually requires two clock cycle to the write operation of mode register.In the process of running, as long as all deposit
Block is stored up all in idle state, so that it may use the content of identical order and clock cycle change mode register.Mode is posted
Storage is divided into different regions according to function.There are also the programmings that some modes allow antifuse, test redundant element, interim mould
It quasi- voltage and exchanges timing and adjusts etc..
Pass through the accessible specific test pattern of test pattern register.Mode register command collection is in clock signal CK
Rising edge deposit the position MA [7:0], then clock signal CK failing edge deposit the position OP [7:0].AD HOC register life
Order can be used for entering test pattern register command collection, to be written to test pattern register.The mode address (MA) of TMRs
Space only just can be used after entering test pattern by mode register command.Because test pattern has oneself unique mode
It is still available that address space, normal mode register write (MRW) and mode register read (MRR) mode.
Until all mode register settings can be maintained until remove.This allows the superposition of test pattern.Actually
There can be two scratchpad registers.First scratchpad register is generated by MA [7:0]+OP [7], i.e. TMR mode TMR.Second test
Register is combined to program by TMR+OP [7:0].Second programmable register can only pass through reset command CMD_RST reflex
Position, or individually TMR [n] mode resets specific test pattern.Exiting test pattern possibly can not remove the second deposit
Device.Once the address MRW will be extended to since MR128 into test pattern.Therefore, TMR [0]=MR [128], TMR [1]=
MR [129], and so on i.e. TMR [x]=MR.
After Figure 12 illustrates sending MRW order, the timing diagram of effective operation code is received.Timing diagram demonstrates the first He
The setting of second test pattern register.Note that TMR [x] signal is remained unchanged until relevant OP [7] are low.Switch TMR signal
Height be for latching the position OP [6:0], to program the second scratchpad register.OP_I [6:0] is generated by OP [6:0].Also
There is one to be limited in back-to-back sending MRW order (being not explicitly shown in time diagram), the clock periodicity between MRW order
It is 10 clock cycle.
Although the present invention is described some embodiments, it is to be appreciated that the invention is not limited to
These embodiments.On the contrary, the present invention is understood that and explains in its broadest sense, as claim is reflected.Cause
This, these claims are construed as not only including equipment described here, method and system, every other and into one
The change and modification of step will be apparent from for having the people of common skill in this respect.
Claims (14)
1. a kind of memory for supporting polynary storage configuration, it is characterized in that including:
Polynary storage configuration mode operates memory for selecting the option of one of multiple storage configurations to select logic；With
And bonding welding pad, wherein bonding welding pad is input into the input terminal of option selection logic.
2. the memory according to claim 1 for supporting polynary storage configuration, it is characterized in that the bonding welding pad is can
Configuration, the function of the bonding welding pad is selected one kind in the polynary storage configuration mode.
3. the memory according to claim 1 for supporting polynary storage configuration, it is characterized in that the memory is further
Including test pattern register, wherein test pattern register receives a certain test pattern register command, wherein selected is more
Function of one of the first storage configuration mode as the test pattern register command.
4. the memory according to claim 3 for supporting polynary storage configuration, it is characterized in that the memory, wherein certain
One test pattern register command is input to option selection logic, original to select as the function of test pattern register command
One of polynary storage configuration mode covered by one of another polynary storage configuration mode.
5. the memory according to claim 1 for supporting polynary storage configuration, it is characterized in that the polynary storage configuration
Mode includes low-power consumption double data rate 2(LPDDR2), low-power consumption double data rate 3(LPDDR3) and low-power consumption Double Data speed
Rate 4(LPDDR4), wherein polynary storage configuration mode has 32 input/output modes and 16 input/output modes.
6. the memory according to claim 1 for supporting polynary storage configuration, it is characterized in that the bonding welding pad receives
First bonding welding pad signal, the second bonding welding pad signal, wherein the first OPTION signal, the second OPTION signal are generated, wherein selecting
Item select logic select one of polynary storage configuration mode as the first bonding welding pad signal, the second bonding welding pad signal,
The function of first OPTION signal, the second OPTION signal.
7. the memory according to claim 6 for supporting polynary storage configuration, it is characterized in that the memory option selects
Selecting logic further comprises multiple latch to generate the first OPTION signal, the second OPTION signal,
Wherein each latch includes the first phase inverter, the second phase inverter, the first NAND gate, the second NAND gate, third NAND gate
With the 4th NAND gate, wherein each latch the second NAND gate generate OPTION signal.
8. the memory according to claim 7 for supporting polynary storage configuration, it is characterized in that each latch the
The output of one phase inverter is input into the second NAND gate and third NAND gate, the output of the second phase inverter be input into first with it is non-
Door and the 4th NAND gate, the operation code for carrying out self-testing mode register command are input into the first NAND gate, and test pattern is posted
Storage order is input to the first NAND gate and third NAND gate, and order reset signal is input to the second phase inverter, the first NAND gate
Output be input into the second NAND gate and third NAND gate, the output of third NAND gate is input to the 4th NAND gate, wherein
The output of two NAND gates is input to the 4th NAND gate, and the output of the 4th NAND gate is input into the second NAND gate.
9. the memory according to claim 7 for supporting polynary storage configuration, it is characterized in that the option selects logic
Further comprise the first nor gate, the second nor gate, the first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter,
5th phase inverter, hex inverter, wherein the first nor gate, the first phase inverter, the second phase inverter, third phase inverter serially connect
It connects, wherein the second nor gate, the 4th phase inverter, the 5th phase inverter, hex inverter serial connection, wherein the first OPTION signal is defeated
Enter to the first nor gate, wherein the first bonding welding pad signal is input to the first nor gate, wherein the second OPTION signal is input to
Two nor gates, wherein the second bonding welding pad signal is input to the second nor gate, wherein third phase inverter output is low-power consumption even numbers
According to the indicator whether rate 2(LPDDR2) mode is activated, wherein hex inverter output is that 16 input/output modes are
The no indicator being activated.
10. the memory according to claim 1 for supporting polynary storage configuration, it is characterized in that the bonding welding pad receives
First bonding welding pad signal, the second bonding welding pad signal, third bond pad signal, wherein the first OPTION signal, the second option
Signal and third OPTION signal are received by option selection logic, and wherein option selection logic selects in polynary storage configuration mode
A kind of the first bonding welding pad signal of conduct, the second bonding welding pad signal, third bond pad signal, first selection signal, second
The function of selection signal and third selection signal.
11. the memory according to claim 10 for supporting polynary storage configuration, it is characterized in that the option selection is patrolled
Collect includes XOR gate, the first phase inverter, the second phase inverter, the first multiple selector, the second multiple selector, third multi-path choice
Device, the 4th multiple selector, the first NAND gate, the second NAND gate, third NAND gate, the 4th NAND gate, third NAND gate, the 4th
NAND gate, third phase inverter, the 4th phase inverter, the first nor gate, the 5th phase inverter, wherein first OPTION signal, second
OPTION signal is input to XOR gate, wherein XOR gate, the first phase inverter, the serial connection of the second phase inverter, wherein the second phase inverter,
First multiple selector, the second multiple selector, third multiple selector, the 4th multiple selector are in parallel, wherein first with it is non-
Door output be input to third NAND gate and the 4th NAND gate, wherein the output of the second NAND gate be input to third NAND gate and
4th NAND gate, wherein the first multiple selector connects with the output of the second multiple selector and is input to third NAND gate,
Middle third multiple selector connects with the output of the 4th multiple selector and is input to the 4th NAND gate, wherein third NAND gate
Be input to third phase inverter, wherein third phase inverter output is low-power consumption double data rate 2(LPDDR2) storage configuration
The output of the indicator whether selected, the 4th NAND gate is the input of the 4th phase inverter, wherein the output of the 4th phase inverter is low function
The indicator whether storage configuration of rate double data rate 3 (LPDDR3) selects, wherein the first nor gate and the 5th phase inverter string
Row connection, wherein the output of the 5th phase inverter is the indicator whether 16 input/output modes select, wherein the first bonding welding pad
Signal is input to the first nor gate, wherein the second bonding welding pad signal is input to the first multiple selector and the second NAND gate,
Middle third bond pad signal is input to the second NAND gate and third multiple selector, wherein the first OPTION signal is input to first
Nor gate, wherein the second OPTION signal is input to XOR gate, the first NAND gate, the 4th multiple selector, wherein third option is believed
Number it is input to XOR gate, the second multiple selector and the first NAND gate.
12. the memory according to claim 11 for supporting polynary storage configuration, it is characterized in that first multichannel is selected
Select device, the second multiple selector, third multiple selector, the 4th multiple selector respectively include a PMOS transistor and one simultaneously
The NMOS transistor of connection, wherein the PMOS grid of the first multiple selector, the NMOS grid of the second multiple selector, the choosing of third multistage road
The PMOS grid of device are selected, the NMOS grid of the 4th multiple selector link together, wherein the NMOS grid of the first multiple selector, second
The PMOS grid of multiple selector, the NMOS grid multiple selector of third multiple selector and the PMOS grid of the 4th multiple selector connect
It is connected together.
13. a kind of memory for supporting polynary storage configuration, comprising:
The option of polynary storage configuration mode, one of storage configuration for selecting multiple storage operations selects logic；
And mode register, test pattern register and bonding welding pad, wherein bonding welding pad is configurable, wherein bonding weldering
Disk is input into the input of option selection logic, and wherein test pattern register receives certain test modes register command；
Selected polynary storage configuration mode first is that configuration bonding welding pad and test pattern register command function, wherein
Polynary storage configuration mode includes low-power consumption double data rate 2(LPDDR2) and low-power consumption double data rate 3(LPDDR3),
Wherein polynary storage configuration mode has 32 input/output modes and 16 input/output modes；The bonding weldering
Disk receives the first bonding welding pad signal, the second bonding welding pad signal, third bond pad signal, wherein the first OPTION signal, the
Two OPTION signals and third OPTION signal are generated；
Wherein option selection logic selects one in polynary storage configuration mode, as the first bonding welding pad signal, the second key
Close pad signal, third bond pad signal, the first OPTION signal, the function of the second OPTION signal and third OPTION signal；
Wherein option selection logic includes latch, for generating the first, the second and third OPTION signal, the first nor gate, the
Two nor gates, the first phase inverter, the second phase inverter, third phase inverter, the 4th phase inverter, the 5th phase inverter, hex inverter,
Wherein the first nor gate, the first phase inverter, the second phase inverter, the serial connection of third phase inverter,
Wherein the second nor gate, the 4th phase inverter, the 5th phase inverter, hex inverter serial connection,
Wherein the first OPTION signal is input to the first nor gate,
Wherein the first bonding welding pad signal is input to the first nor gate,
Wherein the second OPTION signal is input into the second nor gate
Wherein the second bonding welding pad signal is input to the second nor gate,
Wherein the output of third phase inverter is the indicator whether LPDDR2 mode activates,
Wherein hex inverter output is the indicator whether 16 input/output modes are activated.
14. a kind of memory for supporting polynary storage configuration, including；Polynary storage configuration mode, for selecting multiple memories
The option of one of the storage configuration of operation selects logic；
Mode register, test pattern register and bonding welding pad, wherein bonding welding pad is configurable, and bonding welding pad is defeated
Enter the input to option selection logic, test pattern register receives certain test modes register command, selected polynary to deposit
Store up configuration mode first is that configuration pad and test pattern register command function, polynary storage configuration mode includes low function
Consume double data rate 2(LPDDR2), low-power consumption double data rate 3(LPDDR3), low-power consumption double data rate 4(LPDDR4),
Polynary storage configuration mode has 32 input/output modes and 16 input/output modes；
Bonding welding pad the reception first bonding welding pad signal, the second bonding welding pad signal, third bond pad signal, wherein
First OPTION signal, the second OPTION signal, third OPTION signal, the 4th OPTION signal are generated, wherein the choosing of option selection logic
One in polynary storage configuration mode is selected, as the first bonding welding pad signal, the second bonding welding pad signal, third bond pad
Signal, the first OPTION signal, the second OPTION signal, the function of third OPTION signal；
The described option selection logic includes an XOR gate, the first phase inverter, the second phase inverter, the first multiple selector, the
Two multiple selector, third multiple selector, the 4th multiple selector, the first NAND gate, the second NAND gate, third NAND gate,
4th NAND gate, third phase inverter, the 4th phase inverter, the first nor gate, the 5th phase inverter, first OPTION signal and
Two OPTION signals are input into XOR gate, the XOR gate, first phase inverter, second inverter series；
Wherein the second phase inverter, the first multiple selector, the second multiple selector, third multiple selector, the 4th multi-path choice
Device is in parallel,
Wherein the output of the first NAND gate is input into third NAND gate and the 4th NAND gate,
Wherein the output of the second NAND gate is input into third NAND gate and the 4th NAND gate,
Wherein the first multiple selector connects with the output of the second multiple selector and is input to third NAND gate,
Wherein third multiple selector connects with the output of the 4th multiple selector and is input to the 4th NAND gate,
Wherein the output of third NAND gate is input to third phase inverter,
Wherein the output of third phase inverter is the indicator whether LPDDR2 storage configuration mode selects,
Wherein the output of the 4th NAND gate is input to the 4th phase inverter,
Wherein the output of the 4th phase inverter is the indicator whether LPDDR3 storage configuration mode selects,
Wherein the first nor gate and the 5th inverter series,
Wherein the output of the 5th phase inverter is the indicator whether 16 input/output modes are chosen
Wherein the first bonding welding pad signal is input to the first nor gate,
Wherein the second bonding welding pad signal is input to the first multiple selector and the second NAND gate,
Wherein third bond pad signal is input to the second NAND gate and third multiple selector,
Wherein the first OPTION signal is input to the first nor gate,
Wherein the second OPTION signal is input to XOR gate, the first NAND gate and the 4th multiple selector
Wherein third OPTION signal is input to the second multiple selector, XOR gate, the first NAND gate,
Wherein the first multiple selector, the second multiple selector, third multiple selector, the 4th multiple selector, each multichannel
Selector includes the PMOS transistor and NMOS transistor of parallel connection,
The wherein PMOS grid of the first multiple selector, the NMOS grid of the second multiple selector, the PMOS grid of third multiple selector,
The NMOS grid of 4th multiple selector link together,
The wherein NMOS grid of the first multiple selector, the PMOS grid of the second multiple selector, third multiple selector NMOS grid,
The PMOS grid of 4th multiple selector link together.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910275320.0A CN110164488A (en) | 2019-04-08 | 2019-04-08 | A kind of memory for supporting polynary storage configuration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910275320.0A CN110164488A (en) | 2019-04-08 | 2019-04-08 | A kind of memory for supporting polynary storage configuration |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110164488A true CN110164488A (en) | 2019-08-23 |
Family
ID=67639319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910275320.0A Pending CN110164488A (en) | 2019-04-08 | 2019-04-08 | A kind of memory for supporting polynary storage configuration |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110164488A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102540057A (en) * | 2010-11-17 | 2012-07-04 | 海力士半导体有限公司 | Test mode control circuit of semiconductor apparatus and control method thereof |
| CN103824580A (en) * | 2012-11-19 | 2014-05-28 | 三星电子株式会社 | Logic devices, digital filters including logic devices, and methods of controlling logic devices |
| CN103891146A (en) * | 2012-03-08 | 2014-06-25 | 罗德施瓦兹两合股份有限公司 | Semiconductor circuit with electrical connections having multiple signal or potential assignments |
| US20140321200A1 (en) * | 2013-04-25 | 2014-10-30 | Being Advanced Memory Corporation | Phase change memory with flexible time-based cell decoding |
| US9183892B2 (en) * | 2007-12-20 | 2015-11-10 | Conversant Intellectual Property Management Inc. | Data storage and stackable chip configurations |
| US20170062039A1 (en) * | 2015-08-26 | 2017-03-02 | eveRAM Technology America, Inc. | Memory device that supports multiple memory configurations |
| CN107799135A (en) * | 2016-08-31 | 2018-03-13 | 爱思开海力士有限公司 | Semiconductor system |
-
2019
- 2019-04-08 CN CN201910275320.0A patent/CN110164488A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9183892B2 (en) * | 2007-12-20 | 2015-11-10 | Conversant Intellectual Property Management Inc. | Data storage and stackable chip configurations |
| CN102540057A (en) * | 2010-11-17 | 2012-07-04 | 海力士半导体有限公司 | Test mode control circuit of semiconductor apparatus and control method thereof |
| CN103891146A (en) * | 2012-03-08 | 2014-06-25 | 罗德施瓦兹两合股份有限公司 | Semiconductor circuit with electrical connections having multiple signal or potential assignments |
| CN103824580A (en) * | 2012-11-19 | 2014-05-28 | 三星电子株式会社 | Logic devices, digital filters including logic devices, and methods of controlling logic devices |
| US20140321200A1 (en) * | 2013-04-25 | 2014-10-30 | Being Advanced Memory Corporation | Phase change memory with flexible time-based cell decoding |
| US20170062039A1 (en) * | 2015-08-26 | 2017-03-02 | eveRAM Technology America, Inc. | Memory device that supports multiple memory configurations |
| CN107799135A (en) * | 2016-08-31 | 2018-03-13 | 爱思开海力士有限公司 | Semiconductor system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7990746B2 (en) | Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies | |
| US9805781B2 (en) | Semiconductor memory device | |
| US6320812B1 (en) | Error catch RAM for memory tester has SDRAM memory sets configurable for size and speed | |
| US6851076B1 (en) | Memory tester has memory sets configurable for use as error catch RAM, Tag RAM's, buffer memories and stimulus log RAM | |
| US8437209B2 (en) | Integrated circuit | |
| CN101025996A (en) | Multi-port semiconductor memory device and signal input/output method therefor | |
| US10984886B2 (en) | Reduced footprint fuse circuit | |
| CN1627521B (en) | Semiconductor integrated circuit device | |
| CN104143355A (en) | Dynamic random access memory refreshing method and apparatus thereof | |
| JP2000149600A (en) | Semiconductor storage device | |
| US11494319B1 (en) | Apparatuses, systems, and methods for input/output mappings | |
| JP4187084B2 (en) | Semiconductor memory | |
| US7835204B2 (en) | Semiconductor memory device for generating column address | |
| JPS60150285A (en) | Integrated circuit memory | |
| US20090003117A1 (en) | Semiconductor memory device | |
| CN110164488A (en) | A kind of memory for supporting polynary storage configuration | |
| US7308622B2 (en) | Integrated memory and method for testing the memory | |
| US11404104B2 (en) | Semiconductor memory device capable of operating at high speed, low power environment by optimizing latency of read command and write command depending on various operation modes | |
| KR100884587B1 (en) | Multi port memory device | |
| US7447107B2 (en) | Random access memory including multiple state machines | |
| US7930465B2 (en) | Determining operation mode for semiconductor memory device | |
| US20080025128A1 (en) | Memory system | |
| CN100422908C (en) | Memory device having high bus efficiency of network, operating method of the same, and memory system including the same | |
| JP2000331498A (en) | Semiconductor memory | |
| JP2010003388A (en) | Semiconductor memory device and its test method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190823 |
|
| RJ01 | Rejection of invention patent application after publication |