CN110137198B - Color polarization CMOS image sensor and manufacturing method thereof - Google Patents

Color polarization CMOS image sensor and manufacturing method thereof Download PDF

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CN110137198B
CN110137198B CN201910466139.8A CN201910466139A CN110137198B CN 110137198 B CN110137198 B CN 110137198B CN 201910466139 A CN201910466139 A CN 201910466139A CN 110137198 B CN110137198 B CN 110137198B
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layer
photodiode
nanowire
photoelectron
polarization filter
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CN110137198A (en
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金尚忠
吴羽峰
唐莹
严永强
方维
袁骁霖
黄河
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China Jiliang University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14645—Colour imagers
    • H01L27/14647—Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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Abstract

The invention discloses a color polarization CMOS image sensor and a manufacturing method thereof, and the method specifically comprises the following steps: the nano-wire polarization filter comprises a p + substrate (01), a p + layer 1 (02), n + (03), an n + layer 1 (04), a p + layer 2 (05), an n + layer 2 (06), a p + layer 3 (07), an n + layer 3 (08), a photoelectron drift layer (09), a color information output circuit (10) and four nano-wire polarization filters. The sensor comprises 1300 x 800 pixels, each pixel comprising 3 vertically stacked photodiodes and one photoelectron drift layer (09), each diode being formed by alternating doping of p + and n +. The metal nanowires are deposited after the CMOS, thereby increasing the polarization sensitivity of the sensor. Due to different expected penetration depths of different wavelengths, PN junctions with different depths in the same pixel can show different absorption spectra, and therefore spectral response of 200 nm-1000 nm is achieved. The sensor has the advantages of large dynamic range, high signal-to-noise ratio, low power consumption and the like, and has great application value in practical application.

Description

Color polarization CMOS image sensor and manufacturing method thereof
Technical Field
The invention relates to the technical field of image sensors, in particular to a color polarization CMOS image sensor and a manufacturing method thereof.
Background
In recent decades, with the progress of semiconductor technology, CMOS image sensor technology has become mature, but high fill factor and high dynamic range CMOS image sensor are still needed for high quality image capture. A novel stacked CMOS image sensor is developed. The stacked CMOS image sensor has a smaller chip structure and a faster processing speed, relative to the conventional CMOS image sensor.
In the conventional art, the CMOS image sensor has the following disadvantages: 1) The CMOS image sensor has a small dynamic range, and cannot effectively filter or apply ultraviolet information; 2) The output dynamic range of the pixel unit of the traditional CMOS image sensor is not high, and multiple exposures are needed when a high dynamic range image is shot, so that the shooting time and the burden of an image processing circuit are increased; 3) The traditional CMOS image sensor does not add a device sensitive to polarized light, so that some important polarized light information cannot be captured by the image sensor.
Disclosure of Invention
The present invention is directed to overcome the above-mentioned drawbacks and deficiencies of the prior art and to provide a color polarization CMOS image sensor and a method for fabricating the same.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a color polarization CMOS image sensor and a manufacturing method thereof, comprising:
the light-emitting diode comprises a P + substrate (01), a P + layer 1 (02), an n + layer (03), an n + layer 1 (04), a P + layer 2 (05), an n + layer 2 (06), a P + layer 3 (07), an n + layer 3 (08), a photo-generated electron drift layer (09), a color information output circuit (10), a 0-degree nanowire polarization filter (11), a 45-degree nanowire polarization filter (12), a 90-degree nanowire polarization filter (13) and a 135-degree nanowire polarization filter (14).
The CMOS image sensor comprises 1300 x 800 pixels, and each pixel comprises 3 vertically stacked photodiodes and a photoelectron drift layer (09). Thereby realizing the spectral response of 200 nm-1000 nm.
The p + substrate (01) is a positively doped silicon wafer, which serves as a substrate on which a custom wafer having four epitaxial layers is custom fabricated.
The P + layer 1 (02) and the n + layer 1 (04) are first epitaxial layers and are about 1.5 microns thick. P + and n + are doped positively and negatively to form a red photodiode for absorbing red information in incident light.
The p + layer 2 (05) and the n + layer 2 (06) are second epitaxial layers and have the thickness of about 2 mu m. The P + and n + doping forms a green photodiode for absorbing green information in incident light.
The p + layer 3 (07) and the n + layer 3 (08) are third epitaxial layers and have the thickness of about 0.8 μm. P + and n + are doped positively and negatively to form a blue photodiode for absorbing blue information in incident light.
The n + layer (03) realizes negative doping, so that a negative doping isolation region is formed, and electron hole pairs generated by photons in one pixel are prevented from being diffused to adjacent pixels.
The photoelectron drift layer (09) has a steep doping profile, so that the sensitivity to ultraviolet light and the robustness of the sensitivity are improved. For absorbing ultraviolet information in incident light.
The color information output circuit (10) is used for simultaneously accessing information in three photodiodes and a photoelectron drift layer (09) in a line parallel mode.
Each photodiode and the photogenerated electron drift layer (09) are provided with three transistors to reduce the pixel pitch of the CMOS image sensor. Wherein the gates of the access transistor and the reset transistor are connected separately to reduce the number of metal lines used within each pixel.
The 0-degree nanowire polarization filter (11), the 45-degree nanowire polarization filter (12), the 90-degree nanowire polarization filter (13) and the 135-degree nanowire polarization filter (14) are deposited on each pixel by adopting interference lithography and reactive ion etching technologies, the metal nanowires are 75nm in width and 250nm in height, and the working period is 50%. Therefore, each pixel is sensitive to the polarized light, and the robustness of the polarized light sensitivity of the CMOS image sensor is enhanced.
The manufacturing method of the color polarization CMOS image sensor comprises the following steps of, wherein the manufacturing of the metal nanowire polarization filter can be divided into two types, namely a manufacturing method of a metal aluminum nanowire and a manufacturing method of a metal copper nanowire:
A1. fabrication of nanowire polarizing filters:
1. a 250nm thick layer of aluminum was deposited on the substrate by electron beam deposition.
2. Deposition of 75nm thick SiO on top of the aluminum layer by chemical vapor deposition 2 And (3) a layer. This layer will serve as a hard mask for etching the underlying aluminum.
3. A140 nm thick layer of S-1805 photoresist was applied at 3000 rpm.
4. The samples were baked at 120 ℃ for 90 seconds and then cooled at 70 ℃ for 30 seconds to avoid cracking in the photoresist.
5. The quartz mask was brought into contact with the sample. The mask is composed of a layer of chrome to block light except for selected pixels where chrome is removed. Each even pixel in each even row has chromium removed and will be exposed to the interference pattern.
6. An interference pattern was generated using a 532nm continuous wave neodymium-doped yttrium aluminum garnet (Nd: YAQ) laser coupled with a frequency multiplier. The two laser beams are aligned to intersect at 110 ° and produce a 140nm periodic interference pattern on the surface of the exposed photoresist. The photoresist was exposed for 40 seconds.
7. The direction of application of the adhesive is in contact with the substrate. Both the mask and the substrate are rotated 45 deg. with respect to the interference pattern. The photoresist was exposed for 40 seconds.
8. Step 7 was repeated twice, yielding 90 ° and 135 ° pixelated nanowire filters. .
9. After four consecutive exposures, the photoresist was developed for 60 seconds while the sample was stirred.
10. Inductively coupled plasma reactive ion etching (ICP RIE) for etching SiO 2 . At the end of this step, the 75nm nanowire pattern was transferred from the photoresist to the underlying SiO 2 And (3) a layer.
11. The aluminum layer was next etched using a standard ICP RIE recipe. SiO 2 2 The layer acts as a hard mask for etching aluminum and enables the formation of deep trenches, i.e., aluminum nanowires 250nm high and 75nm wide. (high aspect ratio aluminum structures cannot be obtained using photoresist because the photoresist has a higher etch rate than aluminum, and thus it is not possible to form a photoresist structure having an aspect ratio of 100 or higher.)
A2. Fabrication of metallic copper nanowire polarizing filters
1. Deposition of 75nm thick SiO on top of the substrate by chemical vapor deposition 2 And (3) a layer. This layer will serve as a hard mask for etching the electroplated copper.
2. A140 nm thick layer of S-1805 photoresist was applied at 3000 rpm.
3. The samples were baked at 120 ℃ for 90 seconds and then cooled at 70 ℃ for 30 seconds to avoid cracking in the photoresist.
4. The quartz mask was brought into contact with the sample. The mask is composed of a layer of chrome to block light except for selected pixels where the chrome is removed. Each even pixel in each even row has chromium removed and will be exposed to the interference pattern.
5. An interference pattern was generated using a 532nm continuous wave neodymium-doped yttrium aluminum garnet (Nd: YAQ) laser coupled with a frequency multiplier. The two laser beams are aligned to intersect at 110 ° and produce a 140nm periodic interference pattern on the surface of the exposed photoresist. The photoresist was exposed for 40 seconds.
6. The direction of application of the adhesive is in contact with the substrate. Both the mask and the substrate are rotated 45 deg. with respect to the interference pattern. The photoresist was exposed for 40 seconds.
7. Step 6 was repeated twice, yielding 90 ° and 135 ° pixelated nanowire filters.
8. After four consecutive exposures, the photoresist was developed for 60 seconds while the sample was stirred.
9. Inductively coupled plasma reactive ion etching (ICP RIE) for etching SiO 2 . At the end of this step, the 75nm nanowire pattern was transferred from the photoresist to the underlying SiO 2 And (3) a layer.
10. In the formation of SiO 2 On the pattern, a 350nm thick copper layer was deposited by electroplating.
11. The excess copper layer was removed by CMP, finally leaving a 250nm thick copper layer.
B. CMOS imagers with vertically stacked photodiodes:
the imaging sensor is fabricated using a 180nm feature process. The substrate used to fabricate the sensor is a custom wafer with four epitaxial layers. The imager is on a positively doped silicon wafer (10 per cubic centimeter) 15 One boron atom). The first epitaxial layer is grown on top of the silicon wafer to a thickness of about 1.5 μm. The epitaxial layer is positively doped with-10 per cubic centimeter 16 And (3) boron atoms. Next, the negative terminal of the red photodiode is doped by-10 per cubic centimeter of the selected area of the epitaxial layer at 75keV energy 17 Phosphorus atoms and then rapid thermal annealingTo achieve the same. A negatively doped isolation region between adjacent pixels is next created to prevent lateral flow of photo-induced electron-hole pairs. The isolation region is formed by using three different doping concentrations at three different energy levels. The first doping is 1500keV and contains 10 per cubic centimeter 18 Phosphorus atoms of 1000keV for the second time, containing-0.5X 10 per cubic centimeter 18 Phosphorus atoms, the third doping is 750keV and contains 10 per cubic centimeter 17 And a phosphorus atom. Followed by rapid thermal annealing. The impedance of the isolation region is not important as it is only used to eliminate optical cross-talk between adjacent pixels.
Second positively doped epitaxial layer (10 per cubic centimeter) 16 Boron atoms) are grown on top of the first epitaxial layer to a thickness of-2 μm. The next step is to form: the negative terminal of the green photodiode, (2) connected to the negative terminal of the red photodiode, and (3) connected to the negatively doped isolation region between the pixels. The latter two connections are first achieved by using three different doping concentrations at three different energy levels. The first doping is 1500keV and contains 10 per cubic centimeter 18 Phosphorus atoms of 1000keV for the second time, containing-0.5X 10 per cubic centimeter 18 Phosphorus atoms, the third doping is 750keV and contains 10 per cubic centimeter 17 And a phosphorus atom. The final doping step is to form a film having-10 per cubic centimeter at 75keV energy 17 The negative terminal of the green photodiode for each phosphorus atom is then subjected to rapid thermal annealing.
Third positively doped epitaxial layer (10 per cubic centimeter) 16 Boron atoms) are grown on top of the second epitaxial layer to a thickness of-0.8 μm. The next step is to form: (1) the negative terminal of the blue photodiode, (2) to the negative terminals of the green and red photodiodes, (3) to the negatively doped isolation region between the pixels. The latter two connections are first achieved by using two different doping concentrations at three different energy levels. The first doping is 1500keV and contains 10 per cubic centimeter 18 Phosphorus atoms of 1000keV for the second time, containing-0.5X 10 per cubic centimeter 18 Phosphorus atoms, the third doping is 750keV, each cubic centimeter contains-10 17 Phosphorus atomAnd (4) adding the active ingredients. The last step is to form a dielectric layer having a thickness of-10 per cubic centimeter at an energy of 75keV 17 The negative terminal of the blue photodiode, which is a phosphorus atom, is then subjected to rapid thermal annealing.
And the fourth photogenerated electron drift layer is arranged on the top of the third epitaxial layer. The method comprises the following steps: the buried n-layer structure includes (1) an upper neutral region, (2) a middle p + layer, and (3) a buried n-layer. The neutral region is distributed at the surface and has a sufficiently high dopant concentration. The p + layer has a uniform thin and steep doping profile and thus creates an electric field to drift photo-generated electrons to the buried n layer. There is a low concentration junction between the p + layer and the buried n layer. The purpose is to reduce the electric field at the pn junction to suppress dark current. In addition, the junction depth (x) is designed j =80 nm) and dopant concentration such that when the buried n-layer is fully depleted, the depletion layer does not reach the incident light side surface.
The positive terminals of all the photodiodes are connected to ground potential. The negative terminal of each photodiode is connected to each readout circuit in the pixel.
The color information output circuit (10) comprises four readout circuits, each readout circuit comprising three transistors: a reset transistor, a source follower and an access transistor. The reset transistor controls the integration (or exposure) time of the photodiode such that photon-generated electron-hole pairs are integrated on the photodiode intrinsic capacitance when the gate voltage is low. The source follower buffers the integrated photodiode voltage before outputting it onto the column bus. The access transistor controls access to the readout bus so that all pixels in a row share the same readout bus. The gates of the reset and access transistors for the red, green and blue photodiodes are connected together; thus, all three photodiodes have the same exposure control and can be accessed in parallel at the same time. This minimizes the number of metal lines per pixel and the pixel pitch.
Drawings
Fig. 1 is a cross-sectional view of a pixel circuit of a color polarized CMOS image sensor and a method of fabricating the same and a vertically stacked photodiode thereof.
Fig. 2 is a top view of a color polarization CMOS image sensor and a method for fabricating the same.
The reference numbers indicate:
01-p + substrate;
02 — P + layer 1;
03-n + layer;
04-n + layer 1;
05-p + layer 2;
06-n + layer 2;
07-p + layer 3;
08-n + layer 3;
09-a photogenerated electron drift layer;
10-color information output circuit;
11-0 degree nanowire polarization filter;
12-45 degree nanowire polarization filters;
13-90 degree nanowire polarization filters;
14-135 degree nano linear polarization filter.
Detailed Description
In order to explain the concrete flow of the present invention, the following detailed description is made with reference to the accompanying drawings.
Referring to fig. 1, a color polarization CMOS image sensor and a method of fabricating the same. The color polarization CMOS image sensor of the invention comprises: 01-P + substrate, 02-P + layer 1, 03-n + layer, 04-n + layer 1, 05-P + layer 2, 06-n + layer 2, 07-P + layer 3, 08-n + layer 3, 09-photogenerated electronic drift layer, 10-color information output circuit, 11-0 degree nanowire polarization filter, 12-45 degree nanowire polarization filter, 13-90 degree nanowire polarization filter, 14-135 degree nanowire polarization filter.
The CMOS image sensor comprises 1300 x 800 pixels, and each pixel comprises 3 vertical stacked photodiodes and a photoelectron drift layer (09). Thereby realizing the spectral response of 200 nm-1000 nm.
The p + substrate (01) is a positively doped silicon wafer, which serves as a substrate on which a custom wafer having four epitaxial layers is custom fabricated.
The n + layer (03) realizes negative doping, so that a negative doping isolation region is formed, and electron hole pairs generated by photons in one pixel are prevented from being diffused to adjacent pixels.
The P + layer 1 (02) and the n + layer 1 (04) are first epitaxial layers and are about 1.5 microns thick. P + and n + are doped positively and negatively to form a red photodiode for absorbing red information in incident light. The epitaxial layer is positively doped with-10 per cubic centimeter 16 And (3) boron atoms. Next, the negative terminal of the red photodiode is doped to 10 per cubic centimeter of the selected area of the epitaxial layer at 75keV energy 17 And then rapidly thermally annealed. A negatively doped isolation region between adjacent pixels is next created to prevent lateral flow of photo-induced electron-hole pairs. The isolation region is formed by using three different doping concentrations at three different energy levels. The first doping is 1500keV and contains 10 per cubic centimeter 18 Phosphorus atoms of 1000keV for the second time, containing-0.5X 10 per cubic centimeter 18 Phosphorus atoms, the third doping is 750keV, each cubic centimeter contains-10 17 And a phosphorus atom. Followed by rapid thermal annealing.
The p + layer 2 (05) and the n + layer 2 (06) are second epitaxial layers and are about 2 mu m thick. The P + and n + doping forms a green photodiode for absorbing green information in incident light. The next step is to form: the negative terminal of (1) the green photodiode, (2) connected to the negative terminal of the red photodiode, and (3) connected to the negatively doped isolation region between the pixels. The latter two connections are first achieved by using three different doping concentrations at three different energy levels. The first doping is 1500keV and contains 10 per cubic centimeter 18 Phosphorus atoms of 1000keV for the second time, containing-0.5X 10 per cubic centimeter 18 Phosphorus atoms, the third doping is 750keV, each cubic centimeter contains-10 17 And a phosphorus atom. The final doping step is to form a film having-10 per cubic centimeter at 75keV energy 17 The negative terminal of the green photodiode for each phosphorus atom is then subjected to rapid thermal annealing.
The p + layer 3 (07) and the n + layer 3 (08) are third epitaxial layers and have the thickness of about 0.8 μm. P + and n + are doped positively and negatively to form a blue photodiode for absorbing blue information in incident light. The next step isComprises the following steps: (1) the negative terminal of the blue photodiode, (2) to the negative terminals of the green and red photodiodes, (3) to the negatively doped isolation region between the pixels. The latter two connections are first achieved by using two different doping concentrations at three different energy levels. The first doping is 1500keV and contains 10 per cubic centimeter 18 Phosphorus atoms of 1000keV for the second time, containing-0.5X 10 per cubic centimeter 18 Phosphorus atoms, the third doping is 750keV, each cubic centimeter contains-10 17 And a phosphorus atom. The last step is to form a dielectric layer having a thickness of-10 per cubic centimeter at an energy of 75keV 17 The negative terminal of the blue photodiode, which is a phosphorus atom, is then subjected to rapid thermal annealing.
The photoelectron drift layer (09) has a steep doping profile, so that the sensitivity to ultraviolet light and the robustness of the sensitivity are improved. For absorbing ultraviolet information in incident light. The method comprises the following steps: the buried n-layer structure includes (1) an upper neutral region, (2) a middle p + layer, and (3) a buried n-layer. The neutral region is distributed at the surface and has a sufficiently high dopant concentration. The p + layer has a uniform thin and steep doping profile and thus creates an electric field to drift the photo-generated electrons to the buried n layer. There is a low concentration junction between the p + layer and the buried n layer. The purpose is to reduce the electric field at the pn junction to suppress dark current. In addition, the junction depth (x) is designed j =80 nm) and dopant concentration such that when the buried n-layer is fully depleted, the depletion layer does not reach the incident light side surface. A negatively doped isolation region between adjacent pixels is next created to prevent lateral flow of photo-induced electron-hole pairs. The isolation region is formed by using three different doping concentrations at three different energy levels. The first doping is 1500keV and contains 10 per cubic centimeter 18 Phosphorus atoms of 1000keV for the second time, containing-0.5X 10 per cubic centimeter 18 Phosphorus atoms, the third doping is 750keV, each cubic centimeter contains-10 17 And a phosphorus atom. Followed by rapid thermal annealing.
The color information output circuit (10) is used for simultaneously accessing information in three photodiodes and a photoelectron drift layer (09) in a line parallel mode. The positive terminals of all the photodiodes are connected to ground potential. The negative terminal of each photodiode is connected to each readout circuit in the pixel.
Each photodiode and the photogenerated electron drift layer (09) are provided with three transistors to reduce the pixel pitch of the CMOS image sensor. Wherein the gates of the access transistor and the reset transistor are connected separately to reduce the number of metal lines used within each pixel.
The color information output circuit (10) includes three transistors: a reset transistor, a source follower and an access transistor. The reset transistor controls the integration (or exposure) time of the photodiode such that photon-generated electron-hole pairs are integrated on the photodiode intrinsic capacitance when the gate voltage is low. The source follower buffers the integrated photodiode voltage before outputting it onto the column bus. The access transistor controls access to the readout bus so that all pixels in a row share the same readout bus. The gates of the reset and access transistors for the red, green and blue photodiodes are connected together; thus, all three photodiodes have the same exposure control and can be accessed in parallel at the same time. This minimizes the number of metal lines per pixel and the pixel pitch.
The 0-degree nanowire polarization filter (11), the 45-degree nanowire polarization filter (12), the 90-degree nanowire polarization filter (13) and the 135-degree nanowire polarization filter (14) are deposited on each pixel by adopting interference lithography and reactive ion etching technologies as shown in fig. 2, the metal nanowires are 75nm in width and 250nm in height, and have 50% of working period. Therefore, each pixel is sensitive to the polarized light, and the robustness of the polarized light sensitivity of the CMOS image sensor is enhanced.
The manufacturing method of the metal aluminum nanowire polarization filter of the color polarization CMOS image sensor comprises the following steps:
1. a 250nm thick layer of aluminum was deposited on the substrate by electron beam deposition.
2. Depositing 75nm thick SiO on top of the aluminum layer by chemical vapor deposition 2 And (3) a layer. This layer will serve as a hard mask for etching the underlying aluminum.
3. A140 nm thick layer of S-1805 photoresist was applied at 3000 rpm.
4. The samples were baked at 120 ℃ for 90 seconds and then cooled at 70 ℃ for 30 seconds to avoid cracking in the photoresist.
5. The quartz mask was brought into contact with the sample. The mask is composed of a layer of chrome to block light except for selected pixels where chrome is removed. Each even pixel in each even row has chromium removed and will be exposed to the interference pattern.
6. An interference pattern was generated using a 532nm continuous wave neodymium-doped yttrium aluminum garnet (Nd: YAQ) laser coupled with a frequency multiplier. The two laser beams are aligned to intersect at 110 and produce a 140nm periodic interference pattern on the surface of the exposed photoresist. The photoresist was exposed for 40 seconds.
7. The direction of application of the adhesive is in contact with the substrate. Both the mask and the substrate are rotated 45 deg. with respect to the interference pattern. The photoresist was exposed for 40 seconds.
8. Step 7 was repeated twice, yielding 90 ° and 135 ° pixelated nanowire filters. .
9. After four consecutive exposures, the photoresist was developed for 60 seconds while the sample was stirred.
10. Inductively coupled plasma reactive ion etching (ICP RIE) for etching SiO 2 . At the end of this step, the 75nm nanowire pattern was transferred from the photoresist to the underlying SiO 2 And (3) a layer.
11. The aluminum layer was next etched using a standard ICP RIE recipe. SiO 2 2 The layer acts as a hard mask for etching aluminum and enables the formation of deep trenches, i.e., aluminum nanowires 250nm high and 75nm wide. (high aspect ratio aluminum structures cannot be obtained using photoresist because the photoresist has a higher etch rate than aluminum, and thus it is not possible to form a photoresist structure having an aspect ratio of 100 or higher.)
The manufacturing method of the metal aluminum copper nanowire polarization filter of the color polarization CMOS image sensor comprises the following steps:
1. deposition of 75nm thick SiO on top of the substrate by chemical vapor deposition 2 And (3) a layer. This layer will serve as a hard mask for etching the electroplated copper.
2. A140 nm thick layer of S-1805 photoresist was applied at 3000 rpm.
3. The samples were baked at 120 ℃ for 90 seconds and then cooled at 70 ℃ for 30 seconds to avoid cracking in the photoresist.
4. The quartz mask was brought into contact with the sample. The mask is composed of a layer of chrome to block light except for selected pixels where chrome is removed. Each even pixel in each even row has chromium removed and will be exposed to the interference pattern.
5. An interference pattern was generated using a 532nm continuous wave neodymium-doped yttrium aluminum garnet (Nd: YAQ) laser coupled with a frequency multiplier. The two laser beams are aligned to intersect at 110 ° and produce a 140nm periodic interference pattern on the surface of the exposed photoresist. The photoresist was exposed for 40 seconds.
6. The direction of application of the adhesive is in contact with the substrate. Both the mask and the substrate are rotated 45 deg. with respect to the interference pattern. The photoresist was exposed for 40 seconds.
7. Step 6 was repeated twice, yielding 90 ° and 135 ° pixelated nanowire filters.
8. After four consecutive exposures, the photoresist was developed for 60 seconds while the sample was stirred.
9. Inductively coupled plasma reactive ion etching (ICP RIE) for etching SiO 2 . At the end of this step, the 75nm nanowire pattern was transferred from the photoresist to the underlying SiO 2 And (3) a layer.
10. In the formation of SiO 2 On the pattern, a 350nm thick copper layer was deposited by electroplating.
11. The excess copper layer was removed by CMP, finally leaving a 250nm thick copper layer.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (1)

1. A color polarization CMOS image sensor, the structure comprising: the photoelectric composite film comprises a p + substrate (01), a p + layer 1 (02), an n + layer forming a negative doping isolation region, an n + layer 1 (04), a p + layer 2 (05), an n + layer 2 (06), a p + layer 3 (07), an n + layer 3 (08), a photoelectron drift layer (09), a color information output circuit (10), a 0-degree nanowire polarization filter (11), a 45-degree nanowire polarization filter (12), a 90-degree nanowire polarization filter (13) and a 135-degree nanowire polarization filter (14);
the CMOS image sensor comprises 1300 x 800 pixels, each pixel comprises 3 vertically stacked photodiodes and a photoelectron drift layer (09), and a negative doped isolation region is formed between different adjacent pixels and is used for preventing electron-hole pairs generated by photons in one pixel from diffusing to adjacent pixels;
the p + layer 1 (02) is disposed on the p + substrate (01);
the n + layer 1 (04) is arranged on the p + layer 1 (02) to form a red photodiode for absorbing red light information in incident light;
the p + layer 2 (05) is disposed on the n + layer 1 (04);
the n + layer 2 (06) is arranged on the p + layer 2 (05), forming a green photodiode for absorbing green information in incident light;
the p + layer 3 (07) is disposed on the n + layer 2 (06);
the n + layer 3 (08) is arranged on the p + layer 3 (07) to form a blue photodiode for absorbing blue information in incident light;
the photoelectron drift layer (09) is arranged on the n + layer 3 (08); therefore, the spectral response of 200 nm-1000 nm is realized, and each diode is realized by a method of alternately doping p + and n +, which specifically comprises the following steps:
the p + layer 1 (02) and the n + layer 1 (04) form a red photodiode, and the thickness of the red photodiode is 1.5 mu m; the p + layer 2 (05) and the n + layer 2 (06) form a green photodiode, the green photodiode having a thickness of 2 μm; the p + layer 3 (07) and the n + layer 3 (08) form a blue photodiode, and the thickness of the blue photodiode is 0.8 mu m;
after the three photodiodes are deposited, a photoelectron drift layer (09) is uniformly formed, and the photoelectron drift layer has a steep doping profile, so that the sensitivity to ultraviolet light and the robustness of the sensitivity are improved;
the photoelectron drift layer comprises: a neutral region of the upper layer, a p + layer in the middle, a buried n layer with a low concentration junction between the p + layer and the buried n layer, the junction depth and dopant concentration being designed such that when the buried n layer is fully depleted, the depletion layer does not reach the incident light side surface;
the color information output circuit (10) simultaneously accesses three photodiodes and a photoelectron drift layer (09) in a line-parallel manner;
each photodiode and photoelectron drift layer (09) are respectively provided with three transistors, and the pixel pitch of the CMOS image sensor is reduced through compact configuration;
the nanowire polarization filter is deposited on each pixel by adopting the technologies of interference lithography and reactive ion etching, and comprises a 0-degree nanowire polarization filter (11), a 45-degree nanowire polarization filter (12), a 90-degree nanowire polarization filter (13) and a 135-degree nanowire polarization filter (14), wherein the metal nanowire is 75nm in width and 250nm in height, and has a working period of 50%.
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