CN110134177A - A kind of embedded system timing system and its method applied to smart grid - Google Patents
A kind of embedded system timing system and its method applied to smart grid Download PDFInfo
- Publication number
- CN110134177A CN110134177A CN201811454142.XA CN201811454142A CN110134177A CN 110134177 A CN110134177 A CN 110134177A CN 201811454142 A CN201811454142 A CN 201811454142A CN 110134177 A CN110134177 A CN 110134177A
- Authority
- CN
- China
- Prior art keywords
- module
- serial communication
- dsp
- fpga
- irig
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 18
- 238000004891 communication Methods 0.000 claims description 74
- 230000005540 biological transmission Effects 0.000 claims description 34
- 230000009977 dual effect Effects 0.000 claims description 14
- 230000006870 function Effects 0.000 claims description 11
- 230000001360 synchronised effect Effects 0.000 claims description 8
- 238000012544 monitoring process Methods 0.000 claims description 5
- 230000008054 signal transmission Effects 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 3
- 230000002123 temporal effect Effects 0.000 claims description 3
- 238000009825 accumulation Methods 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000007630 basic procedure Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
Abstract
A kind of embedded system timing system applied to smart grid, comprising: global position system GPS module, digital signal processor DSP module, on-site programmable gate array FPGA module, embedded Linux system CPU PowerPC, system time memory module, power module；The present invention is capable of providing the calibration of ns grades of split-second precisions, while when realizing embedded system accurate school, realizes time synchronization between dsp chip and embedded system.
Description
Technical field
The invention belongs to smart grid fields, and in particular to a kind of embedded system timing system applied to smart grid
And its method.
Background technique
With the fast development of smart grid, electric system monitors essence to control protective unit time synchronization each in substation
More stringent requirements are proposed for degree.As Power System Flexible ac transmission FACTS device, control protective unit is usually configured
DSP (digital signal processor) and FPGA (online programmable gate array) and embedded type CPU processor.DSP and FPGA is completed
Protection algorism and each device and board communication and data transmission are controlled, the time system of DSP is usually using GPS Irig-B code
When (referred to as " B code ") school, for safeguarding SOE event time information.Embedded type CPU runs application software (containing protocol stack), realizes
Ethernet communication, LCD such as show at the functions.
Embedded type CPU (SuSE) Linux OS, mode is generally using Ethernet as medium when school, and agreement uses NTP when school
The various protocols such as (Network Time Protocol), IEEE1588.SNTP correcting delay precision be number ms to hundreds of ms, precision compared with
Difference；IEEE1588 precision is higher, can arrive ns grades, but need hardware supported, realizes complex.According to DL/T1100.1-2009
Electric system clock synchronization system first part demand of technical standard, plant stand internal time Simultaneous Monitoring precision are not more than 3ms.When
Embedded Linux system is non-real time operating system, and when using calibration methods such as NTP, correcting delay precision is poor, simultaneously because operation
Linux, timeslice are 1ms~10ms, have larger time difference (number ms or more) when executing time synchronization operation, are unable to satisfy the time
Synchronization accuracy requirement.
In view of problem above, need to propose a kind of accurately real-time time synchronous method.
Summary of the invention
In view of the deficiencies of the prior art, the present invention provides be when a kind of embedded system school applied to smart grid
System is applied to flexible AC transmission FACTS product control protection device telecommunication management plate, and the timing system includes: global positioning system
System GPS module, digital signal processor DSP module, on-site programmable gate array FPGA module, embedded Linux system
CPUPowerPC, system time memory module, power module；The GPS module, the DSP module, the FPGA module, institute
PowerPC is stated to be sequentially connected by serial communication interface；The GPS module and the DSP module pass through serial communication bus phase
Even；
The DSP module, including the registers such as serial communication module and bus control register, interrupt register are protected
The normal operation of DSP is demonstrate,proved, the serial communication module integrates the function of multiple serial communication protocols, can realize according to configuration more
The communication pattern of one of a serial communication protocol, the serial communication module include port control modules；
The FPGA module, including having, there are two the dual port RAM module of separate port, FPGA and FPGA to configure chip, institute
Dual port RAM module is stated for realizing independent read-write capability by two paths, wherein channel is read and write for DSP all the way, it is another
Paths are read and write for PowerPC, and the FPGA configuration chip is used to store the information of FPGA, and the FPGA is to the twoport
RAM module is written and read control and address decoding processing；
The power module is connect with each module and PowerPC, voltage needed for providing whole system work.
A kind of embedded system calibration method applied to smart grid is additionally provided, above-mentioned timing system, institute are applied to
Stating calibration method includes:
Step 1, after the booting of timing system device power-on, timing system automatically adds the program of DSP module and FPGA module
It is downloaded in corresponding control chip, module is made to complete initialization；
Step 2, FPGA module corresponds to pin to the DSP module and configures, while when by the output of the DSP module
Clock is as local global clock；
Step 3, GPS module sends signal to the DSP module, and serial communication module carries out type judgement to signal；
Step 4, when judging the signal of communication for IRIG-B correcting delay signal, the serial communication module is based on described
IRIG-B correcting delay signal selected from multiple serial communication protocols applicable serial communication protocol with by serial communication bus into
Row communication；
Step 5, the serial communication mode for determining the IRIG-B correcting delay signal is synchronous serial communication；
Step 6, the configuration mode of the port control modules of the serial communication bus is coupled in judgement, when the port is controlled
When molding block is configurable for the asynchronous communication on the serial communication bus, according to the local global clock signal,
By the port control modules from asynchronous serial communication mode adjustment be synchronous serial communication mode；
Step 7, the serial communication protocol for enabling serial bus interface and selection transmits the IRIG-B correcting delay signal；
Step 8, the DSP module receives the IRIG-B correcting delay signal, works as from IRIG-B correcting delay signal acquisition
The corresponding level signal of preceding time data, converts the level signal to current system time information T0；
Step 9, the DSP module interruption adds up to system time, generates and interrupts IRQ；
Step 10, the temporal information T0 is write dual port RAM module described in the FPGA module by the DSP module
In agreed address, the interruption IRQ is transferred to PowerPC by interface by the FPGA module；
Step 11, the PowerPC receives the laggard row information judgement of the interruption IRQ, when being judged as school in information
When disconnected, system time information T1 at this time is recorded；
Step 12, the PowerPC starts interrupt service subroutine, from the dual port RAM module of the FPGA module
Agreed address in read the T0 time information data, record system time information T2 at this time；
Step 13, the PowerPC corrects system time using system function.
The beneficial effect comprise that firstly, itself clock accuracy is inadequate the present invention overcomes existing embedded system,
And error can lead to the problem of accumulation, be capable of providing ns grades of split-second precision calibrations, time error does not accumulate；Secondly, of the invention
It is designed by dual port RAM, when not only realizing the accurate school of embedded system, but also when realizing between dsp chip and embedded system
Between synchronous, the problem of avoiding the dispersion of linux system timeslice, by strictly testing, dsp chip and Power PC Processor two
Person time maximum difference 121us, can accomplish 0.1ms grades, even if the influence of embedded Linux system timeslice, is still able to satisfy
Plant stand internal time Simultaneous Monitoring precision is not more than the requirement of 3ms；Again, the present invention is by multiple individual serial communication protocols
Function is combined into the interface individually combined, and can carry out dynamic adjustment, meets different transmission mode demand；Finally, this hair
It is bright by monitor IRIG-B correcting delay signal transmission state, when transmitted error rate be more than threshold value then calibrate automatically, make transmission rate with
Adjustment and the transmission rate that levels off to request, can effectively reduce the generation of error of transmission, and be dynamically adapted transmission rate with
Meet different transmission rate requirements.
Detailed description of the invention
The basic framework of timing system Fig. 1 proposed by the invention.
The basic procedure of calibration method Fig. 2 proposed by the invention.
Specific embodiment
For a better understanding of the present invention, with reference to the description of the embodiment of the accompanying drawings, method of the invention is carried out
Further instruction.
In order to fully understand the present invention, numerous details are referred in the following detailed description.But art technology
Personnel are it should be understood that the present invention may not need these details and realize.In embodiment, it is not described in detail well known side
Method, process, component, in order to avoid unnecessarily make embodiment cumbersome.
A kind of embedded system timing system applied to smart grid shown in Figure 1, of the invention is applied to flexibility
Ac transmission FACTS product control protection device telecommunication management plate, the timing system includes: global position system GPS module, number
When signal processor DSP module, on-site programmable gate array FPGA module, embedded Linux system CPU PowerPC, system
Between memory module, power module；The GPS module, the DSP module, the FPGA module, the PowerPC pass through serial
Communication interface is sequentially connected；The GPS module is connected with the DSP module by serial communication bus；
The DSP module, including the registers such as serial communication module and bus control register, interrupt register are protected
The normal operation of DSP is demonstrate,proved, the serial communication module integrates the function of multiple serial communication protocols, can realize according to configuration more
The communication pattern of one of a serial communication protocol, the serial communication module include port control modules；
The FPGA module, including having, there are two the dual port RAM module of separate port, FPGA and FPGA to configure chip, institute
Dual port RAM module is stated for realizing independent read-write capability by two paths, wherein channel is read and write for DSP all the way, it is another
Paths are read and write for PowerPC, and the FPGA configuration chip is used to store the information of FPGA, and the FPGA is to the twoport
RAM module is written and read control and address decoding processing；
The power module is connect with each module and PowerPC, voltage needed for providing whole system work.
Preferably, wherein the timing system further includes system time memory module, tired for carrying out to system time
Add.
Preferably, wherein the GPS module includes GPS receiver chip, GPS transmitting chip, satellite signal receiving equipment.
A kind of embedded system calibration method applied to smart grid shown in Figure 2, of the invention is applied to above-mentioned
Timing system, the calibration method include:
Step 1, after the booting of timing system device power-on, timing system automatically adds the program of DSP module and FPGA module
It is downloaded in corresponding control chip, module is made to complete initialization；
Step 2, FPGA module corresponds to pin to the DSP module and configures, while when by the output of the DSP module
Clock is as local global clock；
Step 3, GPS module sends signal to the DSP module, and serial communication module carries out type judgement to signal；
Step 4, when judging the signal of communication for IRIG-B correcting delay signal, the serial communication module is based on described
IRIG-B correcting delay signal selected from multiple serial communication protocols applicable serial communication protocol with by serial communication bus into
Row communication；
Step 5, the serial communication mode for determining the IRIG-B correcting delay signal is synchronous serial communication；
Step 6, the configuration mode of the port control modules of the serial communication bus is coupled in judgement, when the port is controlled
When molding block is configurable for the asynchronous communication on the serial communication bus, according to the local global clock signal,
By the port control modules from asynchronous serial communication mode adjustment be synchronous serial communication mode；
Step 7, the serial communication protocol for enabling serial bus interface and selection transmits the IRIG-B correcting delay signal；
Step 8, the DSP module receives the IRIG-B correcting delay signal, works as from IRIG-B correcting delay signal acquisition
The corresponding level signal of preceding time data, converts the level signal to current system time information T0；
Step 9, the DSP module interruption adds up to system time, generates and interrupts IRQ；
Step 10, the temporal information T0 is write dual port RAM module described in the FPGA module by the DSP module
In agreed address, the interruption IRQ is transferred to PowerPC by interface by the FPGA module；
Step 11, the PowerPC receives the laggard row information judgement of the interruption IRQ, when being judged as school in information
When disconnected, system time information T1 at this time is recorded；
Step 12, the PowerPC starts interrupt service subroutine, from the dual port RAM module of the FPGA module
Agreed address in read the T0 time information data, record system time information T2 at this time；
Step 13, the PowerPC corrects system time using system function.
Preferably, wherein the system function for correcting system time is do_settimeofday (), and correction is public
Formula is T=T0+ (T2-T1).
Preferably, wherein described in the serial communication protocol transmission of the step 7, enabling serial bus interface and selection
IRIG-B correcting delay signal, specifically includes:
Step 7-1 receives transmission rate request；
Step 7-2 is calculated according to transmission rate request to generate a fractional value；
Step 7-3 generates the first transmission rate by preset reference frequency divided by the fractional value；
First transmission rate is supplied to the DSP module, makes the DSP module according to described first by step 7-4
Transmission rate receives the IRIG-B correcting delay signal；
Step 7-5, the transmitted error rate of monitoring signal transmission adjust described point if the transmitted error rate is more than threshold value
Numerical value generates the second transmission rate, second transmission rate is provided by the reference frequency divided by the fractional value after adjusting
To the DSP module, the DSP module is made to receive the IRIG-B correcting delay signal according to second transmission rate.
Compared with prior art, the present invention its remarkable advantage are as follows: firstly, the present invention overcomes existing embedded systems itself
Clock accuracy is inadequate, and error can lead to the problem of accumulation, is capable of providing ns grades of split-second precision calibrations, and time error is not accumulated
It is tired；Secondly, the present invention is designed by dual port RAM, when not only realizing the accurate school of embedded system, but also realize dsp chip and
Time synchronization between embedded system avoids the problem of linux system timeslice is dispersed；Again, the present invention will be multiple individual
The function of serial communication protocol is combined into the interface individually combined, and can carry out dynamic adjustment, meets different transmission mode
Demand；Finally, the present invention passes through monitoring IRIG-B correcting delay signal transmission state, when transmitted error rate is more than threshold value then automatic school
Standard makes transmission rate level off to transmission rate request therewith adjusting, can effectively reduce the generation of error of transmission, and can dynamic
Transmission rate is adjusted to meet different transmission rate requirements.
Here the preferred embodiment of the present invention is only illustrated, but its meaning is not intended to limit the scope of the invention, applicability and is matched
It sets.On the contrary, detailed explanation of the embodiments can be implemented by those skilled in the art.It will be understood that without departing from appended power
In the case of the spirit and scope of the invention that sharp claim determines, changes and modifications may be made to details.
Claims (6)
1. a kind of embedded system timing system applied to smart grid is applied to flexible AC transmission FACTS product control and protects
Device telecommunication management plate, which is characterized in that the timing system includes: global position system GPS module, digital signal processor
DSP module, on-site programmable gate array FPGA module, embedded Linux system CPU PowerPC, system time memory module,
Power module；The GPS module, the DSP module, the FPGA module, the PowerPC pass through serial communication interface successively
Connection；The GPS module is connected with the DSP module by serial communication bus；
The DSP module, including the registers such as serial communication module and bus control register, interrupt register guarantee DSP
Normal operation, the serial communication module integrates the function of multiple serial communication protocols, can be realized according to configuration multiple serial
The communication pattern of one of communication protocol, the serial communication module include port control modules；
The FPGA module, it is described double including having there are two the dual port RAM module of separate port, FPGA and FPGA configuration chip
Mouth RAM module is used to realize independent read-write capability by two paths, wherein channel is read and write for DSP all the way, another way is logical
Road is read and write for PowerPC, and the FPGA configuration chip is used to store the information of FPGA, and the FPGA is to the dual port RAM mould
Block is written and read control and address decoding processing；
The power module is connect with each module and PowerPC, voltage needed for providing whole system work.
2. the system as claimed in claim 1, wherein the timing system further includes system time memory module, for being
The system time adds up.
3. the system as claimed in claim 1, wherein the GPS module includes GPS receiver chip, GPS transmitting chip, satellite
Signal receiver.
4. a kind of embedded system calibration method applied to smart grid, a kind of application applied to one of claim 1-3
In the embedded system timing system of smart grid, which is characterized in that the calibration method includes:
Step 1, after the booting of timing system device power-on, timing system is automatically loaded into the program of DSP module and FPGA module
In corresponding control chip, module is made to complete initialization；
Step 2, FPGA module corresponds to pin to the DSP module and configures, while the output clock of the DSP module being made
For local global clock；
Step 3, GPS module sends signal to the DSP module, and serial communication module carries out type judgement to signal；
Step 4, when judging the signal of communication for IRIG-B correcting delay signal, the serial communication module is based on the IRIG-B
Correcting delay signal selects applicable serial communication protocol to be communicated by serial communication bus from multiple serial communication protocols；
Step 5, the serial communication mode for determining the IRIG-B correcting delay signal is synchronous serial communication；
Step 6, the configuration mode of the port control modules of the serial communication bus is coupled in judgement, when the port controlling mould
When block is configurable for the asynchronous communication on the serial communication bus, according to the local global clock signal, by institute
State port control modules from asynchronous serial communication mode adjustment be synchronous serial communication mode；
Step 7, the serial communication protocol for enabling serial bus interface and selection transmits the IRIG-B correcting delay signal；
Step 8, the DSP module receives the IRIG-B correcting delay signal, when obtaining current from the IRIG-B correcting delay signal
Between the corresponding level signal of data, convert the level signal to current system time information T0；
Step 9, the DSP module interruption adds up to system time, generates and interrupts IRQ；
Step 10, the DSP module writes the temporal information T0 agreement of dual port RAM module described in the FPGA module
In address, the interruption IRQ is transferred to PowerPC by interface by the FPGA module；
Step 11, the PowerPC receives the laggard row information judgement of the interruption IRQ, when being judged as school when message interrupts,
Record system time information T1 at this time；
Step 12, the PowerPC starts interrupt service subroutine, from the pact of the dual port RAM module of the FPGA module
Determine to read the T0 time information data in address, records system time information T2 at this time；
Step 13, the PowerPC corrects system time using system function.
5. method as claimed in claim 4, wherein the system function for correcting system time is do_
Settimeofday (), updating formula are T=T0+ (T2-T1).
6. method as claimed in claim 4, wherein the step 7 enables the serial communication association of serial bus interface and selection
View transmits the IRIG-B correcting delay signal, specifically includes:
Step 7-1 receives transmission rate request；
Step 7-2 is calculated according to transmission rate request to generate a fractional value；
Step 7-3 generates the first transmission rate by preset reference frequency divided by the fractional value；
First transmission rate is supplied to the DSP module by step 7-4, makes the DSP module according to first transmission
Rate receives the IRIG-B correcting delay signal；
The transmitted error rate of step 7-5, monitoring signal transmission adjust the fractional value if the transmitted error rate is more than threshold value,
By the reference frequency divided by the fractional value after adjusting, the second transmission rate is generated, second transmission rate is supplied to institute
DSP module is stated, the DSP module is made to receive the IRIG-B correcting delay signal according to second transmission rate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811454142.XA CN110134177A (en) | 2018-11-30 | 2018-11-30 | A kind of embedded system timing system and its method applied to smart grid |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811454142.XA CN110134177A (en) | 2018-11-30 | 2018-11-30 | A kind of embedded system timing system and its method applied to smart grid |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110134177A true CN110134177A (en) | 2019-08-16 |
Family
ID=67568210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811454142.XA Pending CN110134177A (en) | 2018-11-30 | 2018-11-30 | A kind of embedded system timing system and its method applied to smart grid |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110134177A (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101105401A (en) * | 2007-08-06 | 2008-01-16 | 北京航空航天大学 | SDINS/GPS combined guidance system time synchronism and synchronous data extraction method |
| CN101261129A (en) * | 2008-02-22 | 2008-09-10 | 北京航空航天大学 | Integrated navigation computer based on DSP and FPGA |
| US20090103570A1 (en) * | 2005-06-29 | 2009-04-23 | Abb Oy | Time Synchronization in Serial Communications |
| CN201497873U (en) * | 2009-04-07 | 2010-06-02 | 上海许继电气有限公司 | IRIG-B signal decoding timing card device based on CPCI bus |
| CN101882989A (en) * | 2010-05-28 | 2010-11-10 | 四川大学 | Synchronization method based on distributed-type integrated recorder parallel buses |
| CN103019141A (en) * | 2012-12-28 | 2013-04-03 | 成都天进科技有限公司 | Control module, control method and electric power dynamic recording device and implementation method thereof |
| CN203313199U (en) * | 2013-06-03 | 2013-11-27 | 刘庆依 | Intelligent electronic device IEEE C37.238 time synchronization system |
| CN103439590A (en) * | 2013-08-08 | 2013-12-11 | 深圳市康必达中创科技有限公司 | Electric energy monitoring DSP control system |
| CN103678728A (en) * | 2013-11-25 | 2014-03-26 | 北京航空航天大学 | High-speed data recording system based on FPGA+DSP framework and establishment method thereof |
| CN203691063U (en) * | 2014-01-07 | 2014-07-02 | 国电南瑞科技股份有限公司 | Intelligent transformer station centralized measurement and control apparatus |
| CN104730919A (en) * | 2015-04-02 | 2015-06-24 | 西安电子科技大学 | Beidou satellite timing system and method |
| CN107925564A (en) * | 2015-09-01 | 2018-04-17 | 高通股份有限公司 | Multi-phase clock data recovery circuit is calibrated |
-
2018
- 2018-11-30 CN CN201811454142.XA patent/CN110134177A/en active Pending
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090103570A1 (en) * | 2005-06-29 | 2009-04-23 | Abb Oy | Time Synchronization in Serial Communications |
| CN101105401A (en) * | 2007-08-06 | 2008-01-16 | 北京航空航天大学 | SDINS/GPS combined guidance system time synchronism and synchronous data extraction method |
| CN101261129A (en) * | 2008-02-22 | 2008-09-10 | 北京航空航天大学 | Integrated navigation computer based on DSP and FPGA |
| CN201497873U (en) * | 2009-04-07 | 2010-06-02 | 上海许继电气有限公司 | IRIG-B signal decoding timing card device based on CPCI bus |
| CN101882989A (en) * | 2010-05-28 | 2010-11-10 | 四川大学 | Synchronization method based on distributed-type integrated recorder parallel buses |
| CN103019141A (en) * | 2012-12-28 | 2013-04-03 | 成都天进科技有限公司 | Control module, control method and electric power dynamic recording device and implementation method thereof |
| CN203313199U (en) * | 2013-06-03 | 2013-11-27 | 刘庆依 | Intelligent electronic device IEEE C37.238 time synchronization system |
| CN103439590A (en) * | 2013-08-08 | 2013-12-11 | 深圳市康必达中创科技有限公司 | Electric energy monitoring DSP control system |
| CN103678728A (en) * | 2013-11-25 | 2014-03-26 | 北京航空航天大学 | High-speed data recording system based on FPGA+DSP framework and establishment method thereof |
| CN203691063U (en) * | 2014-01-07 | 2014-07-02 | 国电南瑞科技股份有限公司 | Intelligent transformer station centralized measurement and control apparatus |
| CN104730919A (en) * | 2015-04-02 | 2015-06-24 | 西安电子科技大学 | Beidou satellite timing system and method |
| CN107925564A (en) * | 2015-09-01 | 2018-04-17 | 高通股份有限公司 | Multi-phase clock data recovery circuit is calibrated |
Non-Patent Citations (2)
| Title |
|---|
| 张道杰: "基于锁相环结构的GPS时间同步系统及其在电力系统中的应用研究", 中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑, no. 2011, pages 1 - 71 * |
| 杨书杰等;: "基于FPGA的高速数据采集系统研制", 电力自动化设备, vol. 28, no. 06, pages 93 - 96 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10707984B2 (en) | Techniques for synchronizing slave devices | |
| EP2432754B1 (en) | Method and apparatus for synchronising the local time of a plurality of instruments | |
| CN109617641B (en) | Adjustable precision time obtaining method based on pulse per second | |
| US20080155244A1 (en) | Method for updating the timing of a baseboard management controller | |
| CN202008583U (en) | Clock source of synchronous phasor measuring device | |
| WO2013090246A1 (en) | Systems and methods for time synchronization of ieds via radio link | |
| CN109683567B (en) | RS485 network-based system clock synchronization method | |
| CN105446917B (en) | The device that the data record and location information of a kind of PPK-RTK obtains | |
| WO2021008532A1 (en) | Active antenna unit delay alignment method and apparatus and active antenna unit | |
| CN114567926B (en) | Clock synchronization and trigger device for wireless distributed test system | |
| CN102023565A (en) | Device and method for outputting time information | |
| CN111831056A (en) | Real-time clock calibration module and method and real-time clock chip | |
| CN110955179B (en) | Dual-channel shared clock trigger delay adjusting device based on PCI bus | |
| WO2007000498A1 (en) | Method for synchronizing an automation data communications network | |
| CN109407752B (en) | GIS breaker online monitoring system for realizing clock synchronization in RS485 communication | |
| CN110134177A (en) | A kind of embedded system timing system and its method applied to smart grid | |
| CN103178920A (en) | Multi-channel synchronization method in test system of digital transformer substation | |
| CN201185428Y (en) | Time synthesis measuring instrument | |
| CN201556048U (en) | Multifunctional time integrating measuring instrument | |
| CN203708224U (en) | Multipurpose serial time code decoder | |
| CN102983959B (en) | Method for realizing one-step mode and two-step mode for PTP (precision time synchronization protocol) in a plurality of MAC | |
| CN103888211A (en) | Method and device for data transmission between crossed chips | |
| CN102821457A (en) | Clock synchronizing method based on software defined radio and software defined radio system | |
| CN109995137A (en) | A kind of automatic system of intelligent transformer station | |
| CN102426414B (en) | Time checking method of electric energy quality monitoring system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |