CN110133379B - Method for measuring parasitic inductance of Josephson junction - Google Patents
Method for measuring parasitic inductance of Josephson junction Download PDFInfo
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- CN110133379B CN110133379B CN201910506053.3A CN201910506053A CN110133379B CN 110133379 B CN110133379 B CN 110133379B CN 201910506053 A CN201910506053 A CN 201910506053A CN 110133379 B CN110133379 B CN 110133379B
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Abstract
The invention provides a method for measuring the parasitic inductance of a Josephson junction, which comprises the following steps: providing a first test structure to obtain a first inductor; providing a second test structure to obtain a second inductor; providing a third test structure to obtain a third inductor; providing a fourth test structure to obtain a fourth inductor; and calculating to obtain the parasitic inductance of the single Josephson junction based on the condition that the sum of the inductances of the wires in the first test structure and the second test structure is the same as the sum of the inductances of the wires in the third test structure and the fourth test structure. The invention adopts SQUID voltage-magnetic flux modulation technology to obtain the inductance of each test structure, and then obtains the parasitic inductance of a single Josephson junction based on the difference calculation between each test structure, thereby being a method for directly measuring the inductance.
Description
Technical Field
The invention relates to the field of superconducting Josephson junction parameter characterization and superconducting digital circuit design, in particular to a method for measuring the parasitic inductance of a Josephson junction.
Background
In 1961, josephson, a scientist in the united kingdom, discovered the josephson effect named by his name, according to which when a dc voltage is biased across the josephson junction, a certain alternating current is generated in the junction, the frequency of which is proportional to the biased voltage, and when the biased voltage is 1 μ V, the current frequency is 483.6MHz, very high frequency electronic devices can be realized with superconducting josephson junctions, and it has been reported in the literature that the frequency of superconducting counting Flip-flop (TFF, ToggleFlip-Flip) circuits based on josephson junctions reaches 770GHz (Rapid Single Flux Quantum T-Flip operating up to 770GHz, IEEE trans. appl.supercond.9(2), 3212, 1999), and thus superconducting digital devices and circuits based on superconducting josephson junctions have great advantages in increasing the frequency of electronic devices.
First, basic units such as a Josephson Transmission line (JT L, Josephson Junction Transmission L ine), a beam splitter, a buffer and the like can be designed by using a Josephson Junction and an inductor, logic gate circuits such as an AND gate, a NOT gate, an XOR gate and the like of the superconducting digital circuit can be designed by combining the basic units, and then, the logic gate circuits can be integrated into superconducting integrated circuits of different scales and functions by combining the logic gate circuits.
A basic structure of a superconducting digital circuit is an inductance element (prepared by using a superconducting film), another basic structure is a Josephson junction, the Josephson junction is a nonlinear element and needs to be characterized by a plurality of parameters such as critical current Ic, capacitance C, resistance R, and the like, when the specific superconducting digital circuit is designed, firstly the parameters are required to be within a certain range, and the superconducting digital circuit can normally work, but the Josephson junction is a multilayer structure film element, the parameters of distributed inductance, distributed capacitance and the like generated by the multilayer structure film element are widely distributed around a superconducting circuit chip except for the parameters, at present, the Josephson junction applied in the superconducting digital circuit is mainly based on the Josephson junction of Nb or NbN film, the Josephson junction is formed by inserting an insulating layer between an upper electrode and a lower electrode, and connecting a metal film resistor in parallel between the upper electrode and the lower electrode, the equivalent circuit is shown in FIG. 1, wherein L p1, L p 7 and L respectively represent that the parasitic values of an ultrathin wire, a lead wire, a resistor 35p 7 and a parasitic resistance of the superconducting thin film are respectively, the superconducting circuit are designed by a parasitic resistance value of a high frequency band, a parasitic resistance value of a parasitic resistance coefficient of a high frequency circuit is obviously reduced by a high frequency band, a high frequency inductance value of a high frequency inductance, a high frequency circuit is generally considered, a high frequency circuit is considered, a high.
At present, there are two main methods for obtaining the value of the parasitic inductance of the josephson junction, the first is to simulate the current-voltage characteristic curve of the josephson junction by using simulation software such as PSCAN, etc., and obtain the parasitic inductance of the junction by comparing the simulated curve with the actually measured curve, the second is to deduce the inductance difference value in the superconducting digital circuit by comparing the experimental measured value and the designed value of the performance of the superconducting digital circuit, and determine the parasitic inductance value according to the difference value. Both methods derive the parasitic inductance values of the josephson junction by indirect methods. When the current-voltage characteristics of the josephson junction are simulated by using software, firstly, the josephson junction needs to be modeled, and the modeling is related to the structure and the process of the junction, when the structure and the process of the junction are changed, the modeling simulation needs to be carried out again and compared with measured data, and in the second method, the superconducting digital circuit is more complex than the structure of the josephson junction, and the design and the preparation need longer time.
Therefore, how to provide a method for measuring the parasitic inductance of the josephson junction with higher measurement efficiency and higher accuracy has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above disadvantages of the prior art, an object of the present invention is to provide a method for measuring a josephson junction parasitic inductance, which is used to solve the problems of low efficiency, poor accuracy and the like of the method for measuring the josephson junction parasitic inductance in the prior art.
To achieve the above and other related objects, the present invention provides a method for measuring a josephson junction parasitic inductance, the method at least comprising:
providing a first test structure, wherein the first test structure comprises a first Josephson junction array connected in series between a first Josephson junction and a second Josephson junction, one end of the first Josephson junction array is grounded, the first Josephson junction array comprises an even number of sequentially connected Josephson junctions, and the inductance between the first Josephson junction and the second Josephson junction is measured to obtain a first inductance;
providing a second test structure comprising a second josephson junction array in series between the first and second josephson junctions, the second josephson junction array comprising an odd number of sequentially series connected josephson junctions, measuring an inductance between the first and second josephson junctions, resulting in a second inductance;
providing a third test structure comprising a first wire in series between the first and second josephson junctions, the first wire being in the same plane as the underlying wire in series with each josephson junction, measuring the inductance between the first and second josephson junctions, resulting in a third inductance;
providing a fourth test structure, wherein the fourth test structure comprises a second lead connected in series between the first Josephson junction and the second Josephson junction, the second lead and an upper lead connected in series with each Josephson junction are located on the same plane, and measuring inductance between the first Josephson junction and the second Josephson junction to obtain a fourth inductance;
and calculating to obtain the parasitic inductance of the single Josephson junction based on the condition that the sum of the inductances of the wires in the first test structure and the second test structure is the same as the sum of the inductances of the wires in the third test structure and the fourth test structure.
Optionally, the lower layer wire connecting the josephson junctions in series is in the same plane as the bottom electrode of each josephson junction.
More optionally, the material of the wire is a superconducting material.
Optionally, the method of measuring each inductance comprises SQUID flux-voltage modulation techniques.
More optionally, the SQUID flux-voltage modulation technique comprises:
applying a control current to both ends of each test structure, and applying a DC bias current in the first and second Josephson junctions;
adjusting the control current such that a variation of the control current corresponds to an integer multiple of one flux quantum;
and obtaining the value of each inductor based on the relation between the variation of the control current and the integral multiple of one magnetic flux quantum.
Optionally, the parasitic inductance of a single josephson junction satisfies the following relationship:
wherein, LpParasitic inductance of a single Josephson junction, LaIs a first inductance, LbIs a second inductance, LcIs a third inductance, LdFor a fourth inductor, n is the number of josephson junctions in the first josephson junction array, and m is the number of josephson junctions in the second josephson junction array.
More optionally, the number of josephson junctions in the first and second josephson junction arrays is greater than 10.
As described above, the method for measuring the josephson junction parasitic inductance according to the present invention has the following advantageous effects:
the invention relates to a method for measuring the parasitic inductance of a Josephson junction, which adopts SQUID voltage-magnetic flux modulation technology to obtain the inductance of each test structure, and then calculates the parasitic inductance of a single Josephson junction based on the difference between the test structures.
Drawings
Fig. 1 is a schematic diagram showing an equivalent circuit of a josephson junction in the prior art.
Fig. 2 is a schematic diagram showing an equivalent circuit of a josephson transmission line in the prior art.
Fig. 3 is a schematic flow chart of the method for measuring the parasitic inductance of the josephson junction according to the present invention.
FIG. 4 is a schematic diagram of a first test structure according to the present invention.
Fig. 5 is a schematic diagram illustrating the principle of the SQUID flux-voltage modulation technique for measuring inductance according to the present invention.
FIG. 6 is a diagram of a second test structure according to the present invention.
FIG. 7 is a schematic diagram of a third test structure according to the present invention.
FIG. 8 is a diagram illustrating a fourth test structure according to the present invention.
Description of the element reference numerals
1 first test Structure
11 first Josephson junction array
2 second test Structure
21 second josephson junction array
3 third test Structure
4 fourth test Structure
51 substrate
52 first Josephson junction
53 second Josephson junction
54 wiring layer
55 ground plane
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to 8. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
As shown in fig. 3 to 8, the present embodiment provides a method for measuring a josephson junction parasitic inductance, the method at least including:
as shown in fig. 3 and 4, a first test structure 1 is provided to obtain a first inductor L through testinga。
Specifically, the first test structure 1 is located in a SQUID device including a substrate 51, a first josephson junction 52, a second josephson junction 53, a first test structure 1, a wiring layer 54 and a ground layer 55. The first josephson junction 52 and the second josephson junction 53 are formed on the substrate 51, the first josephson junction 52 and the second josephson junction 53 each include a bottom electrode, a top electrode, and an insulating material layer between the bottom electrode and the top electrode (the bottom electrode and the top electrode are made of superconducting material), the bottom electrodes of the first josephson junction 52 and the second josephson junction 53 are located on the substrate 51, and the top electrodes of the first josephson junction 52 and the second josephson junction 53 are connected with an upper ground layer 55 through the wiring layer 54 (the ground layer 55 is made of superconducting material). The first test structure 1 comprises a first josephson junction array 11 and a wire connecting the first josephson junction array 11 in series between the first josephson junction 52 and the second josephson junction 53, the length of the first test structure 1 being set to d. The first josephson junction array 11 is formed on the substrate 51, and the first josephson junction array 11 includes n josephson junctions connected in series in sequence, where n is an even number, preferably, n is set to an even number not less than 10, and in the present embodiment, n is set to 4 for convenience of illustration. Each josephson junction comprises a bottom electrode, a top electrode and an insulating material layer (the bottom electrode and the top electrode are made of superconducting materials) between the bottom electrode and the top electrode, the josephson junctions are sequentially connected in series through the bottom electrode and the top electrode, in the embodiment, the bottom electrode of each josephson junction is connected through a lower layer lead, the top electrode of each josephson junction is connected through an upper layer lead, the lower layer lead and the bottom electrode of each josephson junction are positioned on the same plane (the upper surface and the lower surface are flush, the thickness is equal), and the lower layer lead and the upper layer lead are made of superconducting materials the same as the bottom electrode and the top electrode of the josephson junction. As shown in fig. 4, the bottom electrode of the first josephson junction in the first josephson junction array 11 is connected to the bottom electrode of the first josephson junction 52 through a lower layer wire, the top electrode of the first josephson junction is connected to the top electrode of the second josephson junction through an upper layer wire, and sequentially connected end to end, and the bottom electrode of the fourth josephson junction is connected to the bottom electrode of the second josephson junction 53 through a lower layer wire, thereby realizing series connection.
The lower layer wire may be disposed under the bottom electrode of each josephson junction, and may be made of a superconducting material. The upper layer wire is not lower than the top electrode of each josephson junction, and in the embodiment, the upper layer wire is arranged on the top electrode of each josephson junction and is made of superconducting materials.
Specifically, the inductance of the first test structure 1, denoted as first inductance L, was measured using SQUID flux-voltage modulation techniquea。
More specifically, as shown in FIG. 5, a control current I is applied to two ends of the first test structure 1ctlA flux phi L generated in the SQUID devicea×Ictl(ii) a Applying a DC bias current I in the first and second Josephson junctions 52, 53bBased on SQUID characteristic, its output voltage is the periodic function of its magnetic flux phi, and the period is one magnetic flux quantum phi 0-2.07 × 10-15Wb; varying the control current IctlThe magnetic flux phi generated in the SQUID device can be adjusted to control the current IctlThe variation amount of (b) corresponds to an integral multiple k Φ 0 of one magnetic flux quantum; based on the control current IctlChange amount Δ I ofctlCalculating the relation of the inductance and the integral multiple k phi 0 of a magnetic flux quantum to obtain the value (k phi 0/delta I)ctlK is an integer), and at the same time, the first inductance LaThe following relationship is satisfied:
La＝L1+n·Lp；
wherein, LaIs a first inductor，L1The inductance of the wire between the first and second josephson junctions 52, 53 in the first test structure 1, n being the number of josephson junctions in the first josephson junction array 11, LpIs the parasitic inductance of a single josephson junction.
As shown in fig. 3 and 6, a second test structure 2 is provided to obtain a second inductor L through testingb。
In particular, the second test structure 2 is located in the SQUID device, the second test structure 2 comprising a second josephson junction array 21 and a wire connecting the second josephson junction array 21 in series between the first josephson junction 52 and the second josephson junction 53, the length of the second test structure 2 being set to d. The second josephson junction array 21 is formed on the substrate 51, and the second josephson junction array 21 includes m josephson junctions connected in series in sequence, where m is an odd number, and preferably, m is an odd number not less than 10, and is set to 5 in this embodiment for convenience of illustration. Each josephson junction comprises a bottom electrode, a top electrode and an insulating material layer (the bottom electrode and the top electrode are made of superconducting materials) between the bottom electrode and the top electrode, the josephson junctions are sequentially connected in series through the bottom electrode and the top electrode, in the embodiment, the bottom electrode of each josephson junction is connected through a lower layer lead, the top electrode of each josephson junction is connected through an upper layer lead, the lower layer lead and the bottom electrode of each josephson junction are positioned on the same plane (the upper surface and the lower surface are flush, the thickness is equal), and the lower layer lead and the upper layer lead are made of superconducting materials the same as the bottom electrode and the top electrode of the josephson junction. As shown in fig. 6, a bottom electrode of a first josephson junction in the second josephson junction array 21 is connected to a bottom electrode of the first josephson junction 52 through a lower layer wire, a top electrode of the first josephson junction is connected to a top electrode of a second josephson junction through an upper layer wire, and sequentially connected end to end, and a top electrode of a fifth josephson junction is connected to a bottom electrode of the second josephson junction 53 through an upper layer wire, a conductive structure and a lower layer wire, so as to realize series connection, wherein the conductive structure is made of a superconducting material.
The lower layer wire may be disposed under the bottom electrode of each josephson junction, and may be made of a superconducting material. The upper layer wire is not lower than the top electrode of each josephson junction, and in the embodiment, the upper layer wire is arranged on the top electrode of each josephson junction and is made of superconducting materials.
Specifically, the inductance of the second test structure 2, denoted as second inductance L, was measured using SQUID flux-voltage modulation techniqueb。
More specifically, the method for measuring the inductance of the second test structure 2 is not repeated herein, and refer to the method for measuring the inductance of the first test structure 1, the second inductance LbThe following relationship is satisfied:
Lb＝L2+m·Lp；
wherein, LbIs a second inductance, L2The inductance of the wire between the first and second josephson junctions 52, 53 in the second test structure 2, m being the number of josephson junctions in the second josephson junction array 21, LpIs the parasitic inductance of a single josephson junction.
As shown in fig. 3 and 7, a third test structure 3 is provided to obtain a third inductor L through the testc。
Specifically, the third test structure 3 is located in the SQUID device, the third test structure 3 includes a first wire connected between bottom electrodes of the first and second josephson junctions 52 and 53, the first wire is located at the same plane as a lower wire of the first and second test structures 1 and 2 connecting in series each josephson junction, the material is the same as the lower wire, and the length is set as d. In the present embodiment, the first conductive line is located on the substrate 51, and has the same thickness and material as the bottom electrode of each josephson junction. As shown in fig. 7, one end of the first wire is connected to the bottom electrode of the first josephson junction 52, and the other end of the first wire is connected to the bottom electrode of the second josephson junction 53.
Specifically, SQUID flux-voltage modulation technique is used for measurementThe inductance of the third test structure 3, denoted as third inductance Lc。
More specifically, the method for measuring the inductance of the third test structure 3 is not repeated herein, and refer to the method for measuring the inductance of the first test structure 1, the third inductance LcThe following relationship is satisfied:
Lc＝L3；
wherein, LcIs a third inductance, L3Is the inductance of the first conductor.
As shown in fig. 3 and 8, a fourth test structure 4 is provided to obtain a fourth inductor L through the testd。
Specifically, the fourth test structure 4 is located in the SQUID device, the fourth test structure 4 includes a second wire connected between bottom electrodes of the first josephson junction 52 and the second josephson junction 53, the second wire is located at the same plane as an upper wire of the first test structure 1 and the second test structure 2 connecting in series each josephson junction, and the material of the second wire is the same as that of the upper wire. As shown in fig. 8, one end of the second conducting wire is connected to the bottom electrode of the first josephson junction 52 sequentially through the conducting structure and the lower layer conducting wire, the other end of the second conducting wire is connected to the bottom electrode of the second josephson junction 53 sequentially through the conducting structure and the lower layer conducting wire, and the length of the second conducting wire is equal to the distance between the left end of the top electrode of the first josephson junction in the second test structure 2 and the right end of the upper layer conducting wire.
Specifically, the inductance of the fourth test structure 4, denoted as fourth inductance L, is measured using SQUID flux-voltage modulation techniquesd。
More specifically, the method for measuring the inductance of the fourth test structure 4 is not repeated herein, and refer to the method for measuring the inductance of the first test structure 1, the fourth inductance LdThe following relationship is satisfied:
Ld＝L4；
wherein, LdIs a fourth inductance, L4Is the inductance of the second conductor.
It should be noted that, the order of the steps of obtaining the first inductor, the second inductor, the third inductor, and the fourth inductor is not limited, and is not limited to this embodiment.
As shown in fig. 3, the parasitic inductance of a single josephson junction is calculated based on the fact that the sum of the inductances of the wires in the first test structure 1 and the second test structure 2 is the same as the sum of the inductances of the wires in the third test structure 3 and the fourth test structure 4.
Specifically, L is known from the patterns of the first test structure 1, the second test structure 2, the third test structure 3 and the fourth test structure 41+L2＝L3+L4Further, parasitic inductance L of a single Josephson junction can be obtainedpSatisfies the following relation:
wherein, LpParasitic inductance of a single Josephson junction, LaIs a first inductance, LbIs a second inductance, LcIs a third inductance, LdFor a fourth inductor, n is the number of josephson junctions in the first josephson junction array, and m is the number of josephson junctions in the second josephson junction array.
It should be noted that the parasitic inductance value of the josephson junction is not only related to its structure, but also related to the material from which it is made, for example, the parasitic inductance of the josephson junction made of Nb thin film is different from the parasitic inductance value of the josephson junction made of NbN thin film, so the actual parasitic inductance value of the josephson junction can be measured using the method of the present invention before designing the superconducting digital circuit.
The invention relates to a method for measuring the parasitic inductance of a Josephson junction, which adopts SQUID voltage-magnetic flux modulation technology to obtain the inductance of each test structure, and then calculates the parasitic inductance of a single Josephson junction based on the difference between the test structures.
Example two
This embodiment provides a method for fabricating each test structure in the first embodiment, wherein each test structure is first fabricated by using a micromachining process before measuring a josephson junction parasitic inductance, the method comprising:
(a) a three-layer thin film structure of a first superconducting material layer, an insulating material layer, and a second superconducting material layer is deposited on the substrate 51.
Specifically, in this embodiment, the substrate 51 is made of MgO, the first superconducting material layer and the second superconducting material layer are made of NbN, and the insulating material layer is made of AlN. In practical applications, the material may be set as required, which is not described herein in detail.
(b) And preparing a bottom electrode and a lower layer lead of the Josephson junction by using a micromachining process.
Specifically, the bottom electrodes of the first josephson junction 52, the second josephson junction 53, the first josephson junction array 11 and the second josephson junction array 21, and the lower layer wires are defined by etching the three-layer thin film structure.
(c) Josephson junctions are prepared using microfabrication processes.
Specifically, a junction region of each Josephson junction is defined by etching the insulating material layer and the second superconducting material layer.
(d) And depositing a first insulating film on the surface of the device, and forming holes on the surface of each Josephson junction and the surface of the bottom electrode so as to lead out the top electrode and the bottom electrode in the subsequent steps.
Specifically, the first insulating film is formed on the surface of the device formed in step (c), and the first insulating film is etched to expose the top and bottom electrodes of the first and second josephson junctions, wherein in this embodiment, the first insulating film is made of SiO2。
(e) Depositing a metal film and preparing the metal resistor by utilizing a micromachining process.
Specifically, a metal film is deposited on the insulating film and a metal resistor is formed by etching.
(f) And depositing a first superconducting film, and preparing a top electrode leading-out structure and an upper layer lead by utilizing a micromachining process.
Specifically, in this embodiment, the material of the first superconducting thin film is NbN.
(g) A second insulating film is deposited and an opening is made in the surface of the top electrode of the josephson junction to allow connection to the ground layer 55 in a subsequent step.
Specifically, in this embodiment, the material of the second insulating film is SiO2。
(h) And depositing a second superconducting thin film as a grounding layer, and leading out an electrode of the Josephson junction by using a micromachining process.
Specifically, in this embodiment, the second superconducting thin film is made of NbN.
In summary, the present invention provides a method for measuring a josephson junction parasitic inductance, including: providing a first test structure, wherein the first test structure comprises a first Josephson junction array connected in series between a first Josephson junction and a second Josephson junction, one end of the first Josephson junction array is grounded, the first Josephson junction array comprises an even number of sequentially connected Josephson junctions, and the inductance between the first Josephson junction and the second Josephson junction is measured to obtain a first inductance; providing a second test structure comprising a second josephson junction array in series between the first and second josephson junctions, the second josephson junction array comprising an odd number of sequentially series connected josephson junctions, measuring an inductance between the first and second josephson junctions, resulting in a second inductance; providing a third test structure comprising a first wire in series between the first and second josephson junctions, the first wire being in the same plane as the underlying wire in series with each josephson junction, measuring the inductance between the first and second josephson junctions, resulting in a third inductance; providing a fourth test structure, wherein the fourth test structure comprises a second lead connected in series between the first Josephson junction and the second Josephson junction, the second lead and an upper lead connected in series with each Josephson junction are located on the same plane, and measuring inductance between the first Josephson junction and the second Josephson junction to obtain a fourth inductance; and calculating to obtain the parasitic inductance of the single Josephson junction based on the condition that the sum of the inductances of the wires in the first test structure and the second test structure is the same as the sum of the inductances of the wires in the third test structure and the fourth test structure. The invention relates to a method for measuring the parasitic inductance of a Josephson junction, which adopts SQUID voltage-magnetic flux modulation technology to obtain the inductance of each test structure, and then calculates the parasitic inductance of a single Josephson junction based on the difference between the test structures. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (6)
1. A method for measuring a Josephson junction parasitic inductance, the method comprising:
providing a first test structure, wherein the first test structure comprises a first Josephson junction array connected in series between a first Josephson junction and a second Josephson junction, one end of the first Josephson junction array is grounded, the first Josephson junction array comprises an even number of sequentially connected Josephson junctions, and the inductance between the first Josephson junction and the second Josephson junction is measured to obtain a first inductance;
providing a second test structure comprising a second josephson junction array in series between the first and second josephson junctions, the second josephson junction array comprising an odd number of sequentially series connected josephson junctions, measuring an inductance between the first and second josephson junctions, resulting in a second inductance;
providing a third test structure comprising a first wire in series between the first and second josephson junctions, the first wire being in the same plane as the underlying wire in series with each josephson junction, measuring the inductance between the first and second josephson junctions, resulting in a third inductance;
providing a fourth test structure, wherein the fourth test structure comprises a second lead connected in series between the first Josephson junction and the second Josephson junction, the second lead and an upper lead connected in series with each Josephson junction are located on the same plane, and measuring inductance between the first Josephson junction and the second Josephson junction to obtain a fourth inductance;
calculating parasitic inductance of a single Josephson junction based on the fact that the sum of the inductances of the wires in the first test structure and the second test structure is the same as the sum of the inductances of the wires in the third test structure and the fourth test structure, wherein the parasitic inductance of the single Josephson junction satisfies the following relational expression:
wherein, LpParasitic inductance of a single Josephson junction, LaIs a first inductance, LbIs a second inductance, LcIs a third inductance, LdFor a fourth inductor, n is the number of josephson junctions in the first josephson junction array, and m is the number of josephson junctions in the second josephson junction array.
2. The method of measuring josephson junction parasitic inductance according to claim 1, wherein: the lower layer lead of each Josephson junction in series is positioned on the same plane as the bottom electrode of each Josephson junction.
3. The method of measuring the parasitic inductance of a Josephson junction according to any one of claims 1 to 2, wherein: the wire is made of superconducting materials.
4. The method of measuring josephson junction parasitic inductance according to claim 1, wherein: methods of measuring each inductance include SQUID flux-voltage modulation techniques.
5. The method of measuring the josephson junction parasitic inductance of claim 4, wherein: the SQUID flux-voltage modulation technique includes:
applying a control current to both ends of each test structure, and applying a DC bias current in the first and second Josephson junctions;
adjusting the control current such that a variation of the control current corresponds to an integer multiple of one flux quantum;
and obtaining the value of each inductor based on the relation between the variation of the control current and the integral multiple of one magnetic flux quantum.
6. The method of measuring josephson junction parasitic inductance according to claim 1, wherein: the number of josephson junctions in the first and second josephson junction arrays is greater than 10.
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