CN110120395A - Array substrate and display panel - Google Patents
Array substrate and display panel Download PDFInfo
- Publication number
- CN110120395A CN110120395A CN201910421497.7A CN201910421497A CN110120395A CN 110120395 A CN110120395 A CN 110120395A CN 201910421497 A CN201910421497 A CN 201910421497A CN 110120395 A CN110120395 A CN 110120395A
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- China
- Prior art keywords
- metal
- vss
- metal layer
- metal block
- array substrate
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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- 239000000758 substrate Substances 0.000 title claims abstract description 38
- 239000002184 metal Substances 0.000 claims abstract description 125
- 229910052751 metal Inorganic materials 0.000 claims abstract description 125
- 238000003491 array Methods 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 150000002739 metals Chemical class 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 230000000694 effects Effects 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Cathode-Ray Tubes And Fluorescent Screens For Display (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention provides a kind of array substrate and display panel, which includes: substrate；The first metal layer, the first metal layer include the cathode line of a plurality of parallel interval setting, and the cathode line extends along X-direction；First insulating layer is set on the first metal layer；Second metal layer, it is set on first insulating layer, the second metal layer includes VSS metal block, the VSS metal block include a first VSS metal block extended along Y direction and it is multiple connect with the first VSS metal block and spaced 2nd VSS metal block, each 2nd VSS metal block is in the gap projected between adjacent two articles of cathode lines on the first metal layer.The present invention is staggered by using by the 2nd VSS metal block of VSS metal block with cathode line, to realize the positive area for reducing the first metal layer and second metal layer, display effect can be improved to avoid due to the first metal layer and the breakdown caused short circuit of second metal layer.
Description
Technical field
The present invention relates to field of display technology, and in particular to a kind of array substrate and display panel.
Background technique
In prior art designs in order to increase the overlapping area of cathode line Yu VSS metal, overlap joint is increased except the area VSS and is expanded
Exhibition section.But it is found in processing procedure, it, can be because of electrostatic problem since the region is there are the M2 metal layer of large area is Chong Die with M1 metal layer
Cause M1 metal layer and M2 metal layer to puncture and causes short circuit.Influence display effect.
Therefore, the prior art is defective, needs to improve.
Summary of the invention
The present invention provides a kind of array substrate and display panel, can be breakdown to avoid the first metal layer and second metal layer
Display quality can be improved in caused short circuit.
The present invention provides a kind of array substrates, comprising:
Substrate；
The first metal layer, the first metal layer include the cathode line of a plurality of parallel interval setting, and the cathode line is along X
Axis direction extends；
First insulating layer is set on the first metal layer；
Second metal layer is set on first insulating layer, and the second metal layer includes VSS metal block, described
VSS metal block includes a first VSS metal block extended along Y direction and multiple connect with the first VSS metal block
And spaced 2nd VSS metal block, projection of each 2nd VSS metal block on the first metal layer are located at phase
In gap between adjacent two cathode lines.
In array substrate of the present invention, further includes:
Second insulating layer is set in the second metal layer；
Third metal layer is set in the second insulating layer, and the third metal layer includes mutually isolated pixel
Electrode district and overlap joint metal area, the overlap joint metallic region are located above the 2nd VSS metal block, the overlap joint metal area
Domain is electrically connected by least one plated through-hole through the second insulating layer with the 2nd VSS metal block.
In array substrate of the present invention, projection of the Y-axis on the first metal layer and the X-axis are hung down
Directly, the 2nd VSS metal block extends along the direction for being parallel to the X-axis.
In array substrate of the present invention, the 2nd VSS metal block is in rectangular strip.
In array substrate of the present invention, region between any adjacent two cathode line is with one described second
VSS metal block is opposite.
In array substrate of the present invention, the substrate includes display area and non-display area, the pixel
Electrode district is located at right above the display area, and the overlap joint metal area is located above the non-display area.
In array substrate of the present invention, the overlap joint metal area is rectangular, and its length direction and the Y-axis
In parallel.
In array substrate of the present invention, the first metal layer include further include a plurality of grid metal lines and a plurality of
Data signal line, a plurality of grid metal lines and a plurality of data signal line are located above the display area, the cathode line
Above the non-display area.
In array substrate of the present invention, at least one described plated through-hole includes multiple plated through-hole arrays, often
The one plated through-hole battle array is opposite with a 2nd VSS metal block respectively, and each plated through-hole battle array, which includes multiple, is in
The plated through-hole of rectangular array arrangement.
A kind of display panel, which is characterized in that including array substrate described in any of the above embodiments.
The present invention is staggered by using by the 2nd VSS metal block of VSS metal block with cathode line, reduces the to realize
The positive area of one metal layer and second metal layer, can to avoid due to the first metal layer and second metal layer it is breakdown caused by
Display effect can be improved in short circuit.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of one of some embodiments of the invention array substrate.
Fig. 2 is the local overlooking structural schematic diagram of one of some embodiments of the invention array substrate.
Specific embodiment
Embodiments of the present invention are described below in detail, the example of the embodiment is shown in the accompanying drawings, wherein from beginning
Same or similar element or element with the same or similar functions are indicated to same or similar label eventually.Below by ginseng
The embodiment for examining attached drawing description is exemplary, and for explaining only the invention, and is not considered as limiting the invention.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise " is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of
The description present invention and simplified description, rather than the device or element of indication or suggestion meaning must have a particular orientation, with spy
Fixed orientation construction and operation, therefore be not considered as limiting the invention.In addition, term " first ", " second " are only used for
Purpose is described, relative importance is not understood to indicate or imply or implicitly indicates the quantity of indicated technical characteristic.
" first " is defined as a result, the feature of " second " can explicitly or implicitly include one or more feature.?
In description of the invention, the meaning of " plurality " is two or more, unless otherwise specifically defined.
It is a kind of structure of one of some embodiments of the invention array substrate please refer to Fig. 1 and Fig. 2, Fig. 1
Schematic diagram.Fig. 2 is the local overlooking structural schematic diagram of one of some embodiments of the invention array substrate.In the present embodiment
In, which includes: substrate 10, the first metal layer 20, the first insulating layer 30, second metal layer 40, second insulating layer 50
And third metal layer 60.
Wherein, in some embodiments, which is glass substrate comprising display area 11 and non-display area
12。
Wherein, in some embodiments, which includes the cathode line 21 of a plurality of parallel interval setting, described
Cathode line 21 extends along X-direction.A plurality of 21 uniform intervals of the cathode line setting.Cathode line 21 is located at the non-display area 12
Top.The first metal layer 20 further includes a plurality of grid metal lines 21 and a plurality of data signal line 22, a plurality of grid metal lines 21
It is located above the display area with a plurality of data-signal 22.
Wherein, in some embodiments, which is set on the first metal layer 20；First insulating layer
30 are formed using silicon nitride or precipitation of silica.
Wherein, in some embodiments, which is set on first insulating layer 30.Second gold medal
Belonging to layer 40 includes VSS metal block 41, and the VSS metal block 41 includes a first VSS metal block 411 extended along Y direction
And it is multiple connect with the first VSS metal block 411 and spaced 2nd VSS metal block 412, each described second
VSS metal block 412 is in the projection on the first metal layer 20 in the gap between adjacent two cathode lines 21.This second
Metal layer 40 further includes the function metal layer 42 for being used to form pixel function.Function metal layer 42 is set on the display area 11
Side.Wherein, which can be set source metal, drain metal or signal wire.
Wherein, in some embodiments, which is set in the second metal layer 40；Using silicon nitride
Or precipitation of silica is formed.
Wherein, in some embodiments, which is set in the second insulating layer 50, the third gold
Belonging to floor 50 includes mutually isolated pixel electrode area 62 and overlap joint metal area 61, and the overlap joint metallic region 61 is positioned at described the
Two VSS metal blocks, 412 top, overlap joint 61 domain of metal area pass through at least one plated through-hole through the second insulating layer
51 are electrically connected with the 2nd VSS metal block 412.Pixel electrode area is located at right above the display area, the overlap joint metal
Area is located above the non-display area.Wherein, which includes multiple plated through-hole arrays, each described
Plated through-hole battle array is opposite with a 2nd VSS metal block respectively, and each plated through-hole battle array includes multiple in rectangle battle array
Arrange the plated through-hole of arrangement.
Wherein, pixel electrode area 62 is provided with the pixel electrode of multiple array arrangements, does not describe excessively for the prior art.
Wherein, in some embodiments, projection of the Y-axis on the first metal layer 20 is vertical with the X-axis, described
2nd VSS metal block 412 extends along the direction for being parallel to the X-axis.2nd VSS metal block is in rectangular strip.
Wherein, in some embodiments, the region between any adjacent two cathode line 21 is at most with one described second
VSS metal block 412 is opposite.
In array substrate of the present invention, the overlap joint metal area is rectangular, and its length direction and the Y-axis
In parallel.
The present invention is staggered by using by the 2nd VSS metal block of VSS metal block with cathode line, reduces the to realize
The positive area of one metal layer and second metal layer, can to avoid due to the first metal layer and second metal layer it is breakdown caused by
Display effect can be improved in short circuit.
The present invention also provides a kind of display panels comprising array substrate described in above-mentioned any embodiment.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
1. a kind of array substrate characterized by comprising
Substrate；
The first metal layer, the first metal layer include the cathode line of a plurality of parallel interval setting, and the cathode line is along X-axis side
To extension；
First insulating layer is set on the first metal layer；
Second metal layer is set on first insulating layer, and the second metal layer includes VSS metal block, the VSS gold
Belong to block to include a first VSS metal block extended along Y direction and multiple connect and be spaced with the first VSS metal block
The 2nd VSS metal block being arranged, projection of each 2nd VSS metal block on the first metal layer are located at adjacent two articles
In gap between cathode line.
2. array substrate according to claim 1, which is characterized in that further include:
Second insulating layer is set in the second metal layer；
Third metal layer is set in the second insulating layer, and the third metal layer includes mutually isolated pixel electrode
Area and overlap joint metal area, the overlap joint metallic region are located above the 2nd VSS metal block, and the overlap joint metallic region is logical
At least one plated through-hole crossed through the second insulating layer is electrically connected with the 2nd VSS metal block.
3. array substrate according to claim 2, which is characterized in that projection of the Y-axis on the first metal layer
Vertical with the X-axis, the 2nd VSS metal block extends along the direction for being parallel to the X-axis.
4. array substrate according to claim 3, which is characterized in that the 2nd VSS metal block is in rectangular strip.
5. array substrate according to claim 4, which is characterized in that region between any adjacent two cathode line with
One the 2nd VSS metal block is opposite.
6. array substrate according to claim 2, which is characterized in that the substrate includes display area and non-display area
Domain, the pixel electrode area are located at right above the display area, and the overlap joint metal area is located above the non-display area.
7. array substrate according to claim 6, which is characterized in that the overlap joint metal area is rectangular, and its length
Direction is parallel with the Y-axis.
8. array substrate according to claim 6, which is characterized in that the first metal layer is including further including a plurality of grid
Metal wire and a plurality of data signal line, a plurality of grid metal lines and a plurality of data signal line are located on the display area
Side, the cathode line are located above the non-display area.
9. array substrate according to claim 6, which is characterized in that at least one described plated through-hole includes multiple metals
Change hole array, each plated through-hole battle array is opposite with a 2nd VSS metal block respectively, each plated through-hole battle array
Plated through-hole including the arrangement of multiple rectangular arrays.
10. a kind of display panel, which is characterized in that including the described in any item array substrates of claim 1-9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910421497.7A CN110120395B (en) | 2019-05-21 | 2019-05-21 | Array substrate and display panel |
| PCT/CN2019/105203 WO2020232916A1 (en) | 2019-05-21 | 2019-09-10 | Array substrate and display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910421497.7A CN110120395B (en) | 2019-05-21 | 2019-05-21 | Array substrate and display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110120395A true CN110120395A (en) | 2019-08-13 |
| CN110120395B CN110120395B (en) | 2021-07-23 |
Family
ID=67522952
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910421497.7A Active CN110120395B (en) | 2019-05-21 | 2019-05-21 | Array substrate and display panel |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110120395B (en) |
| WO (1) | WO2020232916A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111524906A (en) * | 2020-04-26 | 2020-08-11 | 深圳市华星光电半导体显示技术有限公司 | Conductive assembly and display device |
| WO2020232916A1 (en) * | 2019-05-21 | 2020-11-26 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN113406831A (en) * | 2021-06-21 | 2021-09-17 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1690779A (en) * | 2004-04-20 | 2005-11-02 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| CN105633297A (en) * | 2014-11-25 | 2016-06-01 | 乐金显示有限公司 | See-through organic light emitting display device and method for manufacturing the same |
| CN105789251A (en) * | 2014-12-26 | 2016-07-20 | 昆山国显光电有限公司 | AMOLED (active matrix organic light emitting diode) display apparatus |
| CN107301843A (en) * | 2017-08-28 | 2017-10-27 | 深圳市华星光电半导体显示技术有限公司 | The power configuration structure and collocation method of top emitting AMOLED panel |
| CN108010942A (en) * | 2017-11-28 | 2018-05-08 | 武汉天马微电子有限公司 | A kind of organic electroluminescence display panel and organic light-emitting display device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017103408A (en) * | 2015-12-04 | 2017-06-08 | 株式会社ジャパンディスプレイ | Display device |
| CN108461530B (en) * | 2018-03-30 | 2021-08-06 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN109148479B (en) * | 2018-08-20 | 2020-09-08 | 武汉华星光电半导体显示技术有限公司 | Array substrate, display panel and preparation method thereof |
| CN110120395B (en) * | 2019-05-21 | 2021-07-23 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
-
2019
- 2019-05-21 CN CN201910421497.7A patent/CN110120395B/en active Active
- 2019-09-10 WO PCT/CN2019/105203 patent/WO2020232916A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1690779A (en) * | 2004-04-20 | 2005-11-02 | 精工爱普生株式会社 | Electro-optical device and electronic apparatus |
| CN105633297A (en) * | 2014-11-25 | 2016-06-01 | 乐金显示有限公司 | See-through organic light emitting display device and method for manufacturing the same |
| CN105789251A (en) * | 2014-12-26 | 2016-07-20 | 昆山国显光电有限公司 | AMOLED (active matrix organic light emitting diode) display apparatus |
| CN107301843A (en) * | 2017-08-28 | 2017-10-27 | 深圳市华星光电半导体显示技术有限公司 | The power configuration structure and collocation method of top emitting AMOLED panel |
| CN108010942A (en) * | 2017-11-28 | 2018-05-08 | 武汉天马微电子有限公司 | A kind of organic electroluminescence display panel and organic light-emitting display device |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020232916A1 (en) * | 2019-05-21 | 2020-11-26 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| CN111524906A (en) * | 2020-04-26 | 2020-08-11 | 深圳市华星光电半导体显示技术有限公司 | Conductive assembly and display device |
| CN111524906B (en) * | 2020-04-26 | 2021-04-02 | 深圳市华星光电半导体显示技术有限公司 | Conductive assembly and display device |
| WO2021217710A1 (en) * | 2020-04-26 | 2021-11-04 | 深圳市华星光电半导体显示技术有限公司 | Conductive assembly and display device |
| CN113406831A (en) * | 2021-06-21 | 2021-09-17 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| WO2022267157A1 (en) * | 2021-06-21 | 2022-12-29 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and display panel |
| US11846858B2 (en) | 2021-06-21 | 2023-12-19 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Array substrate and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020232916A1 (en) | 2020-11-26 |
| CN110120395B (en) | 2021-07-23 |
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