CN110120357B - Semiconductor wafer test structure and forming method thereof - Google Patents
Semiconductor wafer test structure and forming method thereof Download PDFInfo
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- CN110120357B CN110120357B CN201910406880.5A CN201910406880A CN110120357B CN 110120357 B CN110120357 B CN 110120357B CN 201910406880 A CN201910406880 A CN 201910406880A CN 110120357 B CN110120357 B CN 110120357B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
Abstract
A semiconductor wafer test structure and a method for forming the same, the semiconductor wafer test structure includes: a substrate; the first device layer is positioned on the substrate and is internally provided with a plurality of first pads and a plurality of first test units which are arranged along a first direction, each first test unit is electrically connected with two different first pads, and each first pad is electrically connected with two different first test units; the second device layer is positioned on the first device layer, a plurality of second gaskets and a plurality of second testing units are arranged in a second direction in the second device layer, the second direction is different from the first direction, each second testing unit is electrically connected with two different second gaskets, and each second gasket is electrically connected with two different second testing units; and the third gaskets are positioned in the second device layer and are connected with the first gaskets in a one-to-one correspondence mode. The occupied area of the semiconductor wafer test structure is small, and the space utilization rate of a semiconductor device is improved.
Description
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor wafer test structure and a forming method thereof.
Background
In semiconductor integrated circuit layout design and manufacturing processes, test structures are often required to verify the quality of the design and manufacturing processes.
In the field of integrated circuit manufacturing, test structures are microelectronic structures produced under the same process as the production of the product. Data information required for integrated circuit process control and improvement is obtained from measurements of test structures. All devices to be tested and bonding pads in the existing test structure are designed and manufactured on the same layer, along with the compression of manufacturing cost, a specific area is not reserved in the chip manufacturing process for placing the test structure, the test structure is placed in a cutting channel area or a vacant place in a chip, and the existing test structure occupies a large area, so that few devices to be tested in the test structure are tested.
Therefore, it is one of the problems to be solved by those skilled in the art how to implement various tests as much as possible under the condition of limited scribe line area, reduce the test cost, and improve the utilization rate of the wafer.
Disclosure of Invention
The invention provides a semiconductor wafer test structure and a forming method thereof, which are used for improving the space utilization rate of a semiconductor wafer.
To solve the above technical problem, the present invention provides a semiconductor wafer testing structure, comprising: the device comprises a substrate and a first device layer positioned on the substrate, wherein the first device layer is internally provided with a plurality of first gaskets and a plurality of first test units which are arranged along a first direction, each first test unit is electrically connected with two different first gaskets, and each first gasket is electrically connected with two different first test units; the second device layer is positioned on the first device layer, a plurality of second gaskets and a plurality of second testing units are arranged in a second direction in the second device layer, the second direction is different from the first direction, each second testing unit is electrically connected with two different second gaskets, and each second gasket is electrically connected with two different second testing units; and the third gaskets are arranged along the first direction and are connected with the first gaskets in a one-to-one correspondence mode.
Optionally, the method further includes: the third device layer is positioned on the second device layer, a plurality of fourth gaskets and a plurality of third testing units are arranged in the third device layer along a third direction, the third direction is different from the first direction, the third direction is different from the second direction, each third testing unit is electrically connected with two different fourth gaskets, each fourth gasket is electrically connected with two different third testing units, a fifth gasket and a sixth gasket are further arranged in the third device layer, the fourth gaskets are connected with the second gaskets, and the sixth gaskets are connected with the first gaskets.
Optionally, a projection of the fourth pad on the first device layer is a third projection, a projection of the fifth pad on the first device layer is a fourth projection, a projection of the sixth pad on the first device layer is a fifth projection, and the third projection, the fourth projection, and the fifth projection are partially overlapped or completely overlapped.
Optionally, the third projection and the fourth projection partially overlap or completely overlap, the fourth projection and the fifth projection partially overlap or completely overlap, the third projection and the fifth projection partially overlap or completely overlap, or the third projection, the fourth projection and the fifth projection overlap.
Optionally, a projection of the second pad on the first device layer is a first projection, a projection of the third pad on the first device layer is a second projection, and the first projection and the second projection overlap.
Optionally, the first projection overlaps the first pad.
Optionally, the second pad and the first pad are electrically connected by a plug.
Optionally, in the first direction, one first test unit is located between two adjacent first pads.
Optionally, in the first direction, one first test unit is electrically connected to two adjacent first pads, and the first pad is electrically connected to one adjacent first test unit or two adjacent first test units.
Optionally, in the second direction, one second test unit is located between two adjacent second pads.
Optionally, in the second direction, one second test unit is electrically connected to two adjacent second pads, and the second pad is electrically connected to one adjacent second test unit or two adjacent second test units.
Optionally, the second testing unit is located above the first testing unit in a direction perpendicular to the substrate surface, and a projection of the second testing unit on the first device layer overlaps with a position of the first testing unit on the first device layer.
Optionally, the plurality of first pads in the first device layer are arranged in an array, the plurality of first pads are formed into a first pad array, and the first pad array includes: a plurality of first pads of N rows by M columns, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 2.
Optionally, a plurality of first test units in the first device layer are arranged in an array, the plurality of first test units form a first test array, and the first test array includes: (N-1) rows by M columns of first test cells.
Optionally, the plurality of second test units in the second device layer are arranged in an array, the plurality of second test units form a second test array, and the second test array includes a plurality of second test units in N rows and x (M-1) columns.
Optionally, the first test unit includes: resistors, capacitors, inductors, gate structures, interconnect lines, or logic function devices; the second test unit includes: resistors, capacitors, inductors, gate structures, interconnect lines, or logic function devices.
Optionally, the substrate comprises: the test device comprises a test area, a first device area and a second device area, wherein the plurality of first test units are positioned in a first device layer of the test area; the plurality of second test units are positioned in the second device layer of the test area; further comprising: a first device in the first device layer of the first device region; a second device within the second device layer in the second device region.
Optionally, the first test unit and the first device have the same structure.
Optionally, the second testing unit and the second device have the same structure.
The invention also provides a method for forming the semiconductor wafer test structure, which comprises the following steps: providing a substrate; forming a first device layer on the substrate, wherein the first device layer is internally provided with a plurality of first pads and a plurality of first test units which are arranged along a first direction, each first test unit is electrically connected with two different first pads, and each first pad is electrically connected with two different first test units; forming a second device layer on the first device layer, wherein the second device layer is internally provided with a plurality of second pads and a plurality of second test units which are arranged along a second direction, the second direction is different from the first direction, each second test unit is electrically connected with two different second pads, and each second pad is electrically connected with two different second test units; and forming third gaskets in the second device layer, wherein the third gaskets are arranged along the first direction, and the third gaskets are correspondingly connected with the first gaskets one to one.
Optionally, the substrate includes a test region, a first device region and a second device region, and the plurality of first test units are located in a first device layer of the test region; the plurality of second test units are positioned on a second device layer of the test area; further comprising: forming a first device in the first device region and in the first device layer; a second device is formed within the second device layer in the second device region.
Optionally, the first test unit and the first device have the same structure.
Optionally, the second testing unit and the second device have the same structure.
Optionally, in the process of forming the first test unit, the first device is formed.
Optionally, in the process of forming the second test unit, a second device is formed.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the semiconductor wafer test structure provided by the technical scheme of the invention, the first test unit is positioned on the first device layer, and the first test unit is conducted through the two first gaskets in the first direction to form the only test channel. The third pads are located on the second device layer, and the first pads are connected with the third pads in a one-to-one correspondence manner, so that the test channels of the first test unit can be obtained through the third pads distributed along the first direction in the second device layer. The second testing unit is located on the second device layer, and the second testing unit is conducted through the two second gaskets in the second direction to form a unique testing channel. The first test unit and the second test unit are in complementary interference during testing. The number of test structures contained per unit area of the substrate is the sum of the number of first test cells that can be contained in the first device layer and the number of second test cells that can be contained in the second device layer, and therefore the number of test structures contained per unit area of the substrate is increased. Therefore, the number of test structures that can be accommodated in the same area of the scribe line region or the vacant region increases.
Further, in the first direction, the one first test unit is located between two adjacent first pads. In the second direction, the one second test unit is located between two adjacent second pads. The utilization rate of the effective area of the semiconductor wafer is improved, and the wiring is more convenient, so that the utilization rate of the semiconductor wafer is improved.
Furthermore, the projections of the second pad and the third pad are overlapped, so that the area occupied by the semiconductor wafer test structure is further reduced, and the utilization rate of the effective area of the semiconductor wafer is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor wafer test structure formation process;
FIGS. 2-5 are schematic structural views of a semiconductor wafer test structure according to an embodiment of the invention;
FIGS. 6-8 are schematic structural views of a semiconductor wafer test structure according to another embodiment of the present invention;
fig. 9 to 13 are schematic structural views illustrating a method for forming a semiconductor wafer test structure according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of prior art semiconductor wafer test structures is poor.
FIG. 1 is a schematic diagram of a semiconductor wafer test structure.
A semiconductor wafer test structure, referring to fig. 1, comprising: a semiconductor substrate; a pad array on the semiconductor substrate, the pad array including a plurality of pads in N rows by M columns, M being an integer greater than or equal to 2, N being an integer greater than or equal to 2; the test array is positioned on the semiconductor substrate and comprises a plurality of test units in Q rows multiplied by R columns, Q is an integer which is greater than or equal to 1 and less than N, and R is an integer which is greater than or equal to 1 and less than M; in the row direction of the pad array, each test unit is electrically connected with two different pads, and each pad is electrically connected with one test unit or two different test units.
In the above embodiments, a test unit needs to have at least two ends connected to two different pads respectively to form a complete test loop. In order to improve the effective area utilization rate and the wiring convenience of the semiconductor wafer, two adjacent test units can share one pad, namely n pads can contain n-1 test units at most. Then the test array of N rows x (M-1) columns can be accommodated maximally for an array of N rows x M columns of pads. When the test unit of the ith row and the jth column is to be measured (i is an integer which is greater than or equal to 1 and less than or equal to N, j is an integer which is greater than or equal to 1 and less than or equal to M < -1 >), the pad of the ith row and the jth column and the pad of the ith row and the jth +1 column are conducted, and a test path which is unique to the test unit of the ith row and the jth column is formed. The semiconductor wafer test structures in the above embodiments are located in the scribe line region of the semiconductor wafer or the free region of the semiconductor wafer, however, the scribe line region of the semiconductor wafer or the free region of the semiconductor wafer is limited, and the area occupied by the test structures needs to be reduced for the test structures with more capacity. However, the area of the test structures in the above embodiments is difficult to be reduced, resulting in a smaller number of test structures for the capacity of the semiconductor wafer.
The invention provides a semiconductor wafer test structure, comprising: a substrate; the first device layer is positioned on the substrate and is internally provided with a plurality of first pads and a plurality of first test units which are arranged along a first direction; and the second device layer is positioned on the first device layer and is internally provided with a plurality of second gaskets and a plurality of second test units which are arranged along a second direction. In the first direction, each first test unit is electrically connected with two different first pads, and each first pad is electrically connected with one first test unit or two different first test units; in the second direction, each second test unit is electrically connected with two different second pads, and each second pad is electrically connected with one second test unit or two different second test units. Because the selection mode of the pads of the first device layer is different from that of the pads of the second device layer, the first test unit and the second test unit can work independently to complement interference. The second device layer is located above the first device layer, and thus the number of test structures accommodated per unit area increases. The number of the test structures which can be accommodated in the cutting path area or the spare area with the same area is large, so that the utilization rate of the semiconductor wafer is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 5 are schematic structural views of a semiconductor wafer test structure according to an embodiment of the invention.
Referring to fig. 2 to 5, fig. 2 is a top view of the semiconductor wafer test structure along the Z direction in fig. 3, fig. 3 is a schematic cross-sectional structure of a cut line B-B1 in fig. 2, fig. 4 is a schematic cross-sectional structure of a cut line a-a1 in fig. 2, and fig. 5 is a schematic cross-sectional structure of a cut line C-C1 in fig. 4, including: the test device comprises a substrate 200 and a first device layer 201 positioned on the substrate 200, wherein the first device layer 201 is internally provided with a plurality of first pads 210 and a plurality of first test units 220 which are arranged along a first direction X, each first test unit 220 is electrically connected with two different first pads 210, and each first pad 210 is electrically connected with two different first test units 220; a second device layer 202 located on the first device layer 201, wherein the second device layer 202 has a plurality of second pads 230 and a plurality of second test units 240 arranged along a second direction Y, the second direction Y is different from the first direction X, each second test unit 240 is electrically connected to two different second pads 230, and each second pad 230 is electrically connected to two different second test units 240; and third pads on the second device layer 202, the third pads being arranged along the first direction, the third pads being connected to the first pads 310 in a one-to-one correspondence.
In this embodiment, the substrate 200 includes: a test region I, a first device region II and a second device region III.
In this embodiment, the first testing units 220 are located in the first device layer 201 of the testing region I.
In this embodiment, the second testing units 240 are located in the second device layer 202 of the testing area I.
In the present embodiment, in the first direction, the one first test unit 220 is located between two adjacent first pads 210. In other embodiments, the one first test unit is not located between two adjacent first pads.
The one first test unit 220 is located between two adjacent first pads 210, and the wiring is convenient.
The first test units 210 are used for testing logic devices formed in the first device layer 201 formed on the substrate 200 by front end of line (FEOL).
In one embodiment, the first testing units are tests of logic devices formed in the first device layer 201 formed in the substrate 200 by middle-end of layout.
In this embodiment, in the first direction X, one first test unit 220 is electrically connected to two adjacent first pads 210, and the first pads 210 are electrically connected to one adjacent first test unit 220 or two adjacent first test units 220.
The first test unit 220 includes: resistors, capacitors, inductors, gate structures, interconnect lines, or logic function devices.
The test items of the first test unit 220 include: resistance testing, capacitance testing, inductance testing, or other logic function testing.
A first test unit 220 needs to be connected to two different first pads 210 at least at two ends to form a complete test loop, and two adjacent first test units 220 share one first pad 210, so that the area can be saved. Is favorable for the utilization rate of the effective area of the semiconductor wafer. The semiconductor wafer testing structure is positioned in a cutting channel area or a vacant area of the semiconductor wafer, so that the utilization rate of the semiconductor wafer is improved.
In the present embodiment, in the second direction, the one second test unit 240 is located between two adjacent second pads 230. In other embodiments, the one second test unit is not located between two adjacent second pads.
The one second test unit 240 is located between two adjacent second pads 230, and the wiring is convenient.
The second test units 240 are used for testing logic devices formed in the second device layer 202 through a middle-end of line (MEOL), for example, related logic tests of gate structures or source/drain doped regions formed in the second device layer.
In an embodiment, the first test units are used for testing a conductive via structure and a metal interconnection structure formed in the second device layer by back-end of line (BEOL).
In this embodiment, in the second direction Y, one second test unit 240 is electrically connected to two adjacent second pads 230, and the second pads 230 are electrically connected to one adjacent second test unit 240 or two adjacent second test units 240.
The second test unit 240 includes: resistors, capacitors, inductors, gate structures, interconnect lines, or logic function devices.
The test items of the second test unit 240 include: resistance testing, capacitance testing, inductance testing, or other logic function testing.
At least two ends of one second testing unit 240 are respectively connected to two different second pads 230 to form a complete testing loop, and two adjacent second testing units 240 share one second pad 230, so that the area can be saved. Is favorable for the utilization rate of the effective area of the semiconductor wafer. The semiconductor wafer testing structure is positioned in a cutting channel area or a vacant area of the semiconductor wafer, so that the utilization rate of the semiconductor wafer is improved.
In this embodiment, a projection of the second pad 230 on the first device layer 201 is a first projection, a projection of the third pad on the first device layer 201 is a second projection, and the first projection and the second projection overlap. In other embodiments, the first projection and the second projection do not overlap.
The projections of the second pad 230 and the third pad are overlapped, so that the area occupied by the semiconductor wafer test structure is reduced, and the utilization rate of the effective area of the semiconductor wafer is improved.
In this embodiment, the first projection overlaps the first pad 210. In other embodiments, the first projection does not overlap the first pad.
The first projection overlaps the first pad 210, i.e., the second pad 230 is connected to the first pad 210 in a direction perpendicular to the surface of the substrate 200.
In this embodiment, the second gasket 230 and the first gasket 210 are connected by a plug 250.
The first projection overlaps the first pad 210, and the area occupied by the semiconductor wafer test structure is further reduced, so that the utilization rate of the effective area of the semiconductor wafer is improved.
In this embodiment, the plurality of first pads 210 in the first device layer 201 are arranged in an array, the plurality of first pads 210 are formed as a first substrate array, and the first pad array includes: a plurality of first pads 210 of N rows by M columns, M being an integer equal to or greater than 2, and N being an integer equal to or greater than 2.
When the first direction X is a row direction of a first pad array, the plurality of first test units 220 in the first device layer 201 are arranged in an array, the plurality of first test units 220 are formed as a first test array, and the first test array includes: n rows by (M-1) columns of first test cells 220.
In this embodiment, the second pad 230 is located above the first pad 210 in a direction perpendicular to the surface of the substrate 200. The second pads 230 are also arranged in an array.
When the second direction Y is a column direction of the first pad array, the plurality of second test units 240 in the second device layer are arranged in an array, and the plurality of second test units 240 form a second test array, where the second test array includes: (N-1) rows by M columns of second test cells 240.
In this embodiment, the semiconductor wafer test structure further includes: a first device 221 located within the first device layer 201 of the first device region II; a second device 241 located within the second device layer 202 in the second device region III.
In this embodiment, the first testing unit 220 and the first device 221 have the same structure.
Whether the first device 221 functions normally is determined by the test result of the first test unit 220. In this embodiment, the second testing unit 240 and the second device 241 have the same structure.
Whether the second device 241 functions normally is determined by the test result of the second test unit 240.
In this embodiment, the semiconductor wafer test structure further includes: and a third device layer on the second device layer 202, wherein the third device layer has a plurality of fourth pads and a plurality of third test units arranged along a third direction, each third test unit is electrically connected with two different fourth pads, each fourth pad is electrically connected with two different third test units, the third device layer further has a fifth pad and a sixth pad, the fourth pad is connected with the second pad 230, and the sixth pad is connected with the first pad 210.
The first test unit is located on the first device layer, and the first test unit is conducted through the two first gaskets in the first direction to form a unique test channel. The sixth pads are located on the third device layer, and the first pads are connected with the sixth pads in a one-to-one correspondence manner, so that the test channels of the first test unit can be obtained through the sixth pads distributed along the first direction in the third device layer. The second testing unit is located on the second device layer, and the second testing unit is conducted through the two second gaskets in the second direction to form a unique testing channel. The fifth pads are located on the third device layer, and the second pads are connected with the fifth pads in a one-to-one correspondence manner, so that the test channels of the second test unit can be obtained through the fifth pads distributed along the second direction in the third device layer. The third testing unit is located on the third device layer, and the third testing unit is conducted through the two fourth gaskets in the third direction to form a unique testing channel. And the first test unit, the second test unit and the third test unit are subjected to complementary interference during testing. The number of the test structures contained in the unit area of the substrate is the sum of the number of the first test units capable of containing in the first device layer, the number of the second test units capable of containing in the second device layer and the number of the third test units capable of containing in the third device layer, so that the number of the test structures contained in the unit area of the substrate is further increased. Therefore, the number of test structures that can be accommodated in the same area of the scribe lane region or the vacant region is further increased.
The projection of the fourth pad on the first device layer 201 is a third projection, the projection of the fifth pad on the first device layer 201 is a fourth projection, the projection of the sixth pad on the first device layer 201 is a fifth projection, and the third projection, the fourth projection and the fifth projection are partially or completely overlapped.
In an embodiment, the third projection and the fourth projection partially overlap or completely overlap.
In another embodiment, the fourth projection overlaps the fifth projection partially or completely.
In a further embodiment, the third projection overlaps the fifth projection partially or completely.
In this embodiment, the third projection, the fourth projection, and the fifth projection overlap. The area occupied by the semiconductor wafer test structure is reduced, so that the utilization rate of the effective area of the semiconductor wafer is improved.
Fig. 6 to 8 are schematic structural views of a semiconductor wafer test structure according to another embodiment of the present invention. This embodiment differs from the previous embodiments in that the second test unit is located above the first test unit, and the projection of the second test unit on the first device layer overlaps with the position of the first test unit on the first device layer.
Referring to fig. 6 to 8, fig. 6 is a top view of the semiconductor wafer test structure along a direction Z1 in fig. 7, fig. 7 is a schematic cross-sectional structure of a cutting line S-S1 in fig. 6, and fig. 8 is a schematic cross-sectional structure of a cutting line D-D1 in fig. 7, including: the test device comprises a substrate 300 and a first device layer 301 positioned on the substrate 300, wherein the first device layer 301 is internally provided with a plurality of first pads 310 and a plurality of first test units 320 which are arranged along a first direction X, each first test unit 320 is electrically connected with two different first pads 310, and each first pad 310 is electrically connected with two different first test units 320; a second device layer 302 located on the first device layer 301, wherein the second device layer 302 has a plurality of second pads 330 and a plurality of second test units 340 arranged along a second direction Y, the second direction Y is different from the first direction X, each second test unit 340 is electrically connected to two different second pads 330, and each second pad 330 is electrically connected to two different second test units 340; and third pads on the second device layer 302, the third pads being arranged along the first direction X, the third pads being connected to the first pads 310 in a one-to-one correspondence.
The second testing unit 340 is located above the first testing unit 320 in a direction perpendicular to the surface of the substrate 300, and a projection of the second testing unit 340 on the first device layer 301 overlaps with a position of the first testing unit 320 on the first device layer 301.
The structure and location of the first test unit 320 and the first pad 310 are as described above for the first test unit 220 and the first pad 210, and are not described herein again.
The structures and positions of the second testing unit 340 and the second pad 330 are as described above for the second testing unit 240 and the second pad 230, and are not described herein again.
The embodiment also provides a method for forming the semiconductor wafer test structure. Fig. 9 to 13 are schematic structural views illustrating a method for forming a semiconductor wafer test structure according to an embodiment of the invention.
Referring to fig. 9, a substrate 300 is provided.
In this embodiment, the substrate 300 includes: a test region I, a first device region II and a second device region III.
The substrate 300 has a single-layer structure or a multi-layer structure.
In this embodiment, when the substrate 300 has a single-layer structure, the material of the substrate 300 is monocrystalline silicon.
In other embodiments, the substrate is a multilayer structure, the substrate: comprises a substrate and a device layer positioned on the surface of the substrate.
Referring to fig. 10 and 11, fig. 10 is a schematic diagram based on fig. 9, fig. 11 is a top view along a direction Z2 in fig. 10, a first device layer 301 is formed on the substrate 300, the first device layer 301 has a plurality of first pads 310 and a plurality of first test units 320 arranged along a first direction X, each first test unit 320 is electrically connected to two different first pads 310, and each first pad 310 is electrically connected to two different first test units 320.
The structures and positions of the first test unit 320 and the first pad 310 are as described in fig. 6 to 8, and are not described herein again.
The number of first test units 320 is located in the first device layer 301 of the test zone I.
In this embodiment, the method further includes: first devices 321 are formed within the first device layer 301 in the first device region II.
In this embodiment, the first testing unit 320 and the first device 321 have the same structure.
In this embodiment, in the process of forming the first test unit 320, the first device 321 is formed.
If the first test unit 320 and the first device 321 are formed simultaneously, the first test unit 320 and the first device 321 have the same structure, and whether the function of the first device 321 is normal is determined according to the test result of the first test unit 320.
Referring to fig. 12 and 13, fig. 12 is a schematic diagram based on fig. 10, fig. 13 is a top view along a direction Z3 in fig. 12, a second device layer 302 is formed on the first device layer 301, the second device layer 302 has a plurality of second pads 330 and a plurality of second test units 340 arranged along a second direction Y, the second direction Y is different from the first direction X, each second test unit 340 is electrically connected to two different second pads 330, and each second pad 330 is electrically connected to two different second test units 340; third pads are formed on the second device layer 302, the third pads are arranged along the first direction, and the third pads are connected with the first pads 310 in a one-to-one correspondence.
The structures and positions of the second testing unit 340 and the second pad 330 are as described in fig. 6 to 8, and are not described herein again.
In this embodiment, the second testing units 340 are located in the second device layer 341 of the testing region I.
In this embodiment, the method further includes: a second device 341 is formed within the second device layer 302 in the second device region III.
In this embodiment, the second testing unit 340 and the second device 341 have the same structure.
In this embodiment, in the process of forming the second test unit 340, the second device 341 is formed.
If the second test unit 340 and the second device 341 are formed at the same time, the structures of the second test unit 340 and the second device 341 are the same, and it is determined whether the function of the second device 341 is normal according to the test result of the second test unit 340.
In this embodiment, the third gasket overlaps the second gasket 330.
In this embodiment, the projection of the second spacer 330 on the first device layer 301 is a first projection, and the first projection overlaps with the first spacer 310. In other embodiments, the first projection does not overlap the first pad.
The first projection overlaps the first pad 310, i.e., in a direction perpendicular to the surface of the substrate 300, and the second pad 330 is connected to the first pad 310.
In this embodiment, before forming the second gasket 330, the method further includes: forming a groove in the second device layer 302, wherein the groove exposes the surface of the first liner 301 in the first device layer 301; plugs 250 are formed within the grooves.
The plug 250 is used to conduct the first pad 301 and the second pad 302.
In this embodiment, the second spacer 330 is located above the first spacer 310 in a direction perpendicular to the surface of the substrate 200.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (25)
1. A semiconductor wafer test structure, comprising:
a substrate;
the first device layer is positioned on the substrate and is internally provided with a plurality of first pads and a plurality of first test units which are arranged along a first direction, each first test unit is electrically connected with two different first pads, and each first pad is electrically connected with two different first test units;
the second device layer is positioned on the first device layer, a plurality of second gaskets and a plurality of second testing units are arranged in a second direction in the second device layer, the second direction is different from the first direction, each second testing unit is electrically connected with two different second gaskets, and each second gasket is electrically connected with two different second testing units;
and the third gaskets are arranged along the first direction and are connected with the first gaskets in a one-to-one correspondence mode.
2. The semiconductor wafer test structure of claim 1, further comprising: the third device layer is positioned on the second device layer, a plurality of fourth gaskets and a plurality of third testing units are arranged in the third device layer along a third direction, the third direction is different from the first direction, the third direction is different from the second direction, each third testing unit is electrically connected with two different fourth gaskets, each fourth gasket is electrically connected with two different third testing units, a fifth gasket and a sixth gasket are further arranged in the third device layer, the fourth gaskets are connected with the second gaskets, and the sixth gaskets are connected with the first gaskets.
3. The semiconductor wafer test structure of claim 2, wherein a projection of the fourth pad on the first device layer is a third projection, a projection of the fifth pad on the first device layer is a fourth projection, and a projection of the sixth pad on the first device layer is a fifth projection, and the third projection, the fourth projection, and the fifth projection partially overlap or completely overlap.
4. The semiconductor wafer test structure of claim 3, wherein the third projection partially or completely overlaps a fourth projection, the fourth projection partially or completely overlaps a fifth projection, the third projection partially or completely overlaps a fifth projection, or the third, fourth, and fifth projections overlap.
5. The semiconductor wafer test structure of claim 1 or 2, wherein a projection of the second pad on the first device layer is a first projection, a projection of the third pad on the first device layer is a second projection, and the first projection and the second projection overlap.
6. The semiconductor wafer test structure of claim 5, wherein the first projection overlaps the first pad.
7. The semiconductor wafer test structure of claim 6, wherein the second pad and the first pad are electrically connected by a plug.
8. The semiconductor wafer test structure of claim 6, wherein one first test unit is located between two adjacent first pads in the first direction.
9. The semiconductor wafer test structure of claim 8, wherein in the first direction, one first test unit is electrically connected to two adjacent first pads, and the first pad is electrically connected to one adjacent first test unit or two adjacent first test units.
10. The semiconductor wafer test structure of claim 7 or 8, wherein in the second direction, one second test unit is located between two adjacent second pads.
11. The semiconductor wafer test structure of claim 10, wherein in the second direction, one second test unit is electrically connected to two adjacent second pads, and the second pad is electrically connected to one adjacent second test unit or two adjacent second test units.
12. The semiconductor wafer test structure of claim 1, wherein the second test unit is located above the first test unit in a direction perpendicular to the substrate surface, and a projection of the second test unit on the first device layer overlaps a position of the first test unit on the first device layer.
13. The semiconductor wafer test structure of claim 1, wherein the first pads in the first device layer are arranged in an array, the first pads are formed as a first pad array, the first pad array comprises: a plurality of first pads of N rows by M columns, M is an integer greater than or equal to 2, and N is an integer greater than or equal to 2.
14. The semiconductor wafer test structure of claim 13, wherein the first test units in the first device layer are arranged in an array, the first test units are formed as a first test array, and the first test array comprises: (N-1) rows by M columns of first test cells.
15. The semiconductor wafer test structure of claim 13, wherein the second test units in the second device layer are arranged in an array, and the second test units are formed into a second test array, and the second test array comprises N rows x (M-1) columns of the second test units.
16. The semiconductor wafer test structure of claim 1, wherein the first test unit comprises: resistors, capacitors, inductors, gate structures, interconnect lines, or logic function devices; the second test unit includes: resistors, capacitors, inductors, gate structures, interconnect lines, or logic function devices.
17. The semiconductor wafer test structure of claim 16, wherein the substrate comprises a test area, a first device area and a second device area, the first test units are located in a first device layer of the test area; the plurality of second test units are positioned in the second device layer of the test area; further comprising: a first device in the first device layer of the first device region; a second device within the second device layer in the second device region.
18. The semiconductor wafer test structure of claim 17, wherein the first test unit is identical in structure to the first device.
19. The semiconductor wafer test structure of claim 17 or 18, wherein the second test unit is identical in structure to the second device.
20. A method for forming a semiconductor wafer test structure according to any one of claims 1 to 19, comprising:
providing a substrate;
forming a first device layer on the substrate, wherein the first device layer is internally provided with a plurality of first pads and a plurality of first test units which are arranged along a first direction, each first test unit is electrically connected with two different first pads, and each first pad is electrically connected with two different first test units;
forming a second device layer on the first device layer, wherein the second device layer is internally provided with a plurality of second pads and a plurality of second test units which are arranged along a second direction, the second direction is different from the first direction, each second test unit is electrically connected with two different second pads, and each second pad is electrically connected with two different second test units;
and forming third gaskets in the second device layer, wherein the third gaskets are arranged along the first direction, and the third gaskets are correspondingly connected with the first gaskets one to one.
21. The method as claimed in claim 20, wherein the substrate includes a test region, a first device region and a second device region, and the plurality of first test units are located in the first device layer of the test region; the plurality of second test units are positioned in the second device layer of the test area; further comprising: forming a first device in the first device region and in the first device layer; a second device is formed within the second device layer in the second device region.
22. The method as claimed in claim 21, wherein the first testing unit has the same structure as the first device.
23. The method as claimed in claim 21 or 22, wherein the second testing unit has the same structure as the second device.
24. The method as claimed in claim 23, wherein the first device is formed during the forming of the first test unit.
25. The method as claimed in claim 23, wherein the second device is formed during the step of forming the second test unit.
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| US11662366B2 (en) | 2021-09-21 | 2023-05-30 | International Business Machines Corporation | Wafer probe with elastomer support |
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| CN203800037U (en) * | 2014-03-28 | 2014-08-27 | 中芯国际集成电路制造(北京)有限公司 | Reliability testing structure |
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