CN110119637A - Hardware controlling method and hardware system - Google Patents
Hardware controlling method and hardware system Download PDFInfo
- Publication number
- CN110119637A CN110119637A CN201810121494.7A CN201810121494A CN110119637A CN 110119637 A CN110119637 A CN 110119637A CN 201810121494 A CN201810121494 A CN 201810121494A CN 110119637 A CN110119637 A CN 110119637A
- Authority
- CN
- China
- Prior art keywords
- address
- physical address
- hardware
- extension
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
Abstract
A kind of hardware controlling method and hardware system.Hardware controlling method is used to control an at least functional circuit for an operating system.Hardware controlling method includes the following steps.One first virtual address from operating system is converted respectively with one second virtual address as one first intermediate address and one second intermediate address.The first intermediate address and the second intermediate address are converted respectively extends physical address and one second extension physical address into one first.One spacing of starting point interval that first starting point for extending physical address extends physical address with second.The first extension physical address and second is converted respectively extends physical address as one first hardware physical address and one second hardware physical address.First hardware physical address is adjacent to the second hardware physical address.
Description
Technical field
The invention relates to a kind of control method and control system, and is controlled in particular to a kind of by virtual machine
The hardware controlling method and hardware system of switch.
Background technique
With the development of science and technology various electronic product continues to introduce new.Many electronic products carry various function electricity
Road, to realize various functions.Under the requirement of information security, need to carry out each functional circuit the control of permission.Correspond to
Different operating system, only enables the functional circuit of its needs, and must not disable the functional circuit used.
Traditionally, Fig. 1 is please referred to, operating system OS11, OS12 and switch R10, R11, R12, R13, R15, R16 are painted
Corresponding relationship schematic diagram.Each switch R10, R11, R12, R13, R15, R16 correspond to the part of specific function circuit
Or repertoire.Operating system OS11 corresponds to its workable functional circuit, and is allowed to use switch R11, R12, R16；
Operating system OS12 corresponds to its workable functional circuit, and is allowed to use switch R13, R15, R10.
It is allowed to make as shown in Figure 1, conversion circuit 420 inquires switch R10 according to the control instruction of operating system OS12
With.Referring to figure 2., it is painted the schematic diagram of the corresponding relationship of switch R10~R17 and hardware physical address PA '.Hardware is physically
Location PA ' is a corresponding page-size (page size).Due to when arranging in pairs or groups virtual machine control switch, the behaviour of conversion circuit 420
Work is as unit of a page-size, this makes conversion circuit 420 for hardware physical address PA ' provided by switch R10
Simultaneously correspond to should forbidden switch R11, R12, cause should forbidden specific function circuit part or entirely
Portion's function is allowed to use, and then the loophole of information security is caused to generate.
Summary of the invention
The invention relates to a kind of hardware controlling method and hardware systems, utilize setting for extension physical address
Meter, the control instruction for allowing operating system to provide can only enable a switch, without enabling other switches that disable, no
It will cause the loophole of information security.
According to the first aspect of the invention, a kind of hardware controlling method is proposed.The hardware controlling method is used to for an operation
System controls an at least functional circuit.The hardware controlling method includes the following steps.One from the operating system is converted respectively
First virtual address and one second virtual address are one first intermediate address and one second intermediate address.This is converted respectively in first
Between address and second intermediate address be one first to extend physical address and one second extension physical address.The first extension physics
One spacing of starting point interval of the starting point of address and the second extension physical address.The first extension physical address is converted respectively and is somebody's turn to do
Second extends physical address as one first hardware physical address and one second hardware physical address.The first hardware physical address phase
Adjacent to the second hardware physical address.The first hardware physical address and the second hardware physical address corresponding one are determined respectively
The state of first switch and a second switch.State according to the first switch and the second switch controls at least function electricity
Road.
According to the second aspect of the invention, a kind of hardware system is proposed.The hardware system is used to for an operation
System controls an at least functional circuit.The hardware system includes one first conversion circuit, one second conversion circuit and one point
Analyse circuit.First conversion circuit to convert one first virtual address and one second from the operating system virtually respectively
Location is one first intermediate address and one second intermediate address.Second conversion circuit, to convert first intermediate address respectively
It is that one first extension physical address and one second extend physical address with second intermediate address, the first extension physical address
One spacing of starting point interval of starting point and the second extension physical address.The analysis circuit to convert the first extension physics respectively
Address and the second extension physical address are one first hardware physical address and one second hardware physical address.The first hardware object
Address is managed adjacent to the second hardware physical address.The analysis circuit determine more respectively the first hardware physical address and this second
The state of hardware physical address corresponding a first switch and a second switch, and according to the first switch and the second switch
State controls an at least functional circuit.
More preferably understand to have to above-mentioned and other aspect of the invention, special embodiment below, and cooperates institute's attached drawing
Detailed description are as follows for formula:
Detailed description of the invention
Fig. 1 is painted the schematic diagram of the corresponding relationship of operating system and switch.
Fig. 2 is painted the schematic diagram of the corresponding relationship of multiple switch and multiple hardware physical address.
Fig. 3 is painted the schematic diagram of the hardware system of switch.
Fig. 4 is painted the flow chart of the hardware controlling method of the switch according to an embodiment.
Fig. 5 is painted the corresponding relationship of operating system and switch.
Fig. 6 draws switch and extends the comparative diagram of physical address.
Fig. 7 draws the comparative diagram of switch Yu hardware physical address.
Fig. 8 is painted the schematic diagram of the hardware system of the switch of virtual machine according to another embodiment.
Fig. 9 is painted the flow chart of the hardware controlling method of the switch of virtual machine according to another embodiment.
Symbol description
100,200: hardware system
110: the first conversion circuits
120: the second conversion circuits
130,230: analysis circuit
231: decision circuitry
232: mapping circuit
420: conversion circuit
600: switch
A0: initial address
EPA1, EPA2: extend physical address
GP: spacing
ID: identifier
IPA1, IPA2: intermediate address
LUT: look-up table
OS, OS11, OS12, OS21, OS22: operating system
PA, PA ': hardware physical address
R10, R11, R12, R13, R14, R15, R16, R17, R20, R21, R22, R23, R24, R25, R26, R27: switch
S110, S120, S130, S230, S231, S232, S233: step
VA1, VA2: virtual address
Specific embodiment
Following embodiment provides the various embodiments of hardware controlling method and hardware system, utilizes extension physics
The design of address, the control instruction for allowing operating system to provide can only enable a switch, without enabling its that disable
He switchs, and not will cause the loophole of information security.
Referring to figure 3., it is painted the schematic diagram of the hardware system 100 of the switch controlled by virtual machine.Hardware controls
System 100 includes one first conversion circuit 110, one second conversion circuit 120 and an analysis circuit 130.First conversion circuit
110, the second conversion circuit 120 and analysis circuit 130 are, for example, in a chip, a circuit board, a firmware circuitry or a chip
Circuit module.The function mode of each item is described in detail referring to flow chart further below.
Referring to figure 4., it is painted the flow chart of the hardware controlling method of the switch according to an embodiment.Firstly, in step
In S110, the first conversion circuit 110 converts two virtual addresses (virtual address) VA1, VA2 respectively as two intermediate addresses
(intermediate physical address)IPA1,IPA2.Wherein virtual address VA1, VA2 (is not drawn by virtual machine
Show) generation is instructed according to the one of an operating system OS.
Intermediate address IPA1, IPA2 are then sent to the second conversion circuit 120 by the first conversion circuit 110.
In the step s 120, the second conversion circuit 120 according to intermediate address IPA1, IPA2 and operating system OS one
Identifier ID is searched, and extends physical address (extended to convert intermediate address IPA1, IPA2 respectively as two
physical address)EPA1,EPA2.Extend the starting point of physical address EPA1 and extends the starting point interval of physical address EPA2
One spacing GP (being illustrated in Fig. 6).Referring to figure 5., be painted operating system OS21, OS22 and switch R20, R21, R22, R23,
The schematic diagram of the corresponding relationship of R25, R26.Each switch R20, R21, R22, R23, R25, R26 correspond to specific function circuit
Some or all of function.Switch R20, R21, R22, R23, R25, R26 can be a memory or a buffer.Operating system
OS21 corresponds to its workable functional circuit, and is allowed to use switch R21, R22, R26；Operating system OS22 corresponds to it
Workable functional circuit, and it is allowed to use switch R23, R25, R20.
In the present embodiment, the second conversion circuit 120 inquires out according to the virtual address VA1 that operating system OS22 is provided
R20 is closed to be allowed to use.Fig. 6 is please referred to, switch R20, R21 and R22 are drawn and extends the comparative diagram of physical address EPA1.Extend
Physical address EPA1 corresponds to the switch R20 for pulling open a spacing GP, and spacing GP is big greater than a page of the second conversion circuit 120
Small (page size), e.g. 4KB.In this way, which a switch can be corresponded to (on e.g. by extending physical address EPA1 only
The switch R20 stated), without corresponding to the switch R21 and R22 that disable.In this step, the second conversion circuit 120 can
To be to extend physical address EPA1, and look-up table LUT can be by the virtual machine according to look-up table LUT conversion intermediate address IPA1
It is written when booting.It note that in the present embodiment, the corresponding hardware object of each switch R20, R21, R22, R23, R25, R26
Manage address (hardware physical address) PA there is no change, but each switch R20, R21, R22, R23,
The corresponding length for extending physical address EPA1 of R25, R26 is spacing GP.
Alternatively, in another embodiment, the permeable calculating formula conversion intermediate address IPA1 of the second conversion circuit 120,
IPA2 is to extend physical address EPA1, EPA2.
Then, in step s 130, analysis circuit 130 is converted respectively extends physical address EPA1, EPA2 as two hardware objects
Manage address PA1, PA2.Fig. 7 is please referred to, the comparative diagram of switch R20~R27 Yu hardware physical address PA1, PA2 are drawn.Analysis electricity
Road 130 can will extend hardware physical address PA1, PA2 that physical address EPA1, EPA2 are converted to an only corresponding switch.?
In this step, analysis circuit 130 can be converted according to look-up table LUT extends physical address EPA1, EPA2 as hardware physical address
PA1,PA2.Alternatively, in another embodiment, analysis circuit 130 can extend through a calculating formula conversion physical address EPA1,
EPA2 is hardware physical address PA1, PA2.
Then, in step S140, analysis circuit 130 determines the corresponding switch of hardware physical address PA1, PA2 respectively
The state of R20, R21.
Also, in step S150, analysis circuit 130 controls an at least functional circuit according to the state of switch R20, R21.
The relationship of switch and functional circuit can be one-one relationship, many-to-one relationship or many-to-many relationship.
As shown in figure 3, corresponding switch 600 can be enabled through hardware physical address PA1, and operation correspondence is opened in turn
Close 600 functional circuit (not being painted).
In this way, which the control instruction that operating system OS is provided can only open through the design for extending physical address EPA1
It not will cause the loophole of information security without enabling other switches that disable with the switch being allowed to use,
Solves the problems, such as prior art.
Fig. 8 is please referred to, the schematic diagram of the hardware system 200 of switch according to another embodiment is painted.It is real herein
It applies in example, analysis circuit 230 includes that a decision circuitry 231 and a mapping circuit 232, remaining something in common are not repeated to chat
It states.
Fig. 9 is please referred to, the flow chart of the hardware controlling method of switch according to another embodiment is painted.In the present embodiment
In, converting extension physical address EPA1, EPA2 as the step S230 of hardware physical address PA1, PA2 includes step S231, step
S232 and step S233.
As shown in fig. 6, first extends the extension physical address EPA2 of physical address EPA1 and second with a common starting
Address A0.In step S231, decision circuitry 231 judges whether extension physical address EPA1, EPA2 are greater than initial address A0 and add
The address of upper spacing GP.If extending physical address EPA1, EPA2 is greater than the address that initial address adds spacing GP, enter step
S232；If extending the address that physical address EPA1, EPA2 add spacing GP no more than initial address, S233 is entered step.By
The equal quilt between the extension physical address (e.g. extending physical address EPA2) of corresponding second later switch R21~R27
Spacing GP is pulled open, therefore the extension physical address EPA1 of only corresponding first switch R20 has not been changed.Extend physical address EPA1 not
Greater than the address that initial address adds spacing GP, therefore indicate that extending physical address EPA1 is to correspond to first switch R20.
In step S233, circuit 230 is analyzed directly to extend physical address EPA1 as hardware physical address PA1.
In step S232, the transmission of decision circuitry 231 extends physical address EPA2 to mapping circuit 232.Mapping circuit 232
Mapping extends physical address EPA2 and remaps physical address (remapping physical address) for one, analyzes circuit
230 to remap physical address as hardware physical address PA2.
That is, need not then be converted, such as when extending physical address EPA1 is to correspond to first switch R20
This can accelerate the speed of processing.
Above-mentioned various embodiments provide the design for extending physical address EPA1, EPA2, the control for allowing operating system OS to provide
System instruction can only enable the switch being allowed to use, and without enabling other switches that disable, not will cause letter
Cease the loophole of safety.
In conclusion although the present invention has been disclosed by way of example above, it is not intended to limit the present invention..This field
Technical staff, without departing from the spirit and scope of the present invention, when can be used for a variety of modifications and variations.Therefore, guarantor of the invention
Range is protected subject to the appended application those as defined in claim of view.
Claims (18)
1. a kind of hardware controlling method is used to control an at least functional circuit for an operating system, which includes:
Convert one first virtual address from the operating system respectively and one second virtual address be one first intermediate address and
One second intermediate address；
First intermediate address and second intermediate address are converted respectively extends physical address and one second extension into one first
Address is managed, wherein one spacing of starting point interval of the starting point of the first extension physical address and the second extension physical address；
This is converted respectively first extends physical address and this second extends physical address as one first hardware physical address and one the
Two hardware physical address, wherein the first hardware physical address is adjacent to the second hardware physical address；
Determine that the first hardware physical address first switch corresponding with the second hardware physical address is opened with one second respectively
The state of pass；And
State according to the first switch and the second switch controls an at least functional circuit.
2. hardware controlling method as described in claim 1, which is characterized in that the first extension physical address corresponds only to one
The first switch, the second extension physical address correspond only to the second switch.
3. hardware controlling method as described in claim 1, which is characterized in that the first extension physical address and second extension
Physical address has a common initial address, which further includes:
Judge whether the first extension physical address is greater than the address that the initial address adds the spacing；And
If the first extension physical address adds the address of the spacing no more than the initial address, the first extension physics is converted
The step of address is the first hardware physical address is using the first extension physical address as the first hardware physical address.
4. hardware controlling method as described in claim 1, which is characterized in that converting first intermediate address is first extension
The step of physical address is to be carried out by a conversion circuit, and the spacing is greater than or equal to a page-size of the conversion circuit.
5. hardware controlling method as described in claim 1, which is characterized in that the spacing is greater than or equal to 4KB.
6. hardware controlling method as described in claim 1, which is characterized in that converting first intermediate address is first extension
The step of physical address, is converted according to a look-up table.
7. hardware controlling method as claimed in claim 6, which is characterized in that the virtual address is by the operating system through one
Virtual machine is generated according to an instruction, and the look-up table is generated through the virtual machine.
8. hardware controlling method as described in claim 1, which is characterized in that converting first intermediate address is first extension
The step of physical address, is converted according to the identifier for corresponding to the operating system.
9. hardware controlling method as described in claim 1, which is characterized in that converting first intermediate address is first extension
The step of physical address, is converted with a calculating formula.
10. a kind of hardware system is used to control an at least functional circuit, the hardware system packet for an operating system
It includes:
One first conversion circuit, to convert one first virtual address and one second virtual address from the operating system respectively
For one first intermediate address and one second intermediate address；
One second conversion circuit extends physics to convert first intermediate address and second intermediate address respectively into one first
Address extends physical address with one second, between the starting point of the first extension physical address and the starting point of the second extension physical address
Every a spacing；And
One analysis circuit, to convert the first extension physical address and the second extension physical address respectively as one first hardware
Physical address and one second hardware physical address, wherein the first hardware physical address is adjacent to the second hardware physical address；
The analysis circuit determine more respectively the first hardware physical address first switch corresponding with the second hardware physical address with
The state of one second switch, and the state according to the first switch and the second switch controls an at least functional circuit.
11. hardware system as claimed in claim 10, which is characterized in that the first extension physical address corresponds only to one
A first switch, the second extension physical address correspond only to the second switch.
12. hardware system as claimed in claim 10, which is characterized in that the first extension physical address second prolongs with this
Stretching physical address has a common initial address, which includes:
One decision circuitry, to judge whether the first extension physical address is greater than the address that the initial address adds the spacing,
If the first extension physical address adds the address of the spacing no more than the initial address, made with the first extension physical address
For the first hardware physical address.
13. hardware system as claimed in claim 10, which is characterized in that the spacing is greater than or equal to second conversion
One page-size of circuit.
14. hardware system as claimed in claim 10, which is characterized in that the spacing is for 4KB.
15. hardware system as claimed in claim 10, which is characterized in that second conversion circuit is according to a look-up table
Converting first intermediate address is the first extension physical address.
16. hardware system as claimed in claim 15, which is characterized in that the virtual address is penetrated by the operating system
One virtual machine is generated according to an instruction, and the look-up table is generated through the virtual machine.
17. hardware system as claimed in claim 10, which is characterized in that second conversion circuit is according to the corresponding behaviour
The identifier for making system is converted.
18. hardware system as claimed in claim 10, which is characterized in that second conversion circuit is converted with a calculating formula
First intermediate address is the first extension physical address.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810121494.7A CN110119637B (en) | 2018-02-07 | 2018-02-07 | Hardware control method and hardware control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810121494.7A CN110119637B (en) | 2018-02-07 | 2018-02-07 | Hardware control method and hardware control system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110119637A true CN110119637A (en) | 2019-08-13 |
| CN110119637B CN110119637B (en) | 2023-04-14 |
Family
ID=67520112
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810121494.7A Active CN110119637B (en) | 2018-02-07 | 2018-02-07 | Hardware control method and hardware control system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110119637B (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0126769D0 (en) * | 2001-11-07 | 2002-01-02 | Sun Microsystems Inc | Computer system with virtual memory and paging mechanism |
| CN101059761A (en) * | 2006-04-20 | 2007-10-24 | 联想(北京)有限公司 | Dummy machine system and its hardware access method |
| US20070283124A1 (en) * | 2006-06-05 | 2007-12-06 | Sun Microsystems, Inc. | Hybrid techniques for memory virtualization in a computer system |
| US20070294494A1 (en) * | 2006-06-16 | 2007-12-20 | Texas Instruments Incorporated | Page processing circuits, devices, methods and systems for secure demand paging and other operations |
| CN101093448A (en) * | 2006-06-23 | 2007-12-26 | 联想(北京)有限公司 | Method for switching a system of virtual machine and hardware devices |
| US20090037682A1 (en) * | 2007-08-02 | 2009-02-05 | International Business Machines Corporation | Hypervisor-enforced isolation of entities within a single logical partition's virtual address space |
| CN101520738A (en) * | 2008-02-27 | 2009-09-02 | 黄歆媚 | Virtual machine system based on the management technology of equipment access storage and equipment access control method thereof |
| US20090292899A1 (en) * | 2008-05-21 | 2009-11-26 | Arm Limited | Data processing apparatus and method for handling address translation for access requests issued by processing circuitry |
| CN102693186A (en) * | 2011-02-25 | 2012-09-26 | 西门子公司 | Method for managing physical memory of a data storage and data storage management system |
| JP2014119787A (en) * | 2012-12-13 | 2014-06-30 | Renesas Electronics Corp | Processor |
| CN105074663A (en) * | 2013-03-12 | 2015-11-18 | 高通股份有限公司 | Method and apparatus to selectively enable operations of a virtual machine monitor on demand |
| CN106203082A (en) * | 2016-06-29 | 2016-12-07 | 上海交通大学 | The system and method efficiently isolating kernel module based on virtualization hardware characteristic |
| CN107305509A (en) * | 2016-04-22 | 2017-10-31 | 三星电子株式会社 | It is related to the Buffer mapping scheme of the predistribution of internal memory |
-
2018
- 2018-02-07 CN CN201810121494.7A patent/CN110119637B/en active Active
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB0126769D0 (en) * | 2001-11-07 | 2002-01-02 | Sun Microsystems Inc | Computer system with virtual memory and paging mechanism |
| CN101059761A (en) * | 2006-04-20 | 2007-10-24 | 联想(北京)有限公司 | Dummy machine system and its hardware access method |
| US20070283124A1 (en) * | 2006-06-05 | 2007-12-06 | Sun Microsystems, Inc. | Hybrid techniques for memory virtualization in a computer system |
| US20070294494A1 (en) * | 2006-06-16 | 2007-12-20 | Texas Instruments Incorporated | Page processing circuits, devices, methods and systems for secure demand paging and other operations |
| CN101093448A (en) * | 2006-06-23 | 2007-12-26 | 联想(北京)有限公司 | Method for switching a system of virtual machine and hardware devices |
| US20090037682A1 (en) * | 2007-08-02 | 2009-02-05 | International Business Machines Corporation | Hypervisor-enforced isolation of entities within a single logical partition's virtual address space |
| CN101520738A (en) * | 2008-02-27 | 2009-09-02 | 黄歆媚 | Virtual machine system based on the management technology of equipment access storage and equipment access control method thereof |
| US20090292899A1 (en) * | 2008-05-21 | 2009-11-26 | Arm Limited | Data processing apparatus and method for handling address translation for access requests issued by processing circuitry |
| CN102693186A (en) * | 2011-02-25 | 2012-09-26 | 西门子公司 | Method for managing physical memory of a data storage and data storage management system |
| JP2014119787A (en) * | 2012-12-13 | 2014-06-30 | Renesas Electronics Corp | Processor |
| CN105074663A (en) * | 2013-03-12 | 2015-11-18 | 高通股份有限公司 | Method and apparatus to selectively enable operations of a virtual machine monitor on demand |
| CN107305509A (en) * | 2016-04-22 | 2017-10-31 | 三星电子株式会社 | It is related to the Buffer mapping scheme of the predistribution of internal memory |
| CN106203082A (en) * | 2016-06-29 | 2016-12-07 | 上海交通大学 | The system and method efficiently isolating kernel module based on virtualization hardware characteristic |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110119637B (en) | 2023-04-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101661258B1 (en) | Secure input via a touchscreen | |
| CN104169897B (en) | The method of PCI high speed address decoding | |
| US9280494B2 (en) | System method for associating an application runnng on computing system by selectively altering an attribute of the input and output of connected peripheral device | |
| KR980700632A (en) | Circuits, systems and methods for memory mapping and display control systems using them (CIRCUITS, SYSTEMS AND METHOOS FOR MEMORY MAPPING AND DISPLAY CONTROL SYSTEMS USING THE SAME) | |
| US20050283549A1 (en) | Reconfigurable USB I/O device persona | |
| US8209509B2 (en) | Accessing memory in a system with memory protection | |
| US20090150884A1 (en) | Computer and method of providing software user interface | |
| JP2013522748A (en) | Hierarchical translation table control | |
| JPH0212523A (en) | Computer display system | |
| CN101385014A (en) | Command interface | |
| CN101131637A (en) | Method and device for generating user interface | |
| KR102002971B1 (en) | Display and operating unit and method of operating a field instrument using a display and operating unit | |
| KR950025519A (en) | Data processing unit | |
| CN112306439A (en) | One-machine multi-screen interaction system and management method thereof, electronic equipment and storage medium | |
| CN110119637A (en) | Hardware controlling method and hardware system | |
| CN104020989B (en) | Control method and system based on remote application | |
| JP2010218478A (en) | Computer system having hypervisor | |
| KR870007463A (en) | Virtual peripheral controller | |
| US10595446B2 (en) | Optimized and intelligent fan control mechanism inside rack system | |
| JP2012113565A (en) | Network device, network system, and control method of network device | |
| CN203133754U (en) | KVM board card based on server provided with CPCI framework | |
| EP3671472B1 (en) | Data access method and device | |
| JP2007522565A (en) | Computer presentation and command integration apparatus and method | |
| CN108845613A (en) | Interactive intelligent tablet computer and its data processing side and device | |
| JP2003202999A (en) | Virtual computer system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20191224 Address after: No.1, Duhang 1st Road, Hsinchu City, Hsinchu Science Park, Taiwan, China Applicant after: MEDIATEK Inc. Address before: 1/2, 4th floor, 26 Taiyuan Street, Zhubei City, Hsinchu County, Taiwan, China Applicant before: MSTAR SEMICONDUCTOR Inc. |
|
| TA01 | Transfer of patent application right | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |