CN110112160A - A kind of array substrate and preparation method thereof, display device - Google Patents
A kind of array substrate and preparation method thereof, display device Download PDFInfo
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- CN110112160A CN110112160A CN201910394109.0A CN201910394109A CN110112160A CN 110112160 A CN110112160 A CN 110112160A CN 201910394109 A CN201910394109 A CN 201910394109A CN 110112160 A CN110112160 A CN 110112160A
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- H01L27/144—Devices controlled by radiation
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Abstract
The present invention relates to display field, a kind of array substrate and preparation method thereof, display device are disclosed, which includes: multiple photosensitive structures；Each photosensitive structure includes PIN device and the first TFT；First TFT includes: the first electrode on substrate；The first insulating layer in first electrode；Second electrode on the first insulating layer；Active layer in second electrode, active layer are contacted through the first insulating layer with first electrode, and active layer has the channel region being connected between first electrode and second electrode；Second insulating layer on active layer；Grid in second insulating layer, grid cover channel region；PIN device is set on the first TFT and is electrically connected with grid.The first TFT size in the array substrate is smaller, and compact-sized between the first TFT and PIN device, area occupied is smaller on being parallel to substrate, can effectively improve the pixel density of product, is conducive to the production of high PPI.
Description
Technical field
The present invention relates to field of display technology, in particular to a kind of array substrate and preparation method thereof, display device.
Background technique
Currently, PIN (photodiode P-I-N) device is because it is with preferable light sensitive characteristic and simultaneous with panel process
Capacitive has more and more been integrated into inside screen, and for fields such as fingerprint recognition, pulse detections, wherein PIN device
Use be conducive to increase screen integrated level, while screen function can also be enriched, promote screen added value.But it is traditional at present
PIN photo sensor device in, TFT device is independent of each other, parallel unit with PIN unit, and this frame mode occupies
Area is larger, is unfavorable for high PPI (pixel density) production.
Summary of the invention
The first TFT ruler the invention discloses a kind of array substrate and preparation method thereof, display device, in the array substrate
Very little smaller and compact-sized between the first TFT and PIN device, area occupied is smaller on being parallel to substrate, can effectively improve
The pixel density of product is conducive to the production of high PPI.
In order to achieve the above objectives, the present invention the following technical schemes are provided:
A kind of array substrate, comprising: substrate, multiple photosensitive structures on the substrate；Each photosensitive structure
Including PIN device and the first TFT；Wherein, the first TFT includes:
First electrode on the substrate；
The first insulating layer in the first electrode；
Second electrode on first insulating layer；
Active layer in the second electrode, the active layer is through first insulating layer and the first electrode
Contact, and the active layer has the channel region being connected between the first electrode and second electrode, the channel region includes
The first contact zone for contacting with the first electrode, the second contact zone contacted with the second electrode and it is located at described the
Bonding pad between one contact zone and the second contact zone；
Second insulating layer on the active layer；
Grid in the second insulating layer, on the direction perpendicular to the substrate, described in the grid covering
Channel region；
The PIN device is set on the first TFT and is electrically connected with the grid.
In above-mentioned array substrate, for purposes of illustration only, using the direction parallel with substrate as horizontal direction, perpendicular to substrate
Direction is vertical direction, and in the structure of above-mentioned array substrate, substrate is equipped with multiple photosensitive structures, and multiple photosensitive structures can
To be in array distribution, it is also possible to other distribution modes, mainly the functional requirement setting to need photosensitive structure to realize, each
It may include a PIN device and the first TFT being electrically connected with PIN device in photosensitive structure, wherein the first TFT packet
Include the first electrode being cascading on substrate, the first insulating layer and second electrode, on the second electrode with second electrode
The directly active layer of contact setting, and the active layer passes through the first insulating layer and first electrode connects, and in the active layer
With the channel region being connected between first electrode and second electrode, channel region includes that the active layer is contacted with first electrode
One contact zone, the second contact zone that active layer is contacted with second electrode, and between the first contact zone and the second contact zone
And the bonding pad of the first contact zone and the second contact zone is connected, the bonding pad of that layer of having chance with and substrate are not parallel, wherein bonding pad
It can be arranged perpendicular to substrate；It is provided on active layer in second insulating layer and second insulating layer and is provided with grid, hung down
Directly on the direction of substrate, grid covers the channel region of active layer, that is, the orthographic projection of channel region on substrate is located at grid and is serving as a contrast
Within orthographic projection on bottom, wherein PIN device is located at the top of the first TFT, and is electrically connected with grid, above-mentioned electric with PIN device
In first TFT of connection, first electrode and second electrode are arranged along the direction perpendicular to substrate, are connected by active layer, i.e. phase
For substrate, the first TFT is a vertical TFT in structure, and compact-sized, device size is smaller, and area occupied is smaller, separately
Outside, PIN device is located above the first TFT, that is, PIN device and the first TFT arrange setting in the vertical direction, with the first TFT it
Between structure it is compacter, be distinct from PIN device and the TFT being attached thereto in the prior art and arrange in the horizontal direction, the present invention
In PIN device and the first TFT set-up mode, save substrate area occupied in the horizontal direction, be conducive to improve product
Pixel density, be conducive to the production of high PPI.
Therefore, the first TFT size in above-mentioned array substrate is smaller, and compact-sized between the first TFT and PIN device,
Area occupied is smaller on being parallel to substrate, can effectively improve the pixel density of product, is conducive to the production of high PPI.
Preferably, the orthographic projection of the first electrode on substrate protrudes from the second electrode in two sides；Described
One contact zone, second contact zone, the bonding pad and the grid are two；Wherein, a grid and the PIN device
Part electrical connection, another grid is for loading fixed current potential.
Preferably, the photosensitive structure further include: the signal wire being electrically connected with the PIN device；The signal wire is set to
It metal layer on the PIN device and is not overlapped with the PIN device；The signal wire by transparent bridge wiring with it is described
PIN break-over of device；The transparent bridge wiring is set to the film layer on the PIN device and the metal layer.
Preferably, the array substrate further includes the multiple sub-pixels being arranged in array on the substrate, each
The sub-pixel includes luminescent device and the 2nd TFT.
Preferably, the grid same layer of the grid of the 2nd TFT and the first TFT are arranged.
Preferably, the active layer same layer of the active layer of the 2nd TFT and the first TFT are arranged.
Preferably, the source-drain electrode of the 2nd TFT and the signal wire same layer are arranged.
Preferably, the anode of the luminescent device and the transparent bridge wiring same layer are arranged.
Based on same invention thought, the present invention also provides a kind of preparation methods of array substrate, comprising:
First electrode, the first insulating layer, the second electrode, active layer, second for constituting the first TFT are sequentially formed on substrate
Insulating layer and grid；Wherein, the active layer is contacted through first insulating layer with the first electrode, and the active layer
With the channel region being connected between the first electrode and second electrode, the channel region includes contacting with the first electrode
The first contact zone, the second contact zone for being contacted with the second electrode and contacted positioned at first contact zone and second
Bonding pad between area；
The PIN device being electrically connected with the grid is formed on the first TFT.
Preferably, the preparation method further include:
The active layer for forming the first TFT simultaneously, form the active layer of the 2nd TFT；
The grid for forming the first TFT simultaneously, form the grid of the 2nd TFT；
It is blocked using the grid of the 2nd TFT, the part exposed to the active layer of the 2nd TFT is doped work
Skill；
After forming the PIN device, it is formed simultaneously the source-drain electrode of signal wire and the 2nd TFT；
The transparent bridge wiring for forming the conducting PIN device and the signal wire, is formed simultaneously the anode of luminescent device.
Based on same invention thought, the present invention also provides a kind of display devices, including as provided in above-mentioned technical proposal
Any one array substrate.
Detailed description of the invention
Fig. 1 to Fig. 7 is that the film layer structure variation in a kind of preparation process of array substrate provided in an embodiment of the present invention is shown
It is intended to；
Fig. 8 is a kind of film layer structure schematic diagram of array substrate provided in an embodiment of the present invention；
Fig. 9 is a kind of structural schematic diagram of photosensitive structure provided in an embodiment of the present invention；
Icon: 1- substrate；2-PIN device；The first TFT of 3-；4- signal wire；5- transparent bridge wiring；The 2nd TFT of 6-；7- sun
Pole；31- first electrode；The first insulating layer of 32-；33- second electrode；34,62- active layer；35- second insulating layer；36,37,61-
Grid；63- source-drain electrode,；341,342- channel region.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
Fig. 7 is a kind of film layer structure schematic diagram of array substrate provided in an embodiment of the present invention, and Fig. 8 is also implementation of the present invention
A kind of film layer structure schematic diagram for array substrate that example provides；With reference to shown in Fig. 7, Fig. 8 and Fig. 9, the embodiment of the invention provides
A kind of array substrate, comprising: substrate 1, multiple photosensitive structures on substrate；Each photosensitive structure includes PIN device 2 and
One TFT3；Wherein, the first TFT includes: the first electrode 31 on substrate；The first insulating layer in first electrode 31
32；
Second electrode 33 on the first insulating layer；Active layer 34 in second electrode 33, active layer 34 run through
First insulating layer 32 is contacted with first electrode 31, and active layer 34 has the channel being connected between first electrode and second electrode
Area 341, channel region 341 include the first contact zone contacted with first electrode, the second contact zone contacted with second electrode and
Bonding pad between the first contact zone and the second contact zone；Second insulating layer 35 on active layer 34；Set on second
Grid 36 on insulating layer 35, on the direction perpendicular to substrate, grid 36 covers channel region；PIN device is set to the first TFT3
Above and with grid 36 it is electrically connected.
In above-mentioned array substrate, for purposes of illustration only, using the direction parallel with substrate 1 as horizontal direction, perpendicular to substrate 1
Direction be vertical direction, in the structure of above-mentioned array substrate, substrate 1 is equipped with multiple photosensitive structures, and multiple photoresponsive junctions
Structure can be in array distribution, be also possible to other distribution modes, mainly the functional requirement setting to need photosensitive structure to realize,
It may include a PIN device 2 and the first TFT3 being electrically connected with PIN device 2 in each photosensitive structure, wherein this
One TFT3 includes the first electrode 31 being cascading on substrate 1, the first insulating layer 32 and second electrode 33, in the second electricity
The active layer 34 of setting is directly contacted on pole 33 with second electrode, and the active layer 34 passes through the first insulating layer 31 and first electrode
31 connect, and have the channel region 341 being connected between first electrode 31 and second electrode 33, channel in the active layer 34
Area 341 includes the first contact zone for contacting with first electrode of the active layer, and what active layer 34 was contacted with second electrode 33 second connects
Touch area, and between the first contact zone and the second contact zone and connect the first contact zone and the second contact zone bonding pad,
Have chance with that layer bonding pad and substrate it is not parallel, wherein bonding pad can be arranged perpendicular to substrate；Is provided on active layer 34
It is provided with grid 36 in two insulating layers 35 and second insulating layer 35, on the direction perpendicular to substrate, grid 36 is covered with
The channel region 341 of active layer, that is, channel region 341 is located at grid 36 within the orthographic projection on substrate 1 in the orthographic projection on substrate 1,
Wherein, PIN device 2 is located at the top of the first TFT3, and is electrically connected with grid 36, above-mentioned first be electrically connected with PIN device 2
In TFT3, relatively first electrode 31 and second electrode 33 are connected, i.e., along the direction arrangement perpendicular to substrate 1 by active layer 34
In substrate 1, the first TFT3 is a vertical TFT in structure, and compact-sized, device size is smaller, and area occupied is smaller, separately
Outside, PIN device 2 is located above the first TFT3, that is, PIN device 2 and the first TFT3 arrange setting in the vertical direction, with first
Structure is compacter between TFT3, is distinct from PIN device in the prior art and the TFT being attached thereto arranges in the horizontal direction,
The set-up mode of PIN device and the first TFT in the present invention, saves substrate area occupied in the horizontal direction, is conducive to mention
The pixel density of high product is conducive to the production of high PPI.
Therefore, the first TFT size in above-mentioned array substrate is smaller, and compact-sized between the first TFT and PIN device,
Area occupied is smaller on being parallel to substrate, can effectively improve the pixel density of product, is conducive to the production of high PPI.
Specifically, orthographic projection of the second electrode 33 on substrate 1 protrudes from first electrode 31 in two sides；Such as Fig. 7 and Fig. 9
Shown, the first contact zone, the second contact zone, bonding pad and grid are two, a grid 36 and another grid 37；Its
In, a grid 36 is electrically connected with PIN device 2, another grid 37 is for loading fixed current potential.The width of first electrode 31 is big
In second electrode 33, and second electrode 33, above first electrode 31, orthographic projection of the second electrode 33 on substrate 1 falls in first
Electrode 31 is on substrate 1 within orthographic projection, i.e. the two sides of first electrode 31 two sides that lean out second electrode 33, the first electricity
The two sides of pole 31 are respectively formed one relative to the two sides of second electrode 33 and lean out portion, and the active layer 34 of the first TFT is covered on
Contacted in second electrode 33 with second electrode 33, and in the active layer 34 with the two sides edge of second electrode 33 and second electrode 33
The part of contact forms the second contact zone, and active layer can be across second electrode 33 and both ends connect with first electrode 31 respectively
Touching, i.e. active layer are formed with first electrode 31 there are two the first contact zone respectively, and two the first contact zones on substrate 1 just
Projection is located at the two sides of orthographic projection of the second electrode 33 on substrate 1, i.e. two the first contact zones are located at the first electricity
31 two sides of pole lean out portion, then two channel regions, i.e. channel region 341 and channel region 342 are formed in active layer, wherein first
Every side in the two sides corresponding with second electrode 33 of electrode 31 is respectively provided with a grid, between two grids each other absolutely
Edge, and each grid is corresponding with a channel region in active layer 34, and covers corresponding channel region in the vertical direction, two
In a grid, grid 36 is connect with PIN device 2, and PIN device 2 can be arranged directly on the grid with the gate contact simultaneously
For loading fixed current potential by the structure setting of above-mentioned first TFT3, i.e., double grid is arranged in the first TFT3 in electrical connection, grid 37
Structure makes the grid for loading fixed current potential 37 load the voltage signal collocation co- controlling that certain voltage and PIN device 2 generate
The output signal of first TFT3 has the function of amplifying photosensor signal, keeps the induction sensitivity of photosensor signal higher.
As shown in figure 9, the photosensitive structure in above-mentioned array substrate further include: the signal wire 4 being electrically connected with PIN device 2, this
Place's signal wire 4 is for loading fixed current potential；Signal wire 4 be set to PIN device 2 on metal layer and do not weighed mutually with PIN device 2
It is folded；Signal wire 4 is connected by transparent bridge wiring 5 and PIN device 2；Transparent bridge wiring 5 is set to where PIN device 2 and signal wire 4
Metal layer on film layer.
Specifically, above-mentioned array substrate further includes the multiple sub-pixels being arranged in array on substrate 1, every height picture
Element includes luminescent device and the 2nd TFT6, and the 2nd TFT6 is the switch for controlling optical device.
And about the film layer setting in the 2nd TFT6 structure, specifically, the grid 61 of the 2nd TFT6 can be with the first TFT3
Grid 36 and 37 same layer of grid setting；The active layer 62 of 2nd TFT6 can be set with 34 same layer of active layer of the first TFT3
It sets；The source-drain electrode 63 and 4 same layer of signal wire of 2nd TFT6 is arranged.The structure of 2nd TFT6 is made simultaneously with the first TFT3 structure
Standby, simplification of flowsheet is conducive to save cost.
Wherein, the sun that the anode 7 of luminescent device and the setting of 5 same layer of transparent bridge wiring, i.e. transparent bridge wiring 5 are luminescent device
A part in 7 layers of pole, and transparent bridge wiring 5 and the anode 7 in 7 layers of anode are insulated from each other, by a part of shape in 7 layers of anode
At transparent bridge wiring 5, be conducive to save process flow.
In above-mentioned array substrate, signal wire 4 can be set in PIN device 2 on substrate 1 in the orthographic projection on substrate 1
The side of orthographic projection, that is, the side of PIN device 2 is arranged in signal wire 4 in the horizontal direction, specifically, as shown in fig. 7, conduct
PIN device 2 can be arranged in away from the first TFT3's in the horizontal direction in signal wire 4 by a kind of set-up mode of signal wire 4
Side, that is, signal wire 4 is located at orthographic projection of the PIN device 2 on substrate 1 in the orthographic projection on substrate 1 and is serving as a contrast away from the first TFT3
The side of the orthographic projection at bottom 1；As shown in figure 8, another set-up mode as signal wire 4 can will be believed in the horizontal direction
PIN device 2 is arranged in towards the side of the first TFT3 and corresponding with the first TFT3 in the vertical direction in number line 4, that is, signal wire 4
Orthographic projection on substrate 1 can have overlapping with orthographic projection of the first TFT3 on substrate 1, increase photosensitive in above-mentioned array substrate
The compactedness of structure is conducive to the area occupied for further decreasing above-mentioned photosensitive structure, improves pixel density.
Based on same invention thought, referring to figs. 1 to shown in Fig. 7, the present invention also provides a kind of preparation sides of array substrate
Method, comprising: firstly, sequentially forming the first electrode 31 for constituting the first TFT3, the first insulating layer 32, second electrode on substrate 1
33, active layer 34, second insulating layer 35 and grid 36；Wherein, active layer 34 connects through the first insulating layer 32 with first electrode 31
Touching, and active layer 34 has and is connected to channel region 341 between first electrode 31 and second electrode 33, channel region 341 include with
The first contact zone that first electrode 31 contacts, the second contact zone for being contacted with second electrode 33 and positioned at the first contact zone and
Bonding pad between second contact zone；Then, the PIN device 2 being electrically connected with grid is formed on the first TFT3.
Specifically, luminescent device is also formed with and for controlling while forming above-mentioned photosensitive structure in above-mentioned preparation method
2nd TFT of luminescent device processed, wherein specifically, the part film layer in the 2nd TFT can be with the first TFT's in light-sensitive device
It part film layer same layer and prepares to be formed with material, that is, also preparing the 2nd TFT while preparing a TFT, specifically preparing
It can be such that
Firstly, as shown in Figure 1, sequentially forming first electrode 31, the first insulating layer 32, second electrode 33 on substrate；So
Afterwards, as shown in Fig. 2, forming the active layer 34 of the first TFT on the first insulating layer 32, while the is formed on the first insulating layer 32
The active layer 62 of two TFT, it can prepare the active layer 34 and the 2nd TFT of the first TFT simultaneously in same preparation section
Active layer 62, and be doped to part corresponding with source-drain electrode is used in the active layer 62 of the 2nd TFT, make the 2nd TFT's
Part corresponding with source-drain electrode conductor is used in active layer 62, in addition, the active layer 34 of the first TFT runs through the first insulating layer
32 contact with first electrode 31, and the active layer 34 of the first TFT have be connected between first electrode 31 and second electrode 33
Channel region, channel region include the first contact zone contacted with first electrode 31, the second contact zone contacted with second electrode 33, with
And the bonding pad between the first contact zone and the second contact zone；Then, as shown in figure 3, in the first insulating layer 32 and
Second insulating layer 35 is formed on the active layer 62 of have chance with that layer 34 and the 2nd TFT of one TFT, it is then same in second insulating layer 35
When formed the first TFT grid and the 2nd TFT grid；Followed by, as shown in Figure 4 and Figure 5, the shape on the grid of the first TFT
At PIN device 2, later in the interlayer dielectric layer for being formed in the setting of 2 same layer of PIN device；Then as shown in fig. 6, in inter-level dielectric
It is formed on layer for the signal wire 4 in fixed current potential to be electrically connected and connect with PIN device, and the signal wire 4 and PIN device 2 are not
It is directly connected to, insulate between PIN device 2, be formed simultaneously the source-drain electrode 63 of the 2nd TFT, source-drain electrode 62 is situated between through interlayer
Matter layer and the location contacts corresponding with the active layer 62 of the 2nd TFT of second insulating layer 35 are simultaneously electrically connected；Next, such as Fig. 7 institute
Show, form flatness layer on interlayer dielectric layer, PIN device 2 and signal wire 4 and source-drain electrode 63, forms benefit on flatness layer
The anode 7 of transparent bridge wiring 5 and luminescent device is prepared with same Patternized technique, wherein transparent bridge wiring 5 runs through flatness layer
It connect with PIN device 2, and is connect with signal wire 4, PIN device 2 is electrically connected with signal wire 4, anode 7 is through flatness layer and the
The source-drain electrode of two TFT connects.In above-mentioned preparation method, the 2nd TFT6 and the first TFT3 is prepared simultaneously, and in the two structure
Part film layer same layer and prepare simultaneously, be conducive to simplify preparation process, save preparation cost.
Based on same invention thought, a kind of display device is additionally provided in the embodiment of the present invention, including such as above-described embodiment
Any one array substrate of middle offer.
Obviously, those skilled in the art can carry out various modification and variations without departing from this hair to the embodiment of the present invention
Bright spirit and scope.In this way, if these modifications and changes of the present invention belongs to the claims in the present invention and its equivalent technologies
Within the scope of, then the present invention is also intended to include these modifications and variations.
Claims (11)
1. a kind of array substrate characterized by comprising substrate, multiple photosensitive structures on the substrate；It is each described
Photosensitive structure includes PIN device and the first TFT；Wherein, the first TFT includes:
First electrode on the substrate；
The first insulating layer in the first electrode；
Second electrode on first insulating layer；
Active layer in the second electrode, the active layer connect through first insulating layer with the first electrode
Touching, and the active layer has and is connected to channel region between the first electrode and second electrode, the channel region include with
First contact zone of first electrode contact, the second contact zone contacted with the second electrode and positioned at described first
Bonding pad between contact zone and the second contact zone；
Second insulating layer on the active layer；
Grid in the second insulating layer, on the direction perpendicular to the substrate, the grid covers the channel
Area；
The PIN device is set on the first TFT and is electrically connected with the grid.
2. array substrate according to claim 1, which is characterized in that the orthographic projection of the first electrode on substrate is two
Side protrudes from the second electrode；First contact zone, second contact zone, the bonding pad and the grid are
Two；Wherein, a grid is electrically connected with the PIN device, another grid is for loading fixed current potential.
3. array substrate according to claim 1, which is characterized in that the photosensitive structure further include: with the PIN device
The signal wire of electrical connection；The signal wire be set to the PIN device on metal layer and do not overlapped with the PIN device；
The signal wire passes through transparent bridge wiring and the PIN break-over of device；The transparent bridge wiring is set to the PIN device and described
Film layer on metal layer.
4. array substrate according to claim 3, which is characterized in that further include being arranged in array on the substrate
Multiple sub-pixels, each sub-pixel includes luminescent device and the 2nd TFT.
5. array substrate according to claim 4, which is characterized in that the grid of the 2nd TFT is with the first TFT's
The setting of grid same layer.
6. array substrate according to claim 4, which is characterized in that the active layer and the first TFT of the 2nd TFT
Active layer same layer setting.
7. array substrate according to claim 4, which is characterized in that the source-drain electrode and the signal of the 2nd TFT
The setting of line same layer.
8. array substrate according to claim 4, which is characterized in that the anode of the luminescent device and the transparent bridging
The setting of line same layer.
9. a kind of preparation method of such as described in any item array substrates of claim 1-8 characterized by comprising
The first electrode for constituting the first TFT, the first insulating layer, second electrode, active layer, the second insulation are sequentially formed on substrate
Layer and grid；Wherein, the active layer is contacted through first insulating layer with the first electrode, and the active layer has
The channel region being connected between the first electrode and second electrode, the channel region include contacted with the first electrode
One contact zone, the second contact zone contacted with the second electrode and be located at first contact zone and the second contact zone it
Between bonding pad；
The PIN device being electrically connected with the grid is formed on the first TFT.
10. preparation method according to claim 9, which is characterized in that further include:
The active layer for forming the first TFT simultaneously, form the active layer of the 2nd TFT；
The grid for forming the first TFT simultaneously, form the grid of the 2nd TFT；
It is blocked using the grid of the 2nd TFT, the part exposed to the active layer of the 2nd TFT is doped technique；
After forming the PIN device, it is formed simultaneously the source-drain electrode of signal wire and the 2nd TFT；
The transparent bridge wiring for forming the conducting PIN device and the signal wire, is formed simultaneously the anode of luminescent device.
11. a kind of display device, which is characterized in that including such as described in any item array substrates of claim 1-8.
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| US20210305282A1 (en) * | 2019-11-12 | 2021-09-30 | Boe Technology Group Co., Ltd. | Display substrate and method for manufacturing the same, and display appratus |
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