CN110109619A - A kind of storage system and implementation method of closed loop multistage anti-single particle overturning effect - Google Patents
A kind of storage system and implementation method of closed loop multistage anti-single particle overturning effect Download PDFInfo
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- CN110109619A CN110109619A CN201910340318.7A CN201910340318A CN110109619A CN 110109619 A CN110109619 A CN 110109619A CN 201910340318 A CN201910340318 A CN 201910340318A CN 110109619 A CN110109619 A CN 110109619A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/1032—Simple parity
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
- G06F3/0631—Configuration or reconfiguration of storage systems by allocating resources to storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
- G06F3/0644—Management of space entities, e.g. partitions, extents, pools
Abstract
The invention discloses a kind of storage systems of closed loop multistage anti-single particle overturning effect, including CPU, FPGA and memory, CPU is sent to FPGA reads memory instructions or memory write instruction, FPGA parses received instruction, and data write-in memory is executed from the operation for reading data write-in CPU in memory appropriate address or read from CPU appropriate address space after successfully resolved.The invention discloses the implementation methods of the storage system simultaneously.Data inflow and outflow channel error correction path closed loop between CPU, FPGA and memory of the present invention, data manipulation path is short, service speed is fast, and triplication redundancy is done to FPGA program, it ensures to malfunction even if three groups of data of write-in memory and remains to correct, effectively improve storage system anti-single particle overturning ability.
Description
Technical field
The invention belongs to environment Flouride-resistani acid phesphatase technical field, in particular to a kind of closed loop multistage anti-single particle based on FPGA turns over
Turn the storage system and implementation method of effect.
Background technique
When Energetic particle injects semiconductor devices sensitive volume, often the phenomenon that the overturning of meeting generating device logic state,
That is single-particle inversion.With the increase of semiconductor chip collection on a large scale, simple grain occurs in complex electromagnetic environment lower semiconductor device
The probability of son overturning is increasing.Gently then system running state is caused to change when the overturning of device logic state, it is heavy then cause people
Member's catastrophic effects such as injures and deaths and mission failure.
The method of current memory anti-single particle effect mainly includes two aspect of technique and design.Using special anti-spoke
There is higher cost and the drawbacks such as measure is limited according to reinforcement process, the adoptable means of design aspect are flexible and more, have and entangle one
Inspection two, or entangle two inspections mostly etc..But it is single often to there is error correcting system in these methods, and error correction object is unilateral and error correction path open loop etc.
Problem, there are also the spaces further promoted for the effect of anti-single particle overturning effect.
Summary of the invention
Technical problem solved by the present invention is overcoming the shortage of prior art, it is anti-to provide a kind of closed loop multistage based on FPGA
The storage system and implementation method of Single event upset effecf.
Technical solution of the invention are as follows:
A kind of storage system of closed loop multistage anti-single particle overturning effect, including CPU, FPGA and memory, CPU is to FPGA
It sends reading memory instructions or memory write instruction, FPGA parses received instruction, execute after successfully resolved from storage
Data write-in CPU is read in device appropriate address or the operation of data write-in memory is read from CPU appropriate address space.
A kind of storage system implementation method of closed loop multistage anti-single particle overturning effect:
(1) three parts of do not connect mould address space A, B and C are matched by same function distinguishing to the memory space of memory；
(2) CPU sends instructions to FPGA, and FPGA carries out odd to the instruction received, enters step (3)；
(3) if step (2) odd result is correct, FPGA parses the instruction received, is tied according to parsing
Fruit executes corresponding reading or write-in storage operation；When odd result mistake, FPGA send odd failure flags to
CPU, CPU retransmit instruction to FPGA, return step (2)；If the continuous errors number of odd result is more than stipulated number,
Then CPU is restarted after reloading FPGA；
(4) it when FPGA executes write-in storage operation, executes and " three moulds --- read-around ratio is right --- is written, error is written again
The process of mould "；
(5) if operating result and FPGA are inconsistent from CPU reading data in step (4), FPGA is read from CPU again
Access evidence, and step (4) are repeated, if continuously repeating process more than stipulated number, CPU is restarted after reloading FPGA；
(6) " read three moulds --- comparison --- and the mould of error is written again " when FPGA executes reading storage operation, is executed
Process；
(7) if the local cyclic redundancy check for the data that CPU is obtained in step (6) and the cyclic redundancy check received are different
It causes, then CPU retransmits reading instruction, return step (6), if continuously repeating process more than stipulated number, CPU reloading
Restart after FPGA.
In the step (3), the process that FPGA parses the instruction received is as follows:
(3.1) FPGA first judges received instruction head, determines whether this instruction is effective, when instructing effective,
It enters step (3.2), when instruction ignore, enters step (3.3)；
(3.2) illegal command register is reset, then command content is parsed, decision instruction is to read memory to refer to
It enables or memory write instructs, if instruction is to read memory instructions, the memory starting address for including in acquisition instruction, according to
Byte number as defined in agreement reality is read between CPU and FPGA；If instruction is memory write instruction, include in acquisition instruction is wanted
The byte number and packet number of write-in when the two is consistent, are read by the packet number in instruction compared with the packet counter of FPGA from CPU
Respective byte data are taken, the next address of a memory write address space starts that specified byte number is written in the past, by FPGA
Packet counter add 1, the memory address space to be initially written according to three mould address allocation results assign initial value, the packet of FPGA
Counter initial value is 0；When the two is inconsistent, FPGA sends the inconsistent mark of packet number and retransmits instruction to CPU, CPU and give
FPGA；
(3.3) if consecutive invalid instruction number not up to limits number, FPGA is read again after illegal command register is added 1
The instruction for taking CPU to send, return step (3.1) rejudge；When consecutive invalid instruction number reach limitation number when, FPGA to
CPU write enters error flag and waits reloading.
In the step (4), FPGA executes the process of " mould that error is written in write-in three moulds --- read-around ratio is right --- again "
It is as follows:
(4.1) FPGA reads a data from CPU specified memory space, and data are sequentially written in three parts of ground of memory
In location space A, B, C；
(4.2) data in three addresses are sequential read out immediately after being written, and carry out step-by-step two from three calculating；
(4.3) step-by-step two from three calculated result is compared with the initial data read from CPU first, will when the two is inconsistent
Continuous inconsistent register i adds 1, enters step (4.4), when the two is consistent, enters step (4.5)；
(4.4) whether the counts of judgement continuous inconsistent register i at this time have reached stipulated number, if then to
CPU write enters error flag, waits reloading；Otherwise the memory write instruction that CPU is sent is received again, is repeated the above process；
(4.5) continuous inconsistent register i is reset, then by step-by-step two from three calculated result respectively with memory A, B
Compare with the data read in tri- block address of C, it is determined whether consistent respectively；It is inconsistent if it exists, then step-by-step two from three is calculated
As a result it is written in inconsistent memory mould address, and the inconsistent flag register j of this two from three is added 1, enter step
(4.6)；If consistent, (4.7) are entered step；
(4.6) judge whether the counts of continuous inconsistent register j have reached, if then entering error flag to CPU write,
Wait reloading；Otherwise (4.7) are entered step；
(4.7) be written into byte count register and add 1, and judge whether byte to be written has reached, if then FPGA to
Run succeeded mark and the inconsistent number of write operation two from three are written in CPU appropriate address；Otherwise memory write behaviour is continued to execute
Make.
In the step (6), the process that FPGA executes " read three moulds --- comparison --- and the mould of error is written again " is as follows:
(5.1) FPGA reads a number from the corresponding initial address of three mould address spaces A, B and C of memory respectively
According to；
(5.2) data taken out from three mould addresses are subjected to step-by-step two from three, obtained result is respectively the same as three moulds
The data read in address compare, it is determined whether and it is consistent respectively, it is inconsistent if it exists, (5.3) are entered step, if all consistent,
Then two from three result is written in CPU appropriate address, and byte count register to be read is added 1, subsequently into step
(5.5)；
(5.3) two from three result is written in inconsistent mould address, CPU appropriate address then is written into two from three result
In, and the inconsistent flag register k of this two from three is added 1, enter step (5.4)；
(5.4) judge whether the counts of the inconsistent flag register k of two from three have reached, if then entering mistake to CPU write
Accidentally indicate, waits reloading；Otherwise the reading memory instructions that CPU is sent are received again, are repeated the above process；
(5.5) if byte number to be read is unsatisfactory for requiring, read operation is continued to execute, until byte number to be read
It meets the requirements, run succeeded mark and the inconsistent number of read operation two from three are written into CPU appropriate address by FPGA.
In the step (4.7) and step (5.5), when FPGA be written into CPU appropriate address run succeeded indicate when, press
Local cyclic redundancy check is generated according to CRC-16, and is written in CPU appropriate address.
After CPU has received data, the local CPU cyclic redundancy check can be also generated, CPU judges the check code that itself is generated and comes
From the consistency of the check code of FPGA, judgement continuously verifies whether inconsistent number reaches limited number of times when the two is inconsistent, if
It is no, then CPU is verified into inconsistent register and add 1, and re-executes reading storage operation；If so, CPU control FPGA adds again
It carries, and restarts；
When the check code that CPU itself is generated is consistent with the check code from FPGA, it is clear that CPU is verified into inconsistent register
Zero, this reads memory operation instruction and is finished.
In the step (1), three parts of mould address spaces that do not connect are matched by same function distinguishing to the memory space of memory
A, the implementation method of B and C is as follows:
(8.1) address space size needed for determining；
(8.2) determine memory with the presence or absence of three and the above piece constituency, and if it exists, then by three moulds of same functional areas
Address A, B and C are respectively defined in three piece constituencies, mould address range division since address 0 in each constituency；
When only one piece constituency, if required address space is x, address offset amount is a and b, and a and b are much smaller than x,
And a is not equal to b, then the mould address A spatial dimension of the functional areas is defined as 0-x, mould address B spatial dimension is defined as (x+a)-
(2x+a), mould address C spatial dimension are defined as (2x+a+b)-(3x+a+b)；
When there are two piece constituency, by two mould address space allocations in a piece constituency, by another address space
Distribution is in another piece constituency, and two mould address spaces in same constituency distribute as follows, if as needed
Location space is y, and address offset amount is c, and c is much smaller than y, then the first of the piece constituency mould address space range is defined as 0-y, separately
One mould address space range is defined as (y+c)-(2y+c).
In the step (2), the instruction that CPU is sent to FPGA is 32, by big end mode storage content, i.e. address 0
Instruction leader will is stored to address 6, shows the type of instruction, the check bit of the storage of address 7 instruction odd.
Memory write is instructed, what address 8 to address 19 was stored is the number-of-packet of memory to be written, according to 1:1
Mapping, the sector address range represent writable packet number as 0-4095 packet；What address 20 to address 31 was stored is to read from CPU
Byte number, while be also intended to write-in memory byte number, mapped according to 1:1, which represents operable word
Joint number range is 1-4095；
For reading memory instructions, what address 9 to address 31 was stored is the initial address of memory to be read, according to 1:1
Mapping, then the addressable storage address of theoretical maximum is (223-1)。
The advantages of the present invention over the prior art are that:
(1) it is wrong to improve discovery for data inflow and outflow channel error correction path closed loop between CPU, FPGA and memory of the present invention
Probability accidentally, increases the validity of corrective action.
(2) present invention makes full use of the parallel operation characteristic of FPGA, and data manipulation path is short, and service speed is fast, and right
FPGA program does triplication redundancy, effectively improves storage system anti-single particle overturning ability.
(3) present invention utilizes data flow between the level-one error correction flowed of data between CPU and FPGA and FPGA and memory
Dynamic second level error correction, error correcting system are comprehensive, various, it is ensured that remain to correct back even if three groups of data of write-in memory malfunction
Come, it is strong that anti-single particle overturns effect capability.
Detailed description of the invention
Fig. 1 is present system structure chart；
Fig. 2 is a kind of storage system workflow of the closed loop multistage anti-single particle overturning effect based on FPGA of the present invention
Figure；
Fig. 3 is the level-one error correction flow chart of data flow channel between CPU and FPGA of the present invention；
Fig. 4 is FPGA memory write second level error correction process of the present invention；
Fig. 5 is that FPGA of the present invention reads memory second level error correction process.
Specific embodiment
The present invention will be further explained below with reference to the attached drawings.
As shown in Figure 1, the storage system for the closed loop multistage anti-single particle overturning effect that the invention proposes a kind of based on FPGA
System, including CPU, FPGA and memory；CPU is not direct to be connect with memory.CPU by send read or write memory instructions to
It is executed respectively after FPGA, FPGA successfully resolved and reads data write-in CPU or empty from CPU appropriate address from memory appropriate address
Between read data write-in memory operation.
It is illustrated in figure 2 a kind of storage system work of the closed loop multistage anti-single particle overturning effect based on FPGA of the present invention
Flow chart, before system operation, to the memory space of memory by same function distinguishing with three parts do not connect mould address space A, B and
C；After system brings into operation, determine when turn-on data reads and writes process by CPU.After CPU sends instructions to FPGA, FPGA is right first
Instruction head is judged determine whether this instruction is effective.When FPGA judges this instruction to read memory instructions, first will
Illegal command register is reset, meanwhile, command content is parsed, the memory the to be read starting for including in acquisition instruction
Address information resets byte count register to be read.Hereafter FPGA from corresponding three pieces of memory (be denoted as respectively A, B and
C a data) are read according to byte number as defined in agreement reality between CPU and FPGA in the corresponding initial address of modular space.By three
Data in a address carry out the differentiation of step-by-step two from three, and obtained result compares with the data read in three pieces of mould addresses respectively,
Determine whether consistent respectively.It is inconsistent if it exists, then the inconsistent flag register of this two from three is added 1, and by two from three knot
Fruit is written in inconsistent mould address, and two from three result is written in CPU appropriate address.After being finished, if word to be read
Section number is unsatisfactory for requiring, then continues to execute read operation, otherwise generates local cyclic redundancy check according to CRC-16 (i.e. 8005 types),
And it is written in CPU appropriate address together with the mark that runs succeeded, the inconsistent number of two from three.
As shown in Fig. 2, judging instruction head, after FPGA receives the instruction of CPU transmission if judging this instruction
After memory write instruction, illegal command register is reset first, while command content is parsed, wrapped in acquisition instruction
The information such as the byte number to be written and packet number that contain judge whether packet number and FPGA packet counter are consistent, by packet number when consistent
Inconsistent flag register and byte count register to be written are reset.Hereafter FPGA reads one from CPU specified memory space
Secondary data, and data are sequentially written in instruction corresponding memory corresponding three pieces of (i.e. A, B and C) moulds address, and be written ground
Location is the next address of a preceding memory write address space, and the packet counter of FPGA is added 1.The storage to be initially written
Device address space assigns initial value according to three mould address allocation results, and the packet counter initial value of FPGA is 0；Packet number and FPGA packet number meter
When number device is inconsistent, judge continuously whether inconsistent number reaches limited number of times to packet number, if otherwise FPGA is by the inconsistent mark of packet number
Will register receives the instruction of CPU transmission again after adding 1, enter error flag to CPU write if reaching limited number of times, waits and adding again
It carries；
The data in three mould addresses are sequential read out immediately after write-in, and carry out step-by-step two from three differentiation, are obtained
Result first compared with the initial data read from CPU, judgement in such cases continuous inconsistent time when the two is inconsistent
Whether number has reached stipulated number, if it is enters error flag to CPU write, waits reloading；Otherwise it is posted continuously inconsistent
Storage adds 1, and receives the instruction that CPU is sent again, repeats the above process.When two from three result and the original number from CPU reading
According to it is completely the same when, inconsistent register is reset, then by two from three result respectively with reading in three block address of memory
Data compare, it is determined whether consistent respectively.It is inconsistent if it exists, then the inconsistent flag register of this two from three is added 1, and will
Two from three result is written in inconsistent mould address.After being finished, if byte number to be written is unsatisfactory for requiring, continue
Write operation is executed, otherwise indicates that this write instruction is finished, enters the mark that runs succeeded to CPU write.
As shown in Fig. 2, judging instruction head after FPGA receives the instruction of CPU transmission, judging that this instruction is
After illegal command, illegal command register is added 1, if consecutive invalid instruction number not up to limits number, FPGA is re-read
The instruction that CPU is sent, rejudges.When consecutive invalid instruction count reaches limited number of times, FPGA enters error flag to CPU write
And wait reloading.
It is illustrated in figure 3 the level-one error correction flow chart of data flow channel between CPU and FPGA of the present invention, emphasis illustrates
The process of error-detection error-correction when data flow between CPU and FPGA.The FPGA read memory operation shown in Fig. 2 is finished, and will
It runs succeeded after mark write-in CPU, the reception of data and cyclic redundancy check is completed inside CPU, and according to CRC-16 (i.e. 8005 types)
The local CPU cyclic redundancy check is generated, consistency is carried out to the check code itself generated and the check code from FPGA inside CPU
Judgement.When the two is inconsistent judgement continuously verify it is inconsistent whether reach limited number of times, if it is not, CPU is then verified inconsistent post
Storage adds 1, and re-executes FPGA read operation；If so, CPU control FPGA reloading, and restart.When the two check code is consistent
When CPU verified into inconsistent register reset, this instruction execution finishes.To write operation instruction and illegal command shown in Fig. 3
Process flow with it is almost the same shown in Fig. 2.
Fig. 4 show the second level error correction flow chart of FPGA memory write of the present invention, and main includes " three moulds of write-in --- reading
Compare --- the mould of error is written again " process, first to memory address space according to functional requirement, each function zoning
For discontinuous three mould addresses (i.e. A, B and C).For each mould address, FPGA writes first when executing memory write operation
Enter mould A address date, mould B address date is then written, is ultimately written mould C address date.Immediately from mould after write operation
A, data are successively read in mould B and the address mould C, to the data step-by-step two from three of reading, two from three result is read with from CPU first
Initial data compare, when the two is inconsistent, continuous inconsistent register i is added 1, then judges continuous inconsistent register i
Whether number has reached, if then entering error flag to CPU write, waits reloading；Otherwise the memory write that CPU is sent is received again
Instruction, repeats the above process.It will continuous inconsistent register i if consistent with the initial data comparison result read from CPU
It resets, then respectively compared with the data read from mould A, mould B and mould C, when consistent respectively, be written into byte count and post
Storage adds 1, and continues to write to operation when byte to be written does not reach；When three moulds are there are when inconsistent mould, by two from three result
It is written in inconsistent mould address, covers the data that the address originally stored, and continuous inconsistent flag register j is added 1, it should
The size of data stored in register, show FPGA during write operation may by Single event upset effecf influenced
Degree.The data stored in inconsistent flag register are big, show the simple grain that FPGA may be subject to during write operation
Son overturning effects are big, conversely, then influence degree is small.When continuous j number of inconsistent register reaches stipulated number, to
CPU write enters error flag, and waits reloading, otherwise, continues to be written into byte count register and adds 1, and execute and write storage
Device operation generates local cyclic redundancy check according to CRC-16 (i.e. 8005 types) after all data are written, and is connected
With in instruction execution Success Flag and the inconsistent number write-in CPU of two from three.
Fig. 5 show the second level error correction flow chart that FPGA of the present invention reads memory, and main includes " three moulds of reading --- ratio
It is right --- the mould of error is written again " process, be the functional areas to memory according to Fig. 4 the method divide three moulds after,
The error correction and detection process of FPGA execution read operation.As described in Figure 2, FPGA is from memory by carrying out step-by-step after three mould address read-outing datas
Two from three knot is written into inconsistent mould address if two from three result and some mould content are inconsistent for two from three operation
Two from three result is written in CPU appropriate address, and the inconsistent flag register k of two from three is added 1 by fruit, and inconsistent mark is posted
The value reflection FPGA read operation of storage k is by Single event upset effecf effect.When k number of continuous inconsistent flag register
When reaching stipulated number, enters error flag to CPU write, and wait reloading, otherwise, continue to execute read memory operation, until
All data according to CRC-16 (i.e. 8005 types) generate local cyclic redundancy check after reading, and by it together with instruction execution
In Success Flag and the inconsistent number write-in CPU of two from three.
Level-one error correction of the present invention refers to the error correction channel that data flow between CPU and FPGA, and it is odd to send band comprising CPU
To FPGA, the result that FPGA carries out odd to the instruction received and judged instruction head is sent to for the instruction of check bit
CPU；CPU sends the data to FPGA, and data comparison result correctness mark is sent to CPU, the data comparison by FPGA
Refer to that the two from three result that will be obtained from memory write and the step-by-step of the CPU data sent compare one by one；FPGA is by data and CRC
Check results are sent to CPU, and CPU receives data and carries out CRC check to received data, two CRC check results are compared.
In addition, further including that number of operations control and CPU restart judgement, as shown in Figure 3.
Second level error correction of the present invention refers to the error correction channel that data flow between FPGA and memory, writes and deposits comprising FPGA
Reservoir " three moulds of write-in --- read-around ratio is right --- mould of error is written again " and reading memory " read three moulds --- ratio
It is right --- the mould of error is written again " process, as shown in Figure 4 and Figure 5.
In the present invention, the instruction that CPU is sent to FPGA is 32, by big end mode storage content, i.e. address 0 to address
6 storage instruction leader will show the type of instruction, the check bit of the storage of address 7 instruction odd；
Memory write is instructed, what address 8 to address 19 was stored is the number-of-packet of memory to be written, according to 1:1
Mapping, the sector address range represent writable packet number as 0-4095 packet；What address 20 to address 31 was stored is to read from CPU
Byte number, while be also intended to write-in memory byte number, mapped according to 1:1, which represents operable word
Joint number range is 1-4095, can adjust mapping ratio according to actual needs, such as maximum only to need to operate 2048 bytes, then
For FPGA when analyzing the instruction, every 2 bit indicates that the byte number for being actually subjected to operation is 1.
For reading memory instructions, what address 9 to address 31 was stored is the initial address of memory to be read, according to 1:1
Mapping, then the addressable storage address of theoretical maximum is (223-1).According to type of memory, by theoretical maximum accessible address
It is mapped as reality operationally location, if memory presses byte-accessed, and maximum only 128 kilobytes, then need to only be provided according to 1:1
Mapping, and address 15 to address 31 is effectively, address 9 to address 14 is invalid.
Match the realization side of three parts of mould address space A, B and C that do not connect by same function distinguishing to the memory space of memory
Method is as follows:
Address space size needed for determining first；
Then determine that memory whether there is three and the above piece constituency, and if it exists, then by three moulds of same functional areas
Address A, B and C are respectively defined in three piece constituencies, mould address range division since address 0 in each constituency；
When only one piece constituency, if required address space is x, address offset amount is a and b, and a and b are much smaller than x,
And a is not equal to b, then the mould address A spatial dimension of the functional areas is defined as 0-x, mould address B spatial dimension is defined as (x+a)-
(2x+a), mould address C spatial dimension are defined as (2x+a+b)-(3x+a+b)；
When there are two piece constituency, by two mould address space allocations in a piece constituency, by another address space
Distribution is in another piece constituency, and two mould address spaces in same constituency distribute as follows, if as needed
Location space is y, and address offset amount is c, and c is much smaller than y, then the first of the piece constituency mould address space range is defined as 0-y, separately
One mould address space range is defined as (y+c)-(2y+c).
Unspecified part of the present invention belongs to techniques well known.
Claims (10)
1. a kind of storage system of closed loop multistage anti-single particle overturning effect, it is characterised in that: including CPU, FPGA and memory,
CPU sends reading memory instructions to FPGA or memory write instruction, FPGA parse received instruction, hold after successfully resolved
CPU or the reading data write-in memory from CPU appropriate address space is written from data are read in memory appropriate address in row
Operation.
2. a kind of storage system implementation method of closed loop multistage anti-single particle overturning effect described in claim 1, feature exist
In:
(1) three parts of do not connect mould address space A, B and C are matched by same function distinguishing to the memory space of memory；
(2) CPU sends instructions to FPGA, and FPGA carries out odd to the instruction received, enters step (3)；
(3) if step (2) odd result is correct, FPGA parses the instruction received, is held according to parsing result
Row is corresponding to read or is written storage operation；When odd result mistake, FPGA sends odd failure flags to CPU, CPU
Instruction is retransmitted to FPGA, return step (2)；If the continuous errors number of odd result is more than stipulated number, CPU weight
Restart after load FPGA；
(4) when FPGA executes write-in storage operation, " mould that error is written in write-in three moulds --- read-around ratio is right --- again " is executed
Process；
(5) if operating result and FPGA are inconsistent from CPU reading data in step (4), FPGA reads number from CPU again
According to, and step (4) are repeated, if continuously repeating process more than stipulated number, CPU is restarted after reloading FPGA；
(6) stream of " read three moulds --- comparison --- and the mould of error is written again " when FPGA executes reading storage operation, is executed
Journey；
(7) if the local cyclic redundancy check for the data that CPU is obtained in step (6) and the cyclic redundancy check received are inconsistent,
CPU retransmits reading instruction, return step (6), if continuously repeating process more than stipulated number, after CPU reloads FPGA
Restart.
3. a kind of storage system implementation method of closed loop multistage anti-single particle overturning effect according to claim 2, special
Sign is: in the step (3), the process that FPGA parses the instruction received is as follows:
(3.1) FPGA first judges received instruction head, determines whether this instruction is effective, when instructing effective, enters
Step (3.2) when instruction ignore, enters step (3.3)；
(3.2) illegal command register is reset, then command content is parsed, decision instruction is to read memory instructions also
It is memory write instruction, if instruction is to read memory instructions, the memory starting address for including in acquisition instruction, according to CPU
Byte number as defined in agreement reality is read between FPGA；If instruction is memory write instruction, include in acquisition instruction will be write
The byte number and packet number entered when the two is consistent, is read by the packet number in instruction compared with the packet counter of FPGA from CPU
Respective byte data, the next address of a memory write address space starts that specified byte number is written in the past, by FPGA's
Packet counter adds 1, and initial value, the packet number of FPGA are assigned according to three mould address allocation results in the memory address space to be initially written
Counter initial value is 0；When the two is inconsistent, FPGA sends the inconsistent mark of packet number and retransmits instruction to FPGA to CPU, CPU；
(3.3) if consecutive invalid instruction number not up to limits number, FPGA is re-read after illegal command register is added 1
The instruction that CPU is sent, return step (3.1) rejudge；When consecutive invalid instruction number reaches limitation number, FPGA is to CPU
Write error mark simultaneously waits reloading.
4. a kind of storage system implementation method of closed loop multistage anti-single particle overturning effect according to claim 2, special
Sign is: in the step (4), FPGA executes the process of " mould that error is written in write-in three moulds --- read-around ratio is right --- again " such as
Under:
(4.1) FPGA reads a data from CPU specified memory space, and data are sequentially written in three parts of address skies of memory
Between in A, B, C；
(4.2) data in three addresses are sequential read out immediately after being written, and carry out step-by-step two from three calculating；
(4.3) step-by-step two from three calculated result is compared with the initial data read from CPU first, will be continuous when the two is inconsistent
Inconsistent register i adds 1, enters step (4.4), when the two is consistent, enters step (4.5)；
(4.4) continuously whether the counts of inconsistent register i have reached stipulated number at this time for judgement, if then to CPU write
Enter error flag, waits reloading；Otherwise the memory write instruction that CPU is sent is received again, is repeated the above process；
(4.5) continuous inconsistent register i is reset, then by step-by-step two from three calculated result respectively with memory A, B and C tri-
The data read in block address compare, it is determined whether consistent respectively；It is inconsistent if it exists, then step-by-step two from three calculated result is write
Enter in inconsistent memory mould address, and the inconsistent flag register j of this two from three is added 1, enters step (4.6)；If
Unanimously, then (4.7) are entered step；
(4.6) judge whether the counts of continuous inconsistent register j have reached, if then entering error flag to CPU write, wait
Reloading；Otherwise (4.7) are entered step；
(4.7) it is written into byte count register and adds 1, and judge whether byte to be written has reached, if then FPGA is to CPU phase
It answers and run succeeded mark and the inconsistent number of write operation two from three is written in address；Otherwise memory write operation is continued to execute.
5. a kind of storage system implementation method of closed loop multistage anti-single particle overturning effect according to claim 2, special
Sign is: in the step (6), the process that FPGA executes " read three moulds --- comparison --- and the mould of error is written again " is as follows:
(5.1) FPGA reads a data from the corresponding initial address of three mould address spaces A, B and C of memory respectively；
(5.2) data taken out from three mould addresses are subjected to step-by-step two from three, obtained result is respectively the same as three mould addresses
The data of middle reading compare, it is determined whether and it is consistent respectively, it is inconsistent if it exists, (5.3) are entered step, it, will if all consistent
Two from three result is written in CPU appropriate address, and byte count register to be read is added 1, subsequently into step (5.5)；
(5.3) two from three result is written in inconsistent mould address, then two from three result is written in CPU appropriate address,
And the inconsistent flag register k of this two from three is added 1, enter step (5.4)；
(5.4) judge whether the counts of the inconsistent flag register k of two from three have reached, if then entering wrong mark to CPU write
Will waits reloading；Otherwise the reading memory instructions that CPU is sent are received again, are repeated the above process；
(5.5) if byte number to be read is unsatisfactory for requiring, read operation is continued to execute, until byte number to be read meets
It is required that run succeeded mark and the inconsistent number of read operation two from three are written into CPU appropriate address by FPGA.
6. a kind of storage system implementation method of closed loop multistage anti-single particle overturning effect according to claim 4 or 5,
Be characterized in that: in the step (4.7) and step (5.5), when FPGA be written into CPU appropriate address run succeeded indicate when,
Local cyclic redundancy check is generated according to CRC-16, and is written in CPU appropriate address.
7. a kind of storage system implementation method of closed loop multistage anti-single particle overturning effect according to claim 6, special
Sign is: after CPU has received data, can also generate the local CPU cyclic redundancy check, CPU judges check code that itself is generated and comes from
The consistency of the check code of FPGA, judgement continuously verifies whether inconsistent number reaches limited number of times when the two is inconsistent, if it is not,
CPU is then verified into inconsistent register and adds 1, and re-executes reading storage operation；If so, CPU control FPGA reloading,
And restart；
When the check code that CPU itself is generated is consistent with the check code from FPGA, CPU is verified into inconsistent register and is reset,
This reads memory operation instruction and is finished.
8. a kind of storage system implementation method of closed loop multistage anti-single particle overturning effect according to claim 2, special
Sign is: in the step (1), to the memory space of memory by same function distinguishing with three parts of mould address space A that do not connect,
The implementation method of B and C is as follows:
(8.1) address space size needed for determining；
(8.2) determine memory with the presence or absence of three and the above piece constituency, and if it exists, then by three mould addresses of same functional areas
A, B and C is respectively defined in three piece constituencies, mould address range division since address 0 in each constituency；
When only one piece constituency, if required address space is x, address offset amount is that a and b, a and b are much smaller than x, and a is not
Equal to b, then the mould address A spatial dimension of the functional areas is defined as 0-x, mould address B spatial dimension is defined as (x+a)-(2x+
A), mould address C spatial dimension is defined as (2x+a+b)-(3x+a+b)；
When there are two piece constituency, by two mould address space allocations in a piece constituency, by another address space allocation
Two mould address spaces in another piece constituency, and in same constituency distribute as follows, if required address is empty
Between be y, address offset amount be c, c be much smaller than y, then the first of the piece constituency mould address space range is defined as 0-y, another
Mould address space range is defined as (y+c)-(2y+c).
9. a kind of storage system implementation method of closed loop multistage anti-single particle overturning effect according to claim 2, special
Sign is: in the step (2), the instruction that CPU is sent to FPGA is 32, by big end mode storage content, i.e., address 0 to
The storage of address 6 instruction leader will shows the type of instruction, the check bit of the storage of address 7 instruction odd.
10. a kind of storage system implementation method of closed loop multistage anti-single particle overturning effect according to claim 9, special
Sign is: memory write being instructed, what address 8 to address 19 was stored is the number-of-packet of memory to be written, and is reflected according to 1:1
It penetrates, which represents writable packet number as 0-4095 packet；What address 20 to address 31 was stored will read from CPU
Byte number, while it being also intended to the byte number of write-in memory, it is mapped according to 1:1, which represents operable byte
Number range is 1-4095；
For reading memory instructions, what address 9 to address 31 was stored is the initial address of memory to be read, and is mapped according to 1:1,
Then the addressable storage address of theoretical maximum is (223-1)。
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