CN110069892A - A kind of FPGA pin assignment design method and device - Google Patents
A kind of FPGA pin assignment design method and device Download PDFInfo
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- CN110069892A CN110069892A CN201910379084.7A CN201910379084A CN110069892A CN 110069892 A CN110069892 A CN 110069892A CN 201910379084 A CN201910379084 A CN 201910379084A CN 110069892 A CN110069892 A CN 110069892A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The present invention provides a kind of FPGA pin assignment design method and devices, this method comprises: determining design top layer input/output port message file, device usable pins message file corresponding with the model of used FPGA；It runs FPGA pin figure template database and generates script to read both of these documents, to generate the FPGA pin figure template database for graphic interface distribution FPGA pin；Operation have graphical interfaces FPGA pin assignment software, by the file of the database, design top layer input/output port FPGA pin assignment situation, shown with graphical interfaces；Operation according to outside based on graphical interfaces is modified the distribution condition and is updated into the file of above-mentioned database, to complete the design of FPGA pin assignment.First automation carries out pin predistribution, then artificial requirement-based progress pin assignment adjustment, so that artificial investment greatly reduces, therefore this programme can be improved FPGA design efficiency.
Description
Technical field
The present invention relates to field of computer technology, in particular to a kind of FPGA pin assignment design method and device.
Background technique
Currently, electronic information technology industry development is rapid, and it is higher and higher for the performance requirement of special chip, in integrated electricity
While road technique improves rapidly, the complexity of integrated circuit is in exponential increase, and the development & production period substantially extends, cannot be fine
The changeable market demand of adaptation.FPGA (Field-Programmable Gate Array, field programmable gate array) is mentioned
A kind of method that can flexibly realize circuit has been supplied, the contradiction between research and development of products period and properties of product is balanced.But due to
Many functions are all concentrated in one piece of FPGA, cause FPGA pin number huge.
Currently, during FPGA engineering Code Design, due to the placement position of input/output port be have it is interrelated
, different port has different level demands, and there are many classifications to meet different port needs, port pinout for FPGA pin
Distribution file needs are manually write manually entirely, therefore when modification Front-end Design code, placement-and-routing, input/output port adjustment etc.
When, staff needs repeatedly modification FPGA pin assignment file.
As it can be seen that this FPGA pin assignment design process is cumbersome and repeats, frequently, a large amount of time is wasted, FPGA is set
Count low efficiency.
Summary of the invention
The present invention provides a kind of FPGA pin assignment design method and devices, can be improved FPGA design efficiency.
In order to achieve the above object, the present invention is achieved through the following technical solutions:
On the one hand, the present invention provides a kind of FPGA pin assignment design methods, comprising:
S1: design top layer input/output port message file is determined, and determining corresponding with the model of used FPGA
Device usable pins message file；
S2: the FPGA pin figure template database that operation writes in advance generates script, to read the design top layer
Input/output port message file and the device usable pins message file distribute FPGA for graphic interface to generate
The FPGA pin figure template database of pin；
S3: the FPGA pin assignment software with graphical interfaces that operation writes in advance, by the FPGA pinouts
In the file of shape template database, top layer input/output port FPGA pin assignment situation is designed, is shown with graphical interfaces；
S4: the operation according to outside based on the graphical interfaces is modified the design top layer input/output port FPGA and is drawn
Foot distribution condition；
S5: it by the modified design top layer input/output port FPGA pin assignment situation, updates and arrives the FPGA
In the file of pin figure template database, to complete the design of FPGA pin assignment.
Further, the file content of the design top layer input/output port message file, comprising: the name of port set
Whether word, port set type, port set level, port set allow separation, any one in the name of port, port additional levels
Kind is a variety of；
The file content of the device usable pins message file, comprising: pin BANK number, pin type in BANK,
Any one or more in Pin description information, pin numbering.
Further, the S2 includes: the FPGA pin figure template database generation script that operation writes in advance, with
Execute operations described below:
The file content of the design top layer input/output port message file is retrieved, to be single with port set
Position establish level one data structure, secondary data structure is established as unit of port, wherein any level one data structure include to
A few secondary data structure, any level one data structure preserve the information of Single port group, and any secondary data structure is equal
Preserve the information of Single port；
The file content of the device usable pins message file is retrieved, to establish level-one as unit of BANK
Data structure establishes secondary data structure as unit of device usable pins, wherein any level one data structure includes at least
One secondary data structure, any level one data structure preserve the information of a BANK, and any secondary data structure saves
There is the information of a device usable pins；
By searching for established data structure, port set is ranked up；
According to port set ranking results, successively retrieval meets the pin of each port requirements, in each port set
Each port carries out pin predistribution, and the pin assignment situation of each port is corresponded to the secondary data for being stored in each port
In structure；
The call format of graphics template database, the data structure that will be obtained are directed to according to the FPGA pin assignment software
In data-printing output, with generate for graphic interface distribution FPGA pin FPGA pin figure template database.
Further, the file content to the device usable pins message file is retrieved, comprising: using just
Then expression formula retrieves the file content of the device usable pins message file.
Further, described by searching for established data structure, port set is ranked up, comprising: according to default
Port set ordering rule port set is ranked up by searching for established data structure so that preceding port of sorting
Priority of the priority of group not less than the posterior port set that sorts；
Accordingly, the successively retrieval meets the pins of each port requirements, comprising: according to priority from it is high to low,
BANK number is from down to high sequence, and successively retrieval meets the pin of each port requirements.
Further, the data-printing output in the data structure that will be obtained, comprising: printf function is used, it will
Data-printing output in obtained data structure.
Further, after completion FPGA pin assignment design, further comprise: according to the FPGA pinouts
The file of shape template database is generated for this unbound document of the XDC of VIVADO or for this unbound document of the UCF of ISE.
On the other hand, the present invention provides a kind of FPGA pin assignments to design device, comprising:
Determination unit, for determining design top layer input/output port message file, and determination with used FPGA's
The corresponding device usable pins message file of model；
Running unit generates script for running the FPGA pin figure template database write in advance, to read
Design top layer input/output port message file and the device usable pins message file are stated, is used for graphical boundary to generate
The FPGA pin figure template database of face distribution FPGA pin；
Processing unit will be described for running the FPGA pin assignment software with graphical interfaces write in advance
In the file of FPGA pin figure template database, top layer input/output port FPGA pin assignment situation is designed, with figure circle
Face is shown；Operation according to outside based on the graphical interfaces is modified the design top layer input/output port FPGA and is drawn
Foot distribution condition；By the modified design top layer input/output port FPGA pin assignment situation, updates and arrive the FPGA
In the file of pin figure template database, to complete the design of FPGA pin assignment.
Further, the file content of the design top layer input/output port message file, comprising: the name of port set
Whether word, port set type, port set level, port set allow separation, any one in the name of port, port additional levels
Kind is a variety of；
The file content of the device usable pins message file, comprising: pin BANK number, pin type in BANK,
Any one or more in Pin description information, pin numbering.
Further, the running unit is generated for running the FPGA pin figure template database write in advance
Script, to execute operations described below: the file content of the design top layer input/output port message file is retrieved, thus
Level one data structure is established as unit of port set, secondary data structure is established as unit of port, wherein any level one data
Structure includes at least one secondary data structure, and any level one data structure preserves the information of Single port group, and any two
Grade data structure preserves the information of Single port；The file content of the device usable pins message file is retrieved,
To establish level one data structure as unit of BANK, secondary data structure is established as unit of device usable pins, wherein appoint
One level one data structure includes at least one secondary data structure, and any level one data structure preserves the letter of a BANK
Breath, any secondary data structure preserve the information of a device usable pins；By searching for established data structure, opposite end
Mouth group is ranked up；According to port set ranking results, successively retrieval meets the pin of each port requirements, to each port set
Interior each port carries out pin predistribution, and the pin assignment situation of each port is corresponded to the second level for being stored in each port
In data structure；The call format of graphics template database, the data that will be obtained are directed to according to the FPGA pin assignment software
Data-printing output in structure, to generate the FPGA pin figure template data for graphic interface distribution FPGA pin
Library.
Further, the running unit, for using regular expression, to the device usable pins message file
File content is retrieved.
Further, the running unit is used for according to preset port set ordering rule, by searching for established number
According to structure, port set is ranked up, so that the priority for the preceding port set that sorts is not less than the posterior port set that sorts
Priority；According to priority from high to low, BANK number from down to high sequence, successively retrieval meets drawing for each port requirements
Foot.
Further, the running unit, for using printf function, by the data-printing in obtained data structure
Output.
Further, which designs device further include: generation unit, for according to the FPGA pinouts
The file of shape template database is generated for this unbound document of the XDC of VIVADO or for this unbound document of the UCF of ISE.
The present invention provides a kind of FPGA pin assignment design method and devices, this method comprises: determining that design top layer is defeated
Enter output port message file, device usable pins message file corresponding with the model of used FPGA；Operation FPGA draws
Foot graphics template database generates script to read both of these documents, to generate for graphic interface distribution FPGA pin
FPGA pin figure template database；Operation has the FPGA pin assignment software of graphical interfaces, by the file of the database
In, design top layer input/output port FPGA pin assignment situation, shown with graphical interfaces；Figure circle is based on according to outside
The operation in face is modified the distribution condition and is updated into the file of above-mentioned database, to complete the design of FPGA pin assignment.First certainly
Dynamicization carries out pin predistribution, then artificial requirement-based progress pin assignment adjustment, so that artificial investment greatly reduces, therefore energy of the present invention
Enough improve FPGA design efficiency.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is the present invention
Some embodiments for those of ordinary skill in the art without creative efforts, can also basis
These attached drawings obtain other attached drawings.
Fig. 1 is a kind of flow chart for FPGA pin assignment design method that one embodiment of the invention provides；
Fig. 2 is the flow chart for another FPGA pin assignment design method that one embodiment of the invention provides；
Fig. 3 is a kind of schematic diagram for graphical interfaces that one embodiment of the invention provides；
Fig. 4 is the schematic diagram for another graphical interfaces that one embodiment of the invention provides；
Fig. 5 is a kind of schematic diagram for FPGA pin assignment design device that one embodiment of the invention provides；
Fig. 6 is the schematic diagram for another FPGA pin assignment design device that one embodiment of the invention provides.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments, based on the embodiments of the present invention, those of ordinary skill in the art
Every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
As shown in Figure 1, may include following step the embodiment of the invention provides a kind of FPGA pin assignment design method
It is rapid:
Step 101: determining design top layer input/output port message file, and the determining model phase with used FPGA
Corresponding device usable pins message file.
Step 102: the FPGA pin figure template database that operation writes in advance generates script, to read the design
Top layer input/output port message file and the device usable pins message file distribute to generate for graphic interface
The FPGA pin figure template database of FPGA pin.
Step 103: the FPGA pin assignment software with graphical interfaces that operation writes in advance draws the FPGA
In the file of foot graphics template database, top layer input/output port FPGA pin assignment situation is designed, is carried out with graphical interfaces
Display.
Step 104: the design top layer input/output port is modified in the operation according to outside based on the graphical interfaces
FPGA pin assignment situation.
Step 105: the modified design top layer input/output port FPGA pin assignment situation is updated to described
In the file of FPGA pin figure template database, to complete the design of FPGA pin assignment.
The embodiment of the invention provides a kind of FPGA pin assignment design methods, this method comprises: determining that design top layer is defeated
Enter output port message file, device usable pins message file corresponding with the model of used FPGA；Operation FPGA draws
Foot graphics template database generates script to read both of these documents, to generate for graphic interface distribution FPGA pin
FPGA pin figure template database；Operation has the FPGA pin assignment software of graphical interfaces, by the file of the database
In, design top layer input/output port FPGA pin assignment situation, shown with graphical interfaces；Figure circle is based on according to outside
The operation in face is modified the distribution condition and is updated into the file of above-mentioned database, to complete the design of FPGA pin assignment.First certainly
Dynamicization carries out pin predistribution, then artificial requirement-based progress pin assignment adjustment, so that artificial investment greatly reduces, therefore the present invention is real
Applying example can be improved FPGA design efficiency.
In detail, the distribution between pin assignment, that is, several input/output ports and several FPGA pins, in this way, please referring to
Step 101 is stated, needs to predefine port information and pinout information.
For example, in an embodiment of the invention, the file content of the design top layer input/output port message file,
Include: whether name, port set type, port set level, the port set of port set allow separation, the name of port, port attached
It is powered on any one or more in flat.
For example, in an embodiment of the invention, the file content of the device usable pins message file, comprising: draw
Foot BANK number, pin type in BANK, Pin description information, any one or more in pin numbering.
In detail, Xilinx is a supplier of programmable logic total solution.In an embodiment of the invention,
It, can in order to illustrate a kind of determining device when this pin assignment design method is applied to the project using Xilinx FPGA design
With the possibility implementation of pinout information file, so, in above-mentioned steps 101, the model phase of the determination and used FPGA
Corresponding device usable pins message file, comprising: according to the model of used FPGA, used in document from Xilinx device,
Obtain encapsulation corresponding to the model and pin (Packaging and Pinouts) information, and according to the encapsulation got and
Pinout information establishes device usable pins message file.
Above-mentioned steps 102 are please referred to, needs to write FPGA pin figure template database in advance and generates script, use the foot
Originally the FPGA pin figure template database for graphic interface distribution FPGA pin can be generated.
In detail, the script file can be used tcl (Tool Command Language, Tool Command Language),
Python etc. is realized.In detail, Python is a kind of computer programming language.
In an embodiment of the invention, the possibility implementation of database is generated in order to illustrate a kind of Run Script,
So the step 102 includes: the FPGA pin figure template database generation script that operation writes in advance, under executing
State operation:
The file content of the design top layer input/output port message file is retrieved, to be single with port set
Position establish level one data structure, secondary data structure is established as unit of port, wherein any level one data structure include to
A few secondary data structure, any level one data structure preserve the information of Single port group, and any secondary data structure is equal
Preserve the information of Single port；
The file content of the device usable pins message file is retrieved, to establish level-one as unit of BANK
Data structure establishes secondary data structure as unit of device usable pins, wherein any level one data structure includes at least
One secondary data structure, any level one data structure preserve the information of a BANK, and any secondary data structure saves
There is the information of a device usable pins；
By searching for established data structure, port set is ranked up；
According to port set ranking results, successively retrieval meets the pin of each port requirements, in each port set
Each port carries out pin predistribution, and the pin assignment situation of each port is corresponded to the secondary data for being stored in each port
In structure；
The call format of graphics template database, the data structure that will be obtained are directed to according to the FPGA pin assignment software
In data-printing output, with generate for graphic interface distribution FPGA pin FPGA pin figure template database.
In detail, the information of port set may include the name of port set, port set type, port set level, port set
Whether allow to separate etc..
In detail, the information of port may include the name of port, port additional electrical equality.
In detail, the information of BANK may include pin BANK number, pin type etc. in BANK.For example, drawing in BANK
Pin class type is HP type or HR type, or still GTH type.
In detail, the information of device usable pins may include Pin description information, pin numbering etc..
In detail, by generating this FPGA pin figure template database, be equivalent to complete automation pin divide in advance
Match.In the embodiment of the present invention, automation pin predistribution is carried out according to default allocation rule first, it later can be through graphical interfaces
This predistribution result is shown to user, so that user on demand can artificially adjust pin assignment.Referring to FIG. 2, i.e.
It can be the example of a graphical interfaces.This example can be for the example after predistribution, or any adjustment of user
Example afterwards.
Referring to FIG. 2, interface example shown in Fig. 2 shows current pin assignment situation from top layer.It is shown in Fig. 2 several
For the button block of BANK, show the type of the BANK on each button block, for example can be HP, HR, GTH etc.；Type
The number of back is the number of BANK；In subsequent first square brackets, the number before "/" is the used number of pins of BANK,
Total number of pins that number after "/" is BANK；Number in subsequent second square brackets is that user's expectation is placed on the BANK's
Residue does not complete the pin number of distribution.
For example, total number of pins of a BANK is 30, but user expects to have 40 pins and is put into the BANK, in this way,
It is successfully put into the BANK in 30 wherein, another 10 when be put into the BANK not successfully, second square brackets of button block
In number be 10.
When clicking any button block for BANK, next graphical interfaces can be entered, to draw to each under the BANK
Foot is shown, for example, content shown in Fig. 3 can be for next graphical interfaces.
In Fig. 2, bottom is there are also remaining button block and completes distribution button block.The number shown on remaining button block is institute
There is unallocated pin number, the detailed name letter of all unallocated pins can be shown in next graphical interfaces by clicking the button block
Breath.After being assigned, user can click completion distribution button block, thus automatic production constraint file.
Referring to FIG. 3, the number after byte can be the number of each byte in BANK.Number in circle is that pin exists
Number in byte, it is round after number in rectangle frame be pin name.Each circle is corresponding with Single port, if therefore the end
Mouth is currently unallocated pin, then is empty in the rectangle frame of back.
Fig. 3 is shown at intermediate region, and user's expectation is placed on the pinout information of remaining unallocated pin in the BANK.Herein
Number is consistent in the pin number of display, with second square brackets of the button block of the BANK.
Remaining IO number, i.e. total surplus pin number are shown at Fig. 3 lower zone, it can be for residue in other all BANK not
Distribute the summation of pin number.It clicks the button, can also show all unallocated pinout informations in region above.
Referring to FIG. 3, top can have been distributed to the button block point of I/O pin when user needs to manually adjust pin assignment
Firmly and it is dragged to lower section unassigned zone, the button block point of any I/O pin in the unassigned zone of lower section can also be lived and is dragged to
In one rectangle frame of top, pin assignment is completed.
Based on above content, in embodiments of the present invention, further, when executing pin predistribution, if there is can not
The input/output port that pin assignment is completed according to predetermined policy can then be abandoned carrying out pin assignment to the input/output port.
For example, referring to FIG. 3, if an input/output port does not carry out pin assignment, the rectangle frame on the corresponding round right side in the port
In be empty.In this way, user manually can carry out pin assignment to the port on demand, such as can be by a pin in the intermediate region Fig. 3
Button block, drag in the rectangle frame on the corresponding round right side in the port, taking human as the matching relationship established between the two.
In detail, when Run Script, regular expression can be used to carry out information retrieval, use priority sequence carries out pin
Predistribution carries out result printing using printf function.
Therefore, it is based on above content, it is in an embodiment of the invention, described to the device usable pins message file
File content retrieved, comprising: use regular expression, to the file content of the device usable pins message file into
Row retrieval.
It is in an embodiment of the invention, described by searching for established data structure based on above content, to port
Group is ranked up, comprising: according to preset port set ordering rule, by searching for established data structure, to port set into
Row sequence, so that priority of the priority for the preceding port set that sorts not less than the posterior port set that sorts；
Accordingly, the successively retrieval meets the pins of each port requirements, comprising: according to priority from it is high to low,
BANK number is from down to high sequence, and successively retrieval meets the pin of each port requirements.
For example, can require port set not allows the highest priority of separation, and remaining port set can be according to required
Pin BANK byte orderings, for example, the priority of HP type pin is higher than the priority of HR type pin.
Based on above content, in an embodiment of the invention, the data-printing in the data structure that will be obtained is defeated
Out, comprising: use printf function, the data-printing in obtained data structure is exported.
Above-mentioned steps 103 are please referred to, need to write FPGA pin assignment software in advance.It, can be by FPGA using the software
In pin figure template database file, it is aobvious with graphical interfaces to design top layer input/output port FPGA pin assignment situation
Show.In this way, user can operate graphic interface, to modify pin assignment on demand.
In detail, Visual Basic language can be used to write software.
Above-mentioned steps 104 are please referred to, after being shown with graphical interfaces, user pre-allocates situation by observing existing pin,
It is allocated adjustment using graphical interfaces as needed, with complete design top layer input/output port pin assignment.Certainly, please join
Above-mentioned steps 105 are examined, the pin allocation information of change is automatically updated to arrive FPGA pin figure template database file.
In detail, user can freely adjust the position of each FPGA pin before ultimately generating file, to realize most
Excellent FPGA pin assignment.
After completing pin assignment, the XDC for VIVADO software or the UCF constraint text for ISE are produced as needed
Part.Therefore, in an embodiment of the invention, after the step 105, further comprise: according to the FPGA pinouts
The file of shape template database is generated for this unbound document of the XDC of VIVADO or for this unbound document of the UCF of ISE.
Unbound document based on generation can carry out the practical operation of FPGA pin assignment under corresponding the integration environment.
In detail, VIVADO software is an integrated design enviroment of FPGA manufacturer publication, XDC (Xilinx Design
It Constraints) is its unbound document.
In detail, ISE (Integrated Software Environment, integrated software conditions with micro) is Xilinx company
Hardware design tool, UCF be its unbound document.
Based on above-mentioned full content it is found that one embodiment of the invention can be soft by using automatized script and graphical interfaces
Part, according to design top layer input/output port message file and device usable pins message file, automation is generated and is used for
The XDC of VIVADO software or UCF unbound document for ISE.When design modification Front-end Design code, port level standard, end
Mouth name, port number etc., when so that needing to modify port pinout distribution file, it is only necessary to re-call automatized script, make
FPGA pin assignment is carried out with graphic interface software, generates new port pinout distribution file.In this way, greatly improved
The efficiency of FPGA design, accelerates project process.
In conclusion this FPGA pin assignment design based on graphical interfaces provided in an embodiment of the present invention, Ke Yishi
For using the project of Xilinx FPGA design, it can be achieved that automation predistribution pin, is divided based on graphic interface adjustment pin
Match, is automatically performed the generation of pin assignment unbound document, improves the automatization level of FPGA design, reduce mistake caused by manual operation
Accidentally, accelerate project development progress.
As shown in figure 4, one embodiment of the invention provides another FPGA pin assignment design method, to be applied to make
For project with Xilinx FPGA design, specifically includes the following steps:
Step 401: using Python, write FPGA pin figure template database and generate script.
Step 402: using Visual Basic language, write the FPGA pin assignment software with graphical interfaces.
Step 403: determining design top layer input/output port message file.
In the embodiment of the present invention, the file content of this file includes: the name of port set, port set type, port set
Whether level, port set allow separation, the name of port, port additional levels.
Step 404: being obtained corresponding to the model according to the model of used FPGA from Xilinx device using in document
Encapsulation and pinout information establish device usable pins message file and according to the encapsulation and pinout information got.
In the embodiment of the present invention, the file content of this file includes: pin BANK number, pin type in BANK, draws
Foot description information, pin numbering.
Step 405: operation FPGA pin figure template database generates script, to execute step 406 to step 410.
Step 406: the file content of design top layer input/output port message file being retrieved, thus with port set
Level one data structure is established for unit, secondary data structure is established as unit of port, wherein any level one data structure is wrapped
Containing at least one secondary data structure, any level one data structure preserves the information of Single port group, any secondary data knot
Structure preserves the information of Single port.
Step 407: regular expression is used, the file content of device usable pins message file is retrieved, thus
Level one data structure is established as unit of BANK, secondary data structure is established as unit of device usable pins, wherein Ren Yiyi
Grade data structure includes at least one secondary data structure, and any level one data structure preserves the information of a BANK, is appointed
One secondary data structure preserves the information of a device usable pins.
Step 408: according to preset port set ordering rule, by searching for established data structure, to port set into
Row sequence, so that priority of the priority for the preceding port set that sorts not less than the posterior port set that sorts.
Step 409: according to port set ranking results, according to priority from high to low, BANK number from down to high sequence,
Successively retrieval meets the pin of each port requirements, to carry out pin predistribution to each port in each port set, and will
The pin assignment situation correspondence of each port is stored in the secondary data structure of each port.
Step 410: being directed to the call format of graphics template database according to FPGA pin assignment software, use printf letter
Number exports the data-printing in obtained data structure, is drawn with generating for the FPGA of graphic interface distribution FPGA pin
Foot graphics template database.
Step 411: operation has the FPGA pin assignment software of graphical interfaces, by FPGA pin figure template database
File in, design top layer input/output port FPGA pin assignment situation, shown with graphical interfaces.
Step 412: the operation according to outside based on graphical interfaces, modification design top layer input/output port FPGA pin point
With situation.
Step 413: by modified design top layer input/output port FPGA pin assignment situation, updating and arrive FPGA pin
In the file of graphics template database, to complete the design of FPGA pin assignment.
Step 414: according to the file of FPGA pin figure template database, generating and be used for this constraint of the XDC of VIVADO
File.
This FPGA pin assignment design method described in the embodiment of the present invention, easy to implement, process is simple, efficiently steady
It is fixed, it can substantially shorten the time of manual compiling port pinout distribution file, improve FPGA design efficiency.Certainly, because of artificial behaviour
Work greatly reduces, therefore correspondingly reduces the easy bring mistake of manual operation institute.
As shown in figure 5, one embodiment of the invention provides a kind of FPGA pin assignment design device, may include:
Determination unit 501, for determining design top layer input/output port message file, and determining and used FPGA
The corresponding device usable pins message file of model；
Running unit 502 generates script for running the FPGA pin figure template database write in advance, to read
The design top layer input/output port message file and the device usable pins message file, to generate for graphical
The FPGA pin figure template database of interfacial distribution FPGA pin；
Processing unit 503, for running the FPGA pin assignment software with graphical interfaces write in advance, by institute
It states in the file of FPGA pin figure template database, design top layer input/output port FPGA pin assignment situation, with figure
Interface is shown；The design top layer input/output port FPGA is modified in operation according to outside based on the graphical interfaces
Pin assignment situation；The modified design top layer input/output port FPGA pin assignment situation is updated to described
In the file of FPGA pin figure template database, to complete the design of FPGA pin assignment.
In an embodiment of the invention, the file content of the design top layer input/output port message file, comprising:
Whether name, port set type, port set level, the port set of port set allow separation, the name of port, port additional levels
In any one or more；
The file content of the device usable pins message file, comprising: pin BANK number, pin type in BANK,
Any one or more in Pin description information, pin numbering.
In an embodiment of the invention, the running unit 502, for running the FPGA pin figure write in advance
Template database generates script, to execute operations described below: in the file of the design top layer input/output port message file
Appearance is retrieved, to establish level one data structure as unit of port set, secondary data structure is established as unit of port,
In, any level one data structure includes at least one secondary data structure, and any level one data structure preserves Single port
The information of group, any secondary data structure preserve the information of Single port；To the text of the device usable pins message file
Part content is retrieved, to establish level one data structure as unit of BANK, establishes second level as unit of device usable pins
Data structure, wherein any level one data structure includes at least one secondary data structure, and any level one data structure is protected
There is the information of a BANK, any secondary data structure preserves the information of a device usable pins；By searching for establishing
Data structure, port set is ranked up；According to port set ranking results, successively retrieval meets drawing for each port requirements
Foot to carry out pin predistribution to each port in each port set, and the pin assignment situation of each port is corresponded to and is protected
There are in the secondary data structure of each port；The format of graphics template database is directed to according to the FPGA pin assignment software
It is required that the data-printing in obtained data structure is exported, to generate the FPGA for graphic interface distribution FPGA pin
Pin figure template database.
In an embodiment of the invention, the running unit 502 can to the device for using regular expression
It is retrieved with the file content of pinout information file.
In an embodiment of the invention, the running unit 502, for leading to according to preset port set ordering rule
It crosses and searches established data structure, port set is ranked up, so that the priority for the preceding port set that sorts is not less than row
The priority of the posterior port set of sequence；According to priority from high to low, BANK number from down to high sequence, successively retrieval meets
The pin of each port requirements.
In an embodiment of the invention, the running unit 502, for using printf function, the data that will be obtained
Data-printing output in structure.
In an embodiment of the invention, referring to FIG. 6, FPGA pin assignment design device can also include: to generate
Unit 601 generates for the file according to the FPGA pin figure template database and is used for this constraint of the XDC of VIVADO
File or for this unbound document of the UCF of ISE.
The contents such as the information exchange between each unit, implementation procedure in above-mentioned apparatus, due to implementing with the method for the present invention
Example is based on same design, and for details, please refer to the description in the embodiment of the method for the present invention, and details are not described herein again.
In conclusion the embodiment of the present invention have it is at least following the utility model has the advantages that
1, in the embodiment of the present invention, design top layer input/output port message file, the model with used FPGA are determined
Corresponding device usable pins message file；Operation FPGA pin figure template database generates script to read the two texts
Part, to generate the FPGA pin figure template database for graphic interface distribution FPGA pin；Operation has figure circle
The FPGA pin assignment software in face, by the file of the database, design top layer input/output port FPGA pin assignment feelings
Condition is shown with graphical interfaces；Operation according to outside based on graphical interfaces is modified the distribution condition and is updated to above-mentioned number
According in the file in library, designed with completing FPGA pin assignment.First automation carries out pin predistribution, then artificial requirement-based carry out pin
Distribution adjustment, so that artificial investment greatly reduces, therefore the embodiment of the present invention can be improved FPGA design efficiency.
2, one embodiment of the invention can be by using automatized script and graphic interface software, according to design top layer input
Output port message file and device usable pins message file, automation generate the XDC for VIVADO software or are used for ISE
UCF unbound document.When design modification Front-end Design code, port level standard, port name, port number etc., so that needing
When modifying port pinout distribution file, it is only necessary to re-call automatized script, carry out FPGA using graphic interface software and draw
Foot distribution generates new port pinout distribution file.In this way, the efficiency of FPGA design greatly improved, project is accelerated
Progress.
3, it is provided in an embodiment of the present invention this based on graphical interfaces FPGA pin assignment design, can be adapted for using
The project of Xilinx FPGA design is, it can be achieved that automation predistribution pin, adjusts pin assignment based on graphic interface, automatically
It completes pin assignment unbound document to generate, improves the automatization level of FPGA design, reduce mistake caused by manual operation, accelerate
Project development progress.
4, this FPGA pin assignment design method described in the embodiment of the present invention, easy to implement, process is simple, efficiently steady
It is fixed, it can substantially shorten the time of manual compiling port pinout distribution file, improve FPGA design efficiency.Certainly, because of artificial behaviour
Work greatly reduces, therefore correspondingly reduces the easy bring mistake of manual operation institute.
It should be noted that, in this document, such as first and second etc relational terms are used merely to an entity
Or operation is distinguished with another entity or operation, is existed without necessarily requiring or implying between these entities or operation
Any actual relationship or order.Moreover, the terms "include", "comprise" or its any other variant be intended to it is non-
It is exclusive to include, so that the process, method, article or equipment for including a series of elements not only includes those elements,
It but also including other elements that are not explicitly listed, or further include solid by this process, method, article or equipment
Some elements.In the absence of more restrictions, the element limited by sentence " including one ", is not arranged
Except there is also other identical factors in the process, method, article or apparatus that includes the element.
Those of ordinary skill in the art will appreciate that: realize that all or part of the steps of above method embodiment can pass through
The relevant hardware of program instruction is completed, and program above-mentioned can store in computer-readable storage medium, the program
When being executed, step including the steps of the foregoing method embodiments is executed；And storage medium above-mentioned includes: ROM, RAM, magnetic disk or light
In the various media that can store program code such as disk.
Finally, it should be noted that the foregoing is merely presently preferred embodiments of the present invention, it is merely to illustrate skill of the invention
Art scheme, is not intended to limit the scope of the present invention.Any modification for being made all within the spirits and principles of the present invention,
Equivalent replacement, improvement etc., are included within the scope of protection of the present invention.
Claims (10)
1. a kind of field programmable gate array FPGA pin assignment design method characterized by comprising
S1: it determines design top layer input/output port message file, and determines device corresponding with the model of used FPGA
Part usable pins message file；
S2: the FPGA pin figure template database that operation writes in advance generates script, to read the design top layer input
Output port message file and the device usable pins message file distribute FPGA pin for graphic interface to generate
FPGA pin figure template database；
S3: the FPGA pin assignment software with graphical interfaces that operation writes in advance, by the FPGA pin figure mould
In the file of plate database, top layer input/output port FPGA pin assignment situation is designed, is shown with graphical interfaces；
S4: the design top layer input/output port FPGA pin point is modified in the operation according to outside based on the graphical interfaces
With situation；
S5: it by the modified design top layer input/output port FPGA pin assignment situation, updates and arrives the FPGA pin
In the file of graphics template database, to complete the design of FPGA pin assignment.
2. the method according to claim 1, wherein
The file content of the design top layer input/output port message file, comprising: the name of port set, port set type,
Whether port set level, port set allow separation, any one or more in the name of port, port additional levels；
The file content of the device usable pins message file, comprising: pin type, pin in pin BANK number, BANK
Any one or more in description information, pin numbering.
3. the method according to claim 1, wherein
The S2 includes: the FPGA pin figure template database generation script that operation writes in advance, to execute operations described below:
The file content of the design top layer input/output port message file is retrieved, to be built as unit of port set
Vertical level one data structure, establishes secondary data structure, wherein any level one data structure includes at least one as unit of port
A secondary data structure, any level one data structure preserve the information of Single port group, and any secondary data structure saves
There is the information of Single port；
The file content of the device usable pins message file is retrieved, to establish level one data as unit of BANK
Structure establishes secondary data structure as unit of device usable pins, wherein any level one data structure includes at least one
Secondary data structure, any level one data structure preserve the information of a BANK, and any secondary data structure preserves one
The information of device usable pins；
By searching for established data structure, port set is ranked up；
According to port set ranking results, successively retrieval meets the pin of each port requirements, to each in each port set
Port carries out pin predistribution, and the pin assignment situation of each port is corresponded to the secondary data structure for being stored in each port
In；
The call format of graphics template database is directed to according to the FPGA pin assignment software, it will be in obtained data structure
Data-printing output, to generate the FPGA pin figure template database for graphic interface distribution FPGA pin.
4. according to the method described in claim 3, it is characterized in that,
The file content to the device usable pins message file is retrieved, comprising: regular expression is used, to institute
The file content for stating device usable pins message file is retrieved；
And/or
It is described by searching for established data structure, port set is ranked up, comprising: according to preset port set sort advise
Then, by searching for established data structure, port set is ranked up, so that the priority for the preceding port set that sorts is not small
In the priority for the posterior port set that sorts；
Accordingly, the successively retrieval meets the pin of each port requirements, comprising: compiles according to priority from high to low, BANK
Number from down to high sequence, successively retrieval meets the pin of each port requirements；
And/or
Data-printing output in the data structure that will be obtained, comprising: use printf function, the data structure that will be obtained
In data-printing output.
5. according to claim 1 to any method in 4, which is characterized in that
After completion FPGA pin assignment design, further comprise:
According to the file of the FPGA pin figure template database, generates and be used for this unbound document of the XDC of VIVADO or use
In this unbound document of the UCF of ISE.
6. a kind of field programmable gate array FPGA pin assignment designs device characterized by comprising
Determination unit, for determining design top layer input/output port message file, and the determining model with used FPGA
Corresponding device usable pins message file；
Running unit generates script for running the FPGA pin figure template database write in advance, to set described in reading
Top layer input/output port message file and the device usable pins message file are counted, to generate for graphic interface point
FPGA pin figure template database with FPGA pin；
Processing unit, for running the FPGA pin assignment software with graphical interfaces write in advance, by the FPGA
In the file of pin figure template database, design top layer input/output port FPGA pin assignment situation, with graphical interfaces into
Row display；The design top layer input/output port FPGA pin point is modified in operation according to outside based on the graphical interfaces
With situation；By the modified design top layer input/output port FPGA pin assignment situation, updates and arrive the FPGA pin
In the file of graphics template database, to complete the design of FPGA pin assignment.
7. FPGA pin assignment according to claim 6 designs device, which is characterized in that
The file content of the design top layer input/output port message file, comprising: the name of port set, port set type,
Whether port set level, port set allow separation, any one or more in the name of port, port additional levels；
The file content of the device usable pins message file, comprising: pin type, pin in pin BANK number, BANK
Any one or more in description information, pin numbering.
8. FPGA pin assignment according to claim 6 designs device, which is characterized in that
The running unit generates script for running the FPGA pin figure template database write in advance, under executing
It states operation: the file content of the design top layer input/output port message file is retrieved, to be single with port set
Position establish level one data structure, secondary data structure is established as unit of port, wherein any level one data structure include to
A few secondary data structure, any level one data structure preserve the information of Single port group, and any secondary data structure is equal
Preserve the information of Single port；The file content of the device usable pins message file is retrieved, to be with BANK
Unit establishes level one data structure, and secondary data structure is established as unit of device usable pins, wherein any level one data knot
Structure includes at least one secondary data structure, and any level one data structure preserves the information of a BANK, any secondary number
The information of a device usable pins is preserved according to structure；By searching for established data structure, port set is ranked up；
According to port set ranking results, successively retrieval meets the pin of each port requirements, to each port in each port set
Pin predistribution is carried out, and the pin assignment situation of each port correspondence is stored in the secondary data structure of each port；
The call format of graphics template database is directed to according to the FPGA pin assignment software, by the data in obtained data structure
Printout, to generate the FPGA pin figure template database for graphic interface distribution FPGA pin.
9. FPGA pin assignment according to claim 8 designs device, which is characterized in that
The running unit carries out the file content of the device usable pins message file for using regular expression
Retrieval；
And/or
The running unit is used for according to preset port set ordering rule, by searching for established data structure, to port
Group is ranked up, so that priority of the priority for the preceding port set that sorts not less than the posterior port set that sorts；According to excellent
First grade is from high to low, BANK number from down to high sequence, and successively retrieval meets the pin of each port requirements；
And/or
The running unit exports the data-printing in obtained data structure for using printf function.
10. designing device according to the FPGA pin assignment any in claim 6 to 9, which is characterized in that
Further include: generation unit is generated for the file according to the FPGA pin figure template database for VIVADO's
This unbound document of XDC or for this unbound document of the UCF of ISE.
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| CN114970437A (en) * | 2022-07-28 | 2022-08-30 | 北京万龙精益科技有限公司 | Signal network adjusting method for rearrangement of device pins in PCB |
| WO2024060926A1 (en) * | 2022-09-21 | 2024-03-28 | 深圳市紫光同创电子有限公司 | Constraint file import method and apparatus, device, and storage medium |
| CN115374742A (en) * | 2022-10-25 | 2022-11-22 | 广州市保伦电子有限公司 | Method and device for pin package design of schematic diagram and storage medium |
| CN116128448A (en) * | 2023-01-09 | 2023-05-16 | 苏州异格技术有限公司 | Design data processing method and device for FPGA engineering project and electronic equipment |
| CN116128448B (en) * | 2023-01-09 | 2023-10-17 | 苏州异格技术有限公司 | Design data processing method and device for FPGA engineering project and electronic equipment |
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