CN110069238A - A kind of full adding method of superconduction, device and superconduction computing system - Google Patents
A kind of full adding method of superconduction, device and superconduction computing system Download PDFInfo
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- CN110069238A CN110069238A CN201910188473.1A CN201910188473A CN110069238A CN 110069238 A CN110069238 A CN 110069238A CN 201910188473 A CN201910188473 A CN 201910188473A CN 110069238 A CN110069238 A CN 110069238A
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- superconduction
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/50—Adding; Subtracting
- G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
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Abstract
The present invention proposes a kind of full adding method of superconduction, device and superconduction computing system, comprising: obtains two addend A to be added of one's own department or unit iiAnd BiAnd the carry C of previous position i-1i‑1, AiAnd BiBy the XOR gate of the first level production line and with door, respectively obtainAnd AiBi；Ci‑1WithIt is separately input to the XOR gate of the second level production line and participates in operation with door, obtainWithAnd it willWith AiBiIt is input in fusion buffering and obtains togetherOutputAs one's own department or unit and outputAs the carry to latter position i+1.Superconduction full adder disclosed by the invention can lay the foundation for the efficient high-performance computer of future source of energy, and the full adder structure is simple, with CB instead of or door, reduce a level production line, to reduce hardware resource consumption, reduce area overhead, while reducing circuit delay.
Description
Technical field
The present invention relates to field of computer, and the full adding method of in particular to a kind of superconduction, device and superconduction calculate system
System.
Background technique
The prior art is largely all based on CMOS (complementary metal oxide) semiconductor skill for the design of full adder
Art.As the Moore's Law of semiconductor integrated circuit becomes closer to physics limit, in order to meet future source of energy efficiently high property
The needs of energy computer system, it is necessary to find a kind of feasible substitute technology.
In cmos semiconductor technical aspect, existing semiconductor technology, which is faced with, reduces integrated circuit feature sizes and increase
Challenge of both the integrated level of unit area transistor.As integrated circuit feature sizes are close to atomic diameter, by 2021
Afterwards, if continuing to zoom out the feature sizes of semiconductor integrated circuit, economically for, it is no longer desirable.(superconduction is high by RSFQ
Fast list flux quantum) circuit because its characteristic with superelevation arithmetic speed and super low-power consumption be listed in it is most probable next-generation integrated
Circuit.
And full adder is as a kind of basic logical device, realize add, subtract, the core devices such as multiplication and division when, can all use
Full adder.This lays a good foundation for the RSFQ microprocessor of realization high energy efficiency later.And full adder is as a kind of basic logic
Device is widely used, and can be laid the foundation for realization RSFQ microprocessor in the future.
Summary of the invention
For the big problem of prior art power consumption, present invention employs RSFQ circuit engineerings to realize high-speed low-consumption.
Specifically, the invention discloses a kind of full adding method of superconduction, including:
Step 1, two addend A to be added for obtaining one's own department or unit iiAnd BiAnd the carry C of previous position i-1i-1, AiAnd BiPass through
The XOR gate of first level production line and with door, respectively obtainAnd AiBi；
Step 2, Ci-1WithIt is separately input to the XOR gate of the second level production line and participates in operation with door, obtainWithAnd it willWith AiBiIt is input in fusion buffering and obtains together
Step 3, outputAs one's own department or unit and outputAs to latter position
The carry of i+1.
The full adding method of the superconduction, wherein
The step 1 includes:
Step 11 is to guarantee timing synchronization, Ci-1The d type flip flop of the first level production line is latching to by input port；
The step 2 includes:
Step 21 is to guarantee timing synchronization, AiBiThe d type flip flop of the second level production line is latched by input port.
The invention also discloses a kind of full feeder apparatus of superconduction, including:
Device 1, two addend A to be added for obtaining one's own department or unit iiAnd BiAnd the carry C of previous position i-1i-1, AiAnd BiPass through
The XOR gate of first level production line and with door, respectively obtainAnd AiBi；
Device 2, Ci-1WithIt is separately input to the XOR gate of the second level production line and participates in operation with door, obtainWithAnd it willWith AiBiIt is input in fusion buffering and obtains together
Device 3, outputAs one's own department or unit and outputAs to latter position
The carry of i+1.
The full feeder apparatus of the superconduction, wherein
The device 1 includes:
Device 11 is to guarantee timing synchronization, Ci-1The d type flip flop of the first level production line is latching to by input port；
The device 2 includes:
Device 21 is to guarantee timing synchronization, AiBiThe d type flip flop of the second level production line is latched by input port.
The invention also discloses a kind of superconduction computing systems, including the full feeder apparatus of superconduction.
Superconduction full adder disclosed by the invention can lay the foundation for the efficient high-performance computer of future source of energy, and this adds entirely
Device structure is simple, with CB instead of or door, reduce a level production line, to reduce hardware resource consumption, reduce area
Expense, while reducing circuit delay.
Detailed description of the invention
Fig. 1 is superconduction full adder structure chart of the present invention.
Specific embodiment
Inventor has found that the huge power consumption of China's modern times supercomputer and data center makes its utilization when studying
Rate is extremely low, such as the power consumption of the light supercomputer in Chinese martial prowess Taihu Lake that TOP500 ranks the first is that 15.37MW (does not include
Refrigeration).For the power consumption of existing CMOS technology already close to its physics limit, the feature sizes of integrated circuit are straight already close to atom
Diameter.It therefore must development of new device high-performance low-power-consumption computer.And RSFQ because have ultraspeed and super low-power consumption at
For as most possible next generation's integrated circuit technology.
To allow features described above and effect of the invention that can illustrate more clearly understandable, special embodiment below, and cooperate
Bright book attached drawing is described in detail below.
Full adder is a kind of most basic computing unit, when carrying out add operation, not only to consider two addends, also to examine
Consider the carry of previous position (low level) Xiang Benwei.Two addends of full adder are all a bits, and a full adder can only
The add operation for carrying out one, can be expanded full adder the addition to realize more long number.
As a result, when designing full adder, it is necessary to consider three inputs, i.e. two addend AiAnd BiAnd previous position is to this
The carry C of positioni-1.The output of full adder is respectively one's own department or unit and SiAnd the carry C to a high positioni.The truth table of full adder such as 1 institute of table
Show.By truth table it can be seen that the relationship of input and output.
1 full adder truth table of table:
According to truth table, logical expression can be write out, and abbreviation is carried out to expression formula, detailed process is as follows:
Can be seen that formula (1) according to abbreviation result includes two xor operations, and formula (2) includes an xor operation, two
With operation and one or operation.According to the characteristic of RSFQ device traveling wave flowing water, since each RSFQ device includes one
Clock, and the D Flip-Flop (d type flip flop DFF) in RSFQ device has the function of latching, so realizing clock using DFF
It is synchronous.The logic chart of full adder is as shown in Figure 1, A in figurei、Bi、Ci-1For the input port of full adder, Si、CiFor the defeated of full adder
Exit port.CLKinIndicate clock input, CLKoutIndicate clock output.The full adder includes 2 level production lines altogether, totally two exclusive or
Door, two merge buffering (CB) with door, two DFF and one.Wherein, CB is used to implementation or operation, its advantage is not
It needs clock to drive, can reduce by a level production line in this way, improve working frequency.
Low-power consumption of the present invention is because it uses the single flux quantum RSFQ circuit engineering of superconduction high speed, RSFQ circuit itself
Just with the characteristic of high-speed low-consumption.
CB is the distinctive device of superconduction, and semiconductor full adder can not be optimized with CB.And as above-mentioned
The full adder being previously used for all is that the researcher in superconduction direction has used for reference the design of semiconductor full adder.And this time propose
Superconduction full adder, the personnel as computer field, it is contemplated that the optimization made for computer system (superconduction environment).With
CB instead of or door, reduce a level production line, to reduce hardware resource consumption, reduce area overhead, reduce simultaneously
Circuit delay.This is to realize that extensive superconducting integrated circuit lays the foundation later.
The full adder calculating process can be analyzed to following 3 step:
Step 1: AiAnd BiThe XOR gate and AND gate of the first level production line are separately input to by the input port of full adder
Operation is participated in, is obtainedAnd AiBi.To guarantee timing synchronization, while Ci-1First order flowing water is latched by input port
The DFF of line.
Step 2: Ci-1WithThe XOR gate and AND gate for being separately input to the second level production line participate in operation, obtainWithTo guarantee timing synchronization, while AiBiSecond level stream is latched by input port
The DFF of waterline.It is calculatedAfterwards, with AiBiIt is input in CB and obtains together
Step 3: exporting result respectivelyWith
The following are system embodiment corresponding with above method embodiment, present embodiment can be mutual with above embodiment
Cooperation is implemented.The relevant technical details mentioned in above embodiment are still effective in the present embodiment, in order to reduce repetition,
Which is not described herein again.Correspondingly, the relevant technical details mentioned in present embodiment are also applicable in above embodiment.
The invention also discloses a kind of full feeder apparatus of superconduction, including:
Device 1, two addend A to be added for obtaining one's own department or unit iiAnd BiAnd the carry C of previous position i-1i-1, AiAnd BiPass through
The XOR gate of first level production line and with door, respectively obtainAnd AiBi；
Device 2, Ci-1WithIt is separately input to the XOR gate of the second level production line and participates in operation with door, obtainWithAnd it willWith AiBiIt is input in fusion buffering and obtains together
Device 3, outputAs one's own department or unit and outputAs to latter position
The carry of i+1.
The full feeder apparatus of the superconduction, wherein
The device 1 includes:
Device 11 is to guarantee timing synchronization, Ci-1The d type flip flop of the first level production line is latching to by input port；
The device 2 includes:
Device 21 is to guarantee timing synchronization, AiBiThe d type flip flop of the second level production line is latched by input port.
The invention also discloses a kind of superconduction computing systems, including the full feeder apparatus of superconduction.
Claims (5)
1. a kind of full adding method of superconduction characterized by comprising
Step 1, two addend A to be added for obtaining one's own department or unit iiAnd BiAnd the carry C of previous position i-1i-1, AiAnd BiPass through first
The XOR gate of level production line and with door, respectively obtainAnd AiBi；
Step 2, Ci-1WithIt is separately input to the XOR gate of the second level production line and participates in operation with door, obtainWithAnd it willWith AiBiIt is input in fusion buffering and obtains together
Step 3, outputAs one's own department or unit and outputAs to latter position i+1
Carry.
2. the full adding method of superconduction as described in claim 1, which is characterized in that
The step 1 includes:
Step 11 is to guarantee timing synchronization, Ci-1The d type flip flop of the first level production line is latching to by input port；
The step 2 includes:
Step 21 is to guarantee timing synchronization, AiBiThe d type flip flop of the second level production line is latched by input port.
3. a kind of full feeder apparatus of superconduction characterized by comprising
Device 1, two addend A to be added for obtaining one's own department or unit iiAnd BiAnd the carry C of previous position i-1i-1, AiAnd BiPass through first
The XOR gate of level production line and with door, respectively obtainAnd AiBi；
Device 2, Ci-1WithIt is separately input to the XOR gate of the second level production line and participates in operation with door, obtainWithAnd it willWith AiBiIt is input in fusion buffering and obtains together
Device 3, outputAs one's own department or unit and outputAs to latter position i+1
Carry.
4. the full feeder apparatus of superconduction as claimed in claim 3, which is characterized in that
The device 1 includes:
Device 11 is to guarantee timing synchronization, Ci-1The d type flip flop of the first level production line is latching to by input port；
The device 2 includes:
Device 21 is to guarantee timing synchronization, AiBiThe d type flip flop of the second level production line is latched by input port.
5. a kind of superconduction computing system, including the full feeder apparatus of superconduction described in claim 3 or 4.
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| CN111049503A (en) * | 2019-12-19 | 2020-04-21 | 中国科学院计算技术研究所 | Superconducting trigger and operation method thereof |
| CN111427810A (en) * | 2020-03-17 | 2020-07-17 | 中国科学院计算技术研究所 | Asynchronous acquisition device of superconducting interface |
| EP4109757A1 (en) * | 2021-06-22 | 2022-12-28 | Northrop Grumman Systems Corporation | Superconducting exclusive-or (xor) gate system |
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| CN111427810A (en) * | 2020-03-17 | 2020-07-17 | 中国科学院计算技术研究所 | Asynchronous acquisition device of superconducting interface |
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Application publication date: 20190730 |