CN110061728B - Power-on reset device and electronic equipment - Google Patents
Power-on reset device and electronic equipment Download PDFInfo
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- CN110061728B CN110061728B CN201910446476.0A CN201910446476A CN110061728B CN 110061728 B CN110061728 B CN 110061728B CN 201910446476 A CN201910446476 A CN 201910446476A CN 110061728 B CN110061728 B CN 110061728B
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- 239000003990 capacitor Substances 0.000 claims description 25
- 238000005070 sampling Methods 0.000 claims description 13
- 238000001914 filtration Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 230000005669 field effect Effects 0.000 claims description 3
- 229910044991 metal oxide Inorganic materials 0.000 claims description 3
- 150000004706 metal oxides Chemical class 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 10
- 230000003111 delayed effect Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 230000006399 behavior Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
- H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
Abstract
The present disclosure relates to a power-on reset device and an electronic apparatus, the device comprising: the first module is electrically connected with the power supply voltage, is used for following the change of the power supply voltage and outputs a following voltage signal; the second module is electrically connected with the first module and is used for reducing the following voltage signal output by the first module to a threshold voltage under the condition of receiving a control signal; the third module is electrically connected with the second module and the power supply voltage and is used for outputting the control signal for a preset time period under the condition that the power supply voltage is reduced to be equal to or smaller than a preset voltage value; and the fourth module is electrically connected with the first module and is used for carrying out delay processing on the following voltage signal and outputting a power-on reset signal. The power-on reset device disclosed by the disclosure can output stable and reliable power-on reset signals under the condition that a power supply is powered down and powered up rapidly.
Description
Technical Field
The disclosure relates to the field of integrated circuit design, and in particular relates to a power-on reset device and electronic equipment.
Background
In the field of integrated circuit design, various integrated circuits may include a Power On Reset (POR) circuit that functions to ensure that analog and digital modules initialize to a known state after Power is applied. The basic POR function generates an internal reset pulse or level to avoid "contention" and to keep the device static until the supply voltage stabilizes.
However, the POR circuit in the related art has a disadvantage of instability, and cannot generate a stable and reliable power-on reset signal.
Disclosure of Invention
In view of this, the present disclosure provides a power-on reset device and an electronic device to generate a stable and reliable power-on reset signal.
According to one aspect of the present disclosure, a power-on reset device is presented, the device comprising:
the first module is electrically connected with the power supply voltage, is used for following the change of the power supply voltage and outputs a following voltage signal;
the second module is electrically connected with the first module and is used for reducing the following voltage signal output by the first module to a threshold voltage under the condition of receiving a control signal;
the third module is electrically connected with the second module and the power supply voltage and is used for outputting the control signal for a preset time period under the condition that the power supply voltage is reduced to be equal to or smaller than a preset voltage value;
and the fourth module is electrically connected with the first module and is used for carrying out delay processing on the following voltage signal and outputting a power-on reset signal.
In one possible implementation manner, the first module includes a first resistor and a capacitor, wherein a first end of the first resistor is electrically connected to the power supply voltage, a second end of the first resistor is electrically connected to a first end of the capacitor, a second end of the capacitor is grounded, and the first end of the capacitor is used for outputting the following voltage signal.
In one possible implementation manner, the second module includes a metal oxide semiconductor field effect transistor, a first end of the transistor is electrically connected to the first module, a second end of the transistor is grounded, and a third end of the transistor is used for receiving the control signal and controlling a conduction state of the transistor according to the control signal.
In one possible embodiment, the third module includes:
the first sub-module is used for sampling the power supply voltage to obtain a sampling voltage;
the second sub-module is electrically connected with the first sub-module and is used for comparing the sampling voltage with a preset voltage value and outputting a comparison signal under the condition that the sampling voltage is equal to or smaller than the preset voltage value;
and the third sub-module is electrically connected with the second sub-module and is used for filtering the comparison signal and outputting the control signal.
In one possible implementation, the first submodule includes a second resistor and a digital-to-analog converter, where,
one end of the second resistor is electrically connected to the power supply voltage, and the other end of the second resistor is electrically connected to the ground;
the digital-to-analog converter is electrically connected to the second resistor and is used for performing analog-to-digital conversion on the voltage on the second resistor and outputting the sampling voltage.
In one possible implementation, the fourth module includes N inverters, where N is an even number.
In one possible embodiment, the preset time period is greater than or equal to 1ns.
In one possible embodiment, the threshold voltage is a voltage value between 0V and VPP/2, where VPP represents the supply voltage.
According to another aspect of the present disclosure, an electronic device is provided, which includes the power-on reset device.
Through the device, under the condition that the power supply voltage is reduced to be equal to or smaller than the preset voltage value, the third module outputs the control signal with the preset duration to control the second module to reduce the following voltage signal output by the first module to the threshold voltage, so that the following voltage signal can rise from the threshold voltage after the power supply voltage rises, and the power-on reset signal is output after delay processing by the fourth module. The power-on reset device disclosed by the disclosure can output stable and reliable power-on reset signals under the condition that a power supply is powered down and powered up rapidly.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.
Fig. 1 shows a block diagram of a power-on reset device according to an embodiment of the present disclosure.
Fig. 2 shows a schematic diagram of a power-on reset device according to an embodiment of the present disclosure.
Fig. 3 illustrates an operational waveform diagram of a power-on reset device according to an embodiment of the present disclosure.
Fig. 4a shows a schematic diagram of generating and outputting a power-on reset signal using the related art, and fig. 4b shows a schematic diagram of generating and outputting a power-on reset signal using the technical scheme of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
Referring to fig. 1, fig. 1 shows a block diagram of a power-on reset device according to an embodiment of the present disclosure.
As shown in fig. 1, the apparatus includes:
a first module 10 electrically connected to a power supply voltage, for following a change in the power supply voltage, and outputting a following voltage signal;
a second module 20, electrically connected to the first module 10, for reducing the following voltage signal output by the first module 10 to a threshold voltage when receiving a control signal;
a third module 40, electrically connected to the second module 20 and the power supply voltage, for outputting the control signal for a preset duration when the power supply voltage is reduced to be equal to or less than a preset voltage value;
the fourth module 30 is electrically connected to the first module 10, and is configured to delay the following voltage signal and output a power-on reset signal.
Through the device, under the condition that the power supply voltage is reduced to be equal to or smaller than the preset voltage value, the third module outputs the control signal with the preset duration to control the second module to reduce the following voltage signal output by the first module to the threshold voltage, so that the following voltage signal can rise from the threshold voltage after the power supply voltage rises, and the power-on reset signal is output after delay processing by the fourth module. The power-on reset device disclosed by the disclosure can output stable and reliable power-on reset signals under the condition that a power supply is powered down and powered up rapidly.
Various modules of the power-on reset device of the present disclosure may have a variety of different implementations, and a possible implementation of each module will be described below with reference to specific examples.
Referring to fig. 2, fig. 2 is a schematic diagram of a power-on reset device according to an embodiment of the disclosure.
In one possible implementation, as shown in fig. 2, the first module 10 may include a first resistor R1 and a capacitor C, where a first end of the first resistor R1 is electrically connected to the power supply voltage VPP, a second end of the first resistor R1 is electrically connected to a first end of the capacitor C, a second end of the capacitor C is grounded, and the first end of the capacitor C is used for outputting the following voltage signal VA.
Of course, the first module 10 may also comprise other elements, for example, a plurality of resistors, constituting a resistor network to replace said first resistor R1. A capacitor network may be formed by a plurality of capacitors in series or parallel to replace the capacitor C. The present disclosure is not limited in this regard.
In the first module 10 of the present disclosure, when the power supply voltage VPP starts to rise from 0V, the power supply voltage VPP can charge the capacitor C through the first resistor R1, the following voltage signal VA between the capacitor C and the first resistor R1 gradually rises, and finally the following voltage signal VA is close to or equal to the power supply voltage VPP.
In one possible implementation, the second module 20 may include a metal oxide semiconductor field effect transistor Q1, a first terminal of the transistor Q1 is electrically connected to the first module 10, a second terminal of the transistor Q1 is grounded, and a third terminal of the transistor Q1 is configured to receive the control signal and control a conductive state of the transistor according to the control signal.
In one possible implementation, the threshold voltage may be a low voltage, such as a voltage value between 0V and VPP/2, where VPP represents the supply voltage.
In one example, the threshold voltage may be 0V.
In one possible implementation, the first terminal of the transistor Q1 is electrically connected between the first resistor R1 and the capacitor C.
In one possible implementation, the first terminal of the transistor Q1 may be a drain, the second terminal of the transistor Q1 may be a source, and the third terminal of the transistor Q1 may be a gate.
Of course, the second module 20 may also comprise other elements, as long as the following voltage signal can be grounded under the control of the control signal.
The second module 20 of the present disclosure may ground the capacitor C after receiving the control signal, thereby pulling the following voltage signal down to the threshold voltage.
In one possible embodiment, the third module includes:
a first sub-module 401, configured to sample the power supply voltage to obtain a sampled voltage;
a second sub-module 402, electrically connected to the first sub-module 401, for comparing the sampled voltage with a preset voltage value VREF, and outputting a comparison signal when the sampled voltage is equal to or less than the preset voltage value;
and a third sub-module 403, electrically connected to the second sub-module 402, for filtering the comparison signal and outputting the control signal.
In one possible implementation, the first sub-module 401 includes a second resistor R2 and a digital-to-analog converter DAC, where,
one end of the second resistor R2 is electrically connected to the power supply voltage VPP, and the other end of the second resistor R2 is electrically connected to the ground;
the digital-to-analog converter DAC is electrically connected to the second resistor R2, and is configured to perform analog-to-digital conversion on the voltage on the second resistor R2 and output the sampling voltage.
In one possible implementation, the second sub-module 402 may include a comparator CMP.
In one possible implementation, the sampling voltage may be input to a positive input of the comparator CMP, and the preset voltage value VREF may be input to a negative input of the comparator CMP. Of course, other connection methods are also possible.
In case the second sub-module 402 detects that the sampling voltage is equal to or less than the preset voltage value VREF, a comparison signal is output.
In one possible implementation, the comparison signal may be set according to the on condition of the transistor Q1 (e.g., may be a high level signal).
In one possible embodiment, the magnitude of the preset voltage value VREF may be set as needed, which is not limited in this disclosure.
In one possible implementation, the third sub-module 403 may perform filtering processing on the comparison signal, so as to eliminate jitter of the comparison signal, and output the control signal, so that the control signal is more stable.
In one possible implementation, a person skilled in the art may design the third sub-module 403 according to need, and the disclosure is not limited to the specific circuit structure of the third sub-module 403.
Through the cooperation of each sub-module of the third module, the third module can output a control signal to control the operation of the second module under the condition that the power supply voltage is rapidly reduced, so that the capacitor C is connected to the ground under the condition that the second module 20 receives the control signal, and the following voltage signal is rapidly reduced to the threshold voltage.
In one possible implementation, the fourth module 30 includes N inverters, where N is an even number. In one example, as shown in fig. 2, the number of inverters of the fourth module 30 may be 2.
Through the fourth module 30, the present disclosure may enable the following voltage signal VA to be output after being delayed for a preset time, so that the following voltage signal VA is used as a stable power-on reset signal after being delayed to perform power-on reset on the electronic device.
In a possible embodiment, the preset duration of the control signal may be set as required, for example, the preset duration may be set to be greater than or equal to 1ns.
In one example, the preset duration may be 10ns,100ns, etc.
The second module grounds the capacitor C for a preset period of time to pull the following voltage signal VA down to the threshold voltage, and disconnects the connection between the first terminal of the capacitor C and ground after the preset period of time, so that the capacitor C is gradually charged up in the case that the power supply voltage VPP starts to rise (power up), and the following voltage signal VA gradually rises until it is stabilized at a voltage value close to or equal to the power supply voltage VPP, thereby outputting a stable and reliable power-on reset signal.
Referring to fig. 3, fig. 3 is a schematic diagram illustrating an operation waveform of a power-on reset device according to an embodiment of the disclosure.
As shown in fig. 3, when the power supply voltage VPP gradually increases to a stable value (e.g., 3.3v,5v, etc.), the first module follows the voltage variation of the power supply voltage VPP, outputs the following voltage signal VA, and outputs the power-on reset signal POR after being delayed by the fourth module.
When the power supply voltage VPP drops rapidly after being stabilized, the third module detects the voltage change of the power supply voltage VPP, and when the power supply voltage VPP drops to a preset voltage value, the second module is controlled by the output control signal for a preset duration to drop the following voltage signal VA to a threshold voltage (low level signal) rapidly, and in this case, the following voltage signal is delayed by the fourth module and then outputs a low-level power-on reset signal to reset the electronic device.
After a preset period of time, the second module disconnects the connection between the first end of the capacitor C and the ground, the power supply voltage is gradually increased (electrified), the capacitor C starts to charge, the voltage signal VA is gradually increased, and after the power supply voltage VPP reaches a stable value, the fourth module outputs a stable power-on reset signal to reset the electronic equipment.
Referring to fig. 4 a-4 b, fig. 4a shows a schematic diagram of generating and outputting a power-on reset signal by using a related art, and fig. b shows a schematic diagram of generating and outputting a power-on reset signal by using the technical scheme of the present disclosure.
As shown in fig. 4a, when the power supply voltage is rapidly powered down and powered up from a stable value, the related art has a failure condition, and cannot output a stable power-on reset signal (no change occurs in the signal at the block in the POR signal). Moreover, under the condition of repeated rapid power-down and power-up, the related technology cannot output a stable power-up reset signal, and has failure condition.
As shown in fig. 4b, the present disclosure may output a stable and reliable power-on reset signal when the power supply voltage is rapidly powered down and powered up from a stable value. And the power-on reset signal is output stably and reliably under the condition of quick power-off and power-on for many times, so that the power-on reset of the electronic equipment is carried out.
Moreover, the power-on reset signal can start to act from a fixed initial value (threshold voltage) under the condition of quick power-down and power-up, so that consistency of POR behaviors of power-on reset every time is ensured.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the improvement of technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (9)
1. A power-on reset device, the device comprising:
the first module is electrically connected with the power supply voltage, is used for following the change of the power supply voltage and outputs a following voltage signal;
the second module is electrically connected with the first module and is used for reducing the following voltage signal output by the first module to a threshold voltage under the condition of receiving a control signal;
the third module is electrically connected with the second module and the power supply voltage and is used for outputting the control signal for a preset time period under the condition that the power supply voltage is reduced to be equal to or smaller than a preset voltage value;
and the fourth module is electrically connected with the first module and is used for carrying out delay processing on the following voltage signal and outputting a power-on reset signal, wherein after the power supply voltage rises, the following voltage signal rises from the threshold voltage, and after the delay processing of the fourth module, the power-on reset signal is output.
2. The apparatus of claim 1, wherein the first module comprises a first resistor, a capacitor, wherein a first end of the first resistor is electrically connected to the supply voltage, a second end of the first resistor is electrically connected to a first end of the capacitor, a second end of the capacitor is grounded, and the first end of the capacitor is configured to output the follow-up voltage signal.
3. The apparatus of claim 1, wherein the second module comprises a metal oxide semiconductor field effect transistor, a first terminal of the transistor is electrically connected to the first module, a second terminal of the transistor is grounded, and a third terminal of the transistor is configured to receive the control signal and control a conductive state of the transistor according to the control signal.
4. The apparatus of claim 1, wherein the third module comprises:
the first sub-module is used for sampling the power supply voltage to obtain a sampling voltage;
the second sub-module is electrically connected with the first sub-module and is used for comparing the sampling voltage with a preset voltage value and outputting a comparison signal under the condition that the sampling voltage is equal to or smaller than the preset voltage value;
and the third sub-module is electrically connected with the second sub-module and is used for filtering the comparison signal and outputting the control signal.
5. The apparatus of claim 4, wherein the first submodule includes a second resistor and a digital-to-analog converter, wherein,
one end of the second resistor is electrically connected to the power supply voltage, and the other end of the second resistor is electrically connected to the ground;
the digital-to-analog converter is electrically connected to the second resistor and is used for performing analog-to-digital conversion on the voltage on the second resistor and outputting the sampling voltage.
6. The apparatus of claim 1, wherein the fourth module comprises N inverters, wherein N is an even number.
7. The apparatus of claim 1, wherein the predetermined time period is greater than or equal to 1ns.
8. The apparatus of claim 1, wherein the threshold voltage is a voltage value between 0V and VPP/2, where VPP represents the supply voltage.
9. An electronic device, characterized in that it comprises a power-on reset device according to any of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910446476.0A CN110061728B (en) | 2019-05-27 | 2019-05-27 | Power-on reset device and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910446476.0A CN110061728B (en) | 2019-05-27 | 2019-05-27 | Power-on reset device and electronic equipment |
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| CN110061728A CN110061728A (en) | 2019-07-26 |
| CN110061728B true CN110061728B (en) | 2024-02-27 |
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