CN110061005B

CN110061005B - Flash memory and manufacturing method thereof

Info

Publication number: CN110061005B
Application number: CN201810047653.3A
Authority: CN
Inventors: 恩凯特·库马; 马洛宜·库马; 李家豪
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2018-01-18
Filing date: 2018-01-18
Publication date: 2021-09-17
Anticipated expiration: 2038-01-18
Also published as: CN110061005A

Abstract

The invention provides a flash memory and a manufacturing method thereof, wherein the manufacturing method of the flash memory comprises the steps of forming a first conducting layer on a semiconductor substrate, forming a patterned mask layer on the first conducting layer, wherein an opening of the patterned mask layer exposes the first conducting layer, forming a second conducting layer on the patterned mask layer, wherein the second conducting layer extends into the opening, carrying out a first etching process on the second conducting layer to form a gap on the side wall of the opening, carrying out an oxidation process to form an oxide structure in the opening, using the oxide structure as a mask, carrying out a second etching process to form a floating gate, and forming a source region and a drain region in the semiconductor substrate.

Description

Flash memory and manufacturing method thereof

Technical Field

The present invention relates to flash memories, and more particularly, to an embedded flash memory having a floating gate with a sharp tip and a method of manufacturing the same.

Background

Flash memory is a type of non-volatile memory. In general, a flash memory includes two gates, a first gate is a floating gate (floating gate) for storing data, and a second gate is a control gate (control gate) for inputting and outputting data. The floating gate is located under the control gate and is in a "floating" state. By floating is meant surrounding and isolating the floating gate with an insulating material to prevent charge loss. The control gate is connected to a Word Line (WL) to control the device. One of the advantages of flash memory is that block-by-block erase (blb) data is possible. Flash memory is widely used in enterprise servers, storage and network technologies, and in a wide range of consumer electronics products, such as flash drives for personal disks (USB), mobile phones, digital cameras, tablet computers, personal computer cards (PC cards) for notebook computers, embedded controllers, and so on.

Many different types of non-volatile memories are commercially available, such as flash memories, electrically erasable programmable read-only memories (EEPROMs), and multi-time programmable (MTP) non-volatile memories. However, embedded flash memory, particularly embedded split-gate flash memory, has significant advantages over other non-volatile memory technologies.

Although existing flash memories and methods of manufacturing the same are adequate for their intended purposes, they have not yet fully met the requirements in every aspect, and thus flash memory technology still remains a problem to overcome.

Disclosure of Invention

Embodiments of flash memories and methods of manufacturing the same, particularly embedded split gate flash memories, are provided. In some embodiments of the invention, spacers are formed on the sidewalls of the openings. Then, during the oxidation process, a portion of the spacers are oxidized to form an oxide structure within the opening. After the oxidation process is performed, the remaining portion of the spacer has a concave surface facing the oxide structure above it, and after a subsequent etching process, a complete floating gate having a vertical tip is formed.

In the foregoing method, spacers are used to form the tips of the floating gates, and the erase (erase) efficiency of the device depends on the sharpness of the tips. Therefore, the presence of the spacers can shorten the duration of the oxidation process, while ensuring that the tips have a sufficient sharpness, so that the thickness of the floating gate underlying the oxide structure is not too thin. As a result, the flash memory having the floating gate with the pointed end formed by the foregoing method may yield advantages such as improving the erase efficiency of the device, increasing the overall performance of the device, and facilitating the fabrication in any flash memory process.

In addition, in some embodiments of the present invention, the oxide structure is formed before the complete floating gate is formed, so the oxide structure can be used as a mask during the etching process for forming the floating gate, thereby eliminating the need to use an additional mask to generate the tip, and reducing the process cost.

According to some embodiments, a method of manufacturing a flash memory is provided. The method includes forming a first conductive layer on a semiconductor substrate, and forming a patterned mask layer on the first conductive layer, wherein an opening of the patterned mask layer exposes the first conductive layer. The method also includes forming a second conductive layer over the patterned masking layer, wherein the second conductive layer extends into the opening. The method further includes performing a first etch process on the second conductive layer to form spacers on sidewalls of the opening, and performing an oxidation process to form an oxide structure within the opening. In addition, the method includes performing a second etching process to form the floating gate with the oxide structure as a mask, and forming a source region and a drain region in the semiconductor substrate.

According to some embodiments, a flash memory is provided. The flash memory comprises a floating gate arranged on a semiconductor substrate, wherein a first edge of the floating gate is a first tip end, and a second edge of the floating gate is a second tip end. The flash memory also includes an oxide structure disposed on the floating gate, wherein a first protruding portion of the oxide structure is directly over the first tip and a second protruding portion of the oxide structure is directly over the second tip. The flash memory further comprises a source region and a drain region arranged in the semiconductor substrate, and the floating gate is positioned between the source region and the drain region.

The following embodiments and the accompanying reference drawings will provide detailed descriptions.

Drawings

The aspects of the embodiments of the present invention will be better understood from the following detailed description taken in conjunction with the accompanying drawings. It is noted that some components (features) may not be drawn to scale according to industry standard practice. In fact, the dimensions of the various elements may be increased or decreased for clarity of discussion.

Fig. 1-8 are cross-sectional schematic diagrams illustrating intermediate stages in forming the flash memory of fig. 8, according to some embodiments of the present invention.

Reference numerals:

100-flash memory;

101-a semiconductor substrate;

103 dielectric layer;

103' dielectric structure;

105 to a first conductive layer;

105' to the remaining portion of the first conductive layer;

107-patterning a mask layer;

108-opening;

109 to a second conductive layer;

109 a-a first spacer;

109 b-a second spacer;

109 a' to the remainder of the first spacer;

109 b' to the remainder of the second spacer;

110-depression;

111-oxide structure;

111a to a first projection;

111b to a second projection;

113 floating gate;

115-control grid;

117-source region;

119 to the drain region.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different components of the provided semiconductor devices. Specific examples of components and arrangements thereof are described below to simplify the present embodiments. These are, of course, merely examples and are not intended to be limiting. For example, references in the description to a first element being formed on a second element may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements are formed between the first and second elements such that they are not in direct contact. In addition, embodiments of the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described below. Like reference numerals are used to designate like elements in the various figures and described embodiments. It will be understood that additional operations may be provided before, during, or after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

Fig. 1-8 are cross-sectional schematic diagrams illustrating intermediate stages in forming the flash memory 100 of fig. 8, according to some embodiments of the present invention.

According to some embodiments, as shown in fig. 1, a semiconductor substrate 101 is provided. In some embodiments, the semiconductor substrate 101 may be made of silicon or other semiconductor materials, or the semiconductor substrate 101 may comprise other elemental semiconductor materials, such as germanium (Ge). In some embodiments, the semiconductor substrate 101 is made of a compound semiconductor such as silicon carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the semiconductor substrate 101 is made of an alloy semiconductor, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or indium gallium phosphide. In some embodiments, the semiconductor substrate 101 includes a silicon-on-insulator (SOI) substrate.

In some embodiments, the semiconductor substrate 101 has the first conductivity type, for example, the semiconductor substrate 101 of the present embodiment is a lightly doped P-type substrate, while in other embodiments, the semiconductor substrate 101 may be a lightly doped N-type substrate.

Continuing with the foregoing, according to some embodiments, as shown in fig. 2, a dielectric layer 103 is formed on a semiconductor substrate 101. In some embodiments, the dielectric layer 103 may be made of silicon oxide, silicon nitride, silicon oxynitride, or other suitable dielectric material. Furthermore, the dielectric layer 103 may be formed by a thermal oxidation process, a Chemical Vapor Deposition (CVD) process, or a combination thereof.

Then, a first conductive layer 105 is formed on the dielectric layer 103. In some embodiments, the first conductive layer 105 may be made of polysilicon. However, in other embodiments, first conductive layer 105 may be made of other suitable conductive materials, such as a metallic material. The first conductive layer 105 may be formed by a deposition process, such as a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, a Low Pressure CVD (LPCVD) process, a High Density Plasma CVD (HDPCVD) process, a Metal Organic Chemical Vapor Deposition (MOCVD) process, a plasma-enhanced CVD (PECVD) process, or a combination thereof.

Referring to fig. 2, after the first conductive layer 105 is formed, a mask layer (not shown) is formed on the first conductive layer 105. Subsequently, the mask layer is patterned by performing a patterning process to form a patterned mask layer 107 having an opening 108 therein. The patterning process includes a photolithography process and an etching process. The photolithography process includes photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, washing, and baking (e.g., hard baking). The etching process includes dry etching or wet etching.

In some embodiments, the patterned masking layer 107 may be made of a nitride, such as silicon nitride, or other suitable materials. It is noted that the opening 108 of the patterned mask layer 107 exposes a portion of the first conductive layer 105, and the opening 108 is formed to define the location of a floating gate to be subsequently formed.

Next, according to some embodiments, as shown in FIG. 3, a second conductive layer 109 is formed over the patterned masking layer 107. In addition, the second conductive layer 109 extends into the opening 108 of the patterned mask layer 107. In other words, the second conductive layer 109 is formed to cover the patterned mask layer 107 and the portion of the first conductive layer 105 exposed by the opening 108.

In some embodiments, the portion of the first conductive layer 105 exposed by the opening 108 is completely covered by the second conductive layer 109, and the second conductive layer 109 has a recess 110 directly above the location of the opening 108. More specifically, the recess 110 is located within the opening 108.

Some processes and materials for forming the second conductive layer 109 are similar or identical to those for forming the first conductive layer 105, and thus, a description thereof will not be repeated. In some embodiments, first conductive layer 105 and second conductive layer 109 are made of the same material, such as polysilicon.

As shown in fig. 4, a first etching process is performed on the second conductive layer 109 to remove the second conductive layer 109 covering the patterned mask layer 107. In addition, a portion of the second conductive layer 109 filling the opening 108 is also removed by the first etching process, leaving the first and

second spacers

109a and 109b on opposite sidewalls of the opening 108. In other words, the first spacers 109a and the second spacers 109b are formed of the second conductive layer 109.

In some embodiments, the first and

second spacers

109a and 109b may have the same height as the patterned mask layer 107. In other embodiments, the height of the first and

second spacers

109a and 109b may be less than the height of the patterned mask layer 107.

In some embodiments, the first etching process comprises a dry etching process or a wet etching process. As a result, after the first etching process is performed, a portion of the top surface of the first conductive layer 105 is exposed again by the opening 108. Further, as shown in fig. 4, the first and

second spacers

109a and 109b have convex surfaces facing the center of the opening 108.

According to some embodiments, an oxidation process is performed to form an oxide structure 111 within the opening 108, as shown in fig. 5. During the oxidation process, a portion of the first spacers 109a, a portion of the second spacers 109b, and a portion of the first conductive layer 105 under the opening 108 are oxidized and converted to form an oxide structure 111. As a result, the bottom surface of the oxide structure 111 is lower than the bottom surface of the patterned mask layer 107, and the remaining portion 109a '(also referred to as a first tip) of the first spacer and the remaining portion 109 b' (also referred to as a second tip) of the second spacer have a concave surface facing the oxide structure 111.

The remaining portion 109a 'of the first spacer and the remaining portion 109 b' of the second spacer are tips of the floating gates 113 (shown in fig. 6). It is noted that in the stage shown in fig. 5, the floating gate 113 is not yet fully formed. Since the first and

second spacers

109a and 109b can provide the heights of the first and second tips 109a 'and 109 b', the duration of the oxidation process can be shortened such that the thickness of the first conductive layer 105 under the oxide structure 111 is not too thin.

In other words, a sufficient minimum distance D may be maintained between the oxide structure 111 and the dielectric layer 103, and the first tip 109a 'and the second tip 109 b' may have a sufficient sharpness degree. As a result, the erase efficiency of the device may be improved.

Furthermore, referring to fig. 5, the oxide structure 111 includes a first protrusion portion 111a and a second protrusion portion 111b protruding from the top surface of the patterned mask layer 107. It is noted that the first protruding portion 111a is located directly above the first tip 109a ', and the second protruding portion 111b is located directly above the second tip 109 b'. The first protruding portion 111a and the second protruding portion 111b are located at opposite side edges of the oxide structure 111.

Specifically, the first protruding portion 111a and the second protruding portion 111b have circular arc top surfaces. In some embodiments, the top surfaces of the first and second protruding

portions

111a and 111b may be semicircular or semi-elliptical.

In addition, in the present embodiment, the oxide structure 111 may also include a flat top surface between the first protruding portion 111a and the second protruding portion 111b, and the flat top surface is lower than the top surfaces of the first protruding portion 111a and the second protruding portion 111 b.

Next, as shown in fig. 6, a second etching process is performed using the oxide structure 111 as a mask to form a complete floating gate 113. In some embodiments, the second etch process may comprise a dry etch process or a wet etch process. After the second etching process, the patterned mask layer 107 and a portion of the first conductive layer 105 under the patterned mask layer 107 are removed.

More specifically, the patterned mask layer 107 and the portion of the first conductive layer 105 not covered by the oxide structure 111 are etched away, and the remaining portion 105 ', the first tip 109a ' and the second tip 109b ' of the first conductive layer constitute the floating gate 113. Once the second etching process is finished, the floating gate 113 is completed, and the first tip 109a 'and the second tip 109 b' are located at opposite side edges of the floating gate 113.

Referring again to fig. 6, after the second etching process, another dielectric layer is formed to cover the sidewalls of the floating gates 113. The dielectric layer on the sidewalls of the floating gate 113 and the previously formed dielectric layer 103 may combine to form a dielectric structure 103'. In this embodiment, the floating gate 113 is completely surrounded by the dielectric structure 103' and the oxide structure 111.

According to some embodiments, a control gate 115 is formed on dielectric structure 103', as shown in fig. 7. In some embodiments, control gate 115 extends over oxide structure 111. More specifically, the control gate 115 covers the first protruding portion 111a of the oxide structure 111, and the control gate 115 does not cover the second protruding portion 111b of the oxide structure 111. Notably, the control gate 115 is separated from the floating gate 113 by the dielectric structure 103' and the oxide structure 111.

In some embodiments, a third conductive layer (not shown) is formed overlying the dielectric structure 103' and the oxide structure 111. Then, the third conductive layer is patterned to form the control gate 115. The patterning process of the third conductive layer may be similar or identical to the process used to form the patterned mask layer 107, and thus, a description thereof will not be repeated. In the present embodiment, the thickness of the control gate 115 is greater than that of the floating gate 113, and the length of the control gate 115 is greater than that of the floating gate 113.

Some materials and processes for forming the third conductive layer may be similar or identical to those for forming the first conductive layer 105 and the second conductive layer 109, and thus, a description thereof will not be repeated. In some embodiments, the first conductive layer 105, the second conductive layer 109, and the third conductive layer are made of the same material, such as polysilicon.

Next, according to some embodiments, as shown in FIG. 8, a source region 117 and a drain region 119 are formed by implanting ions into the semiconductor substrate 101. Floating gate 113 and control gate 115 are located between source region 117 and drain region 119.

In the present embodiment, the semiconductor substrate 101 is a P-type substrate, and the source region 117 and the drain region 119 are formed by implanting N-type dopants, such As phosphorus (P) or arsenic (As), into the semiconductor substrate 101. In other embodiments, the semiconductor substrate 101 is an N-type substrate, and the source region 117 and the drain region 119 are formed by implanting P-type dopants, such as boron (B), into the semiconductor substrate 101. The conductivity type of the semiconductor substrate 101 is opposite to the conductivity type of the source region 117 and the drain region 119. Once the source region 117 and the drain region 119 are formed, the flash memory 100 is completed.

In some embodiments of the invention, spacers are formed on the sidewalls of the openings. Then, during the oxidation process, a portion of the spacers are oxidized to form an oxide structure within the opening. After the oxidation process is performed, the remaining portion of the spacer has a concave surface facing the oxide structure above it, and after a subsequent etching process, a complete floating gate having a vertical tip is formed.

In the foregoing method, the spacers are used to form the tips of the floating gates, and the erase efficiency of the device depends on the sharpness of the tips. Therefore, the presence of the spacers can shorten the duration of the oxidation process, while ensuring that the tips have a sufficient sharpness, so that the thickness of the floating gate underlying the oxide structure is not too thin. As a result, the flash memory having the floating gate with the pointed end formed by the foregoing method may yield advantages such as improving the erase efficiency of the device, increasing the overall performance of the device, and facilitating the fabrication in any flash memory process.

In addition, in some embodiments of the present invention, the oxide structure is formed before the complete floating gate is formed, so the oxide structure can be used as a mask during the etching process for forming the floating gate, thereby eliminating the need to use an additional mask to generate the tip and reducing the process cost.

The foregoing outlines several embodiments so that those skilled in the art may better understand the aspects of the present embodiments. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention.

Claims

1. A method of manufacturing a flash memory, comprising:

forming a first conductive layer on a semiconductor substrate;

forming a patterned mask layer on the first conductive layer, wherein an opening of the patterned mask layer exposes the first conductive layer;

forming a second conductive layer over the patterned masking layer, wherein the second conductive layer extends into the opening;

performing a first etching process on the second conductive layer to form a spacer on a sidewall of the opening;

performing an oxidation process to form an oxide structure within the opening, wherein a portion of the spacer and a portion of the first conductive layer are converted to the oxide structure during the oxidation process;

using the oxide structure as a mask, and performing a second etching process to form a floating gate; and

a source region and a drain region are formed in the semiconductor substrate.

2. The method of claim 1, wherein the second conductive layer has a recess directly above the opening of the patterned mask layer before the first etching process is performed.

3. The method of claim 1, wherein top surfaces of the patterned mask layer and the first conductive layer are exposed after the first etching process is performed.

4. The method of claim 1, wherein the spacer has a convex surface facing a center of the opening before the oxidation process is performed.

5. The method of claim 1, wherein a portion of the spacer and a portion of the first conductive layer under the opening are converted to the oxide structure during the oxidation process.

6. The method of claim 1, wherein a bottom surface of the oxide structure is lower than a bottom surface of the patterned mask layer.

7. The method of claim 1, wherein a remaining portion of the spacer has a concave surface facing the oxide structure after the oxidation process.

8. The method of claim 1, wherein the oxide structure protrudes from a top surface of the patterned mask layer.

9. The method of claim 1, wherein the patterned mask layer and a portion of the first conductive layer covered by the patterned mask layer are removed during the second etching process.

10. The method of claim 1, wherein the spacer and the first conductive layer are made of the same material, and the floating gate is composed of a remaining portion of the spacer and a remaining portion of the first conductive layer after the second etching process is performed.

11. The method of claim 1, wherein the source region and the drain region are formed by implanting ions into a semiconductor substrate, and the floating gate is located between the source region and the drain region.

12. The method of claim 1, further comprising:

forming a dielectric layer to cover a sidewall of the floating gate; and

a control gate is formed on the semiconductor substrate, wherein the control gate extends over the oxide structure.

13. The method of claim 12, wherein the control gate covers a ledge of the oxide structure, the ledge having a rounded top surface, and wherein the gate electrode is separated from the floating gate by the dielectric layer.

14. A flash memory, comprising:

a floating gate disposed on a semiconductor substrate, wherein a first edge of the floating gate is a first tip, and a second edge of the floating gate is a second tip;

an oxide structure disposed on the floating gate, wherein a first protruding portion of the oxide structure is located directly above the first tip, and a second protruding portion of the oxide structure is located directly above the second tip;

a dielectric structure disposed under the floating gate and on a portion of the sidewall of the floating gate, wherein the bottom of the floating gate is embedded in the dielectric structure; and

a source region and a drain region disposed in the semiconductor substrate, and the floating gate is disposed between the source region and the drain region.

15. The flash memory of claim 14 wherein said floating gate has a thickness that decreases from said first edge and said second edge toward a middle portion of said floating gate such that said floating gate has a concave top surface.

16. The flash memory of claim 14 wherein the first ledge and the second ledge of the oxide structure have rounded top surfaces.

17. The flash memory of claim 14 wherein the oxide structure has a planar top surface between the first protruding portion and the second protruding portion.

18. The flash memory of claim 14, further comprising:

a dielectric layer covering a sidewall of the floating gate; and

a control gate disposed on the semiconductor substrate, wherein the control gate extends over the first protruding portion of the oxide structure.

19. The flash memory of claim 18 wherein said floating gate and said control gate are made of polysilicon.

20. The flash memory of claim 18 wherein the control gate is separated from the floating gate by the dielectric layer and the control gate does not cover the second protruding portion of the oxide structure.