CN110059492B - AES encryption circuit capable of detecting errors based on double-path complementary structure - Google Patents
AES encryption circuit capable of detecting errors based on double-path complementary structure Download PDFInfo
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- CN110059492B CN110059492B CN201910258257.XA CN201910258257A CN110059492B CN 110059492 B CN110059492 B CN 110059492B CN 201910258257 A CN201910258257 A CN 201910258257A CN 110059492 B CN110059492 B CN 110059492B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/30—Authentication, i.e. establishing the identity or authorisation of security principals
- G06F21/45—Structures or tools for the administration of authentication
- G06F21/46—Structures or tools for the administration of authentication by designing passwords or checking the strength of passwords
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/60—Protecting data
- G06F21/602—Providing cryptographic facilities or services
Abstract
The invention discloses an AES encryption circuit capable of detecting errors based on a two-way complementary structure, which comprises: a key expansion unit, a conventional AES encryption circuit unit, a complementary AES encryption circuit unit, and a selector. The AES encryption circuit can defend power consumption attack and also can defend error injection attack; by designing the complementary AES encryption unit, the Hamming weight of data in the circuit is kept unchanged when the circuit processes different data; whether the encryption circuit is abnormal or not is judged through the result value of the exclusive OR operation of the output of the conventional AES encryption circuit unit and the output of the complementary AES encryption circuit unit, so that the output of the selector is controlled, and the error injection attack is effectively prevented.
Description
Technical Field
The invention relates to the technical field of implementation of cryptographic circuits, in particular to an AES (advanced encryption Standard) encryption circuit capable of detecting errors based on a double-path complementary structure.
Background
Advanced Encryption Standard (AES), also known as Rijndael Encryption method, is designed by belgium cryptologists Joan Daemen and Vincent Rijmen, and is a new generation of block symmetric cryptographic algorithm established in 2001 by the national institute of standards and technology, which is used to replace the original Data Encryption Standard (DES). The AES cipher algorithm is an iterative, symmetric block cipher algorithm with a data block length of 128 bits and key lengths of 128, 192 and 256 bits. According to the three different key lengths, the encryption process needs to perform 10, 12 and 14 rounds of transformation operations respectively, and each round of transformation operation comprises four sub-operations of byte replacement, row shifting, column mixing and key addition except for the last round. To eliminate symmetry, the last round of transformation does not contain a column mix operation and a key addition operation is added before the first round of transformation.
According to different application requirements, the AES encryption circuit adopts different implementation architectures. Referring to fig. 3 (a) and 3 (b), AES encryption circuit implementation architectures can be generally divided into two types: a cyclic deployment configuration and a fully deployed configuration. In a cyclic deployment structure use is made of N k (1≤N k ≤N r ,N r = 10/12/14) round transform units (including independent key addition operations), the loop unrolling structure requires less circuit area than the full unrolling structure, especially when N k 1 hour (N) k And =1, also referred to as a full-loop structure), the loop deployment structure has a minimum circuit area. But the loop unrolling structure requires iteration
The final result can be obtained, and thus the data processing speed is low. The circular expansion structure is used in occasions requiring small circuit area and low data rate, such as a wireless sensor network, RFID and the like. The loop unrolling structure may also compromise circuit area and speed according to specific application requirements. The fully-unfolded structure uses N r The circuit area of the round conversion circuit unit is large, but data does not need to be fed back, and the data processing speed is high. The fully expanded structure can also accelerate the data processing speed by increasing the number of pipeline stages. The full expansion structure is suitable for high-speed data real-time processing occasions, such as real-time video signal transmission and the like.
Power consumption attacks, also known as Power Analysis (Power Analysis), are based on the correlation between the Power consumed by the cryptographic chip and the intermediate values of the key and algorithm. The extensive use of CMOS logic in integrated circuits causes power consumption to be related to the input and output transition states of the circuit, and more power is consumed when the CMOS cells have signal transitions. In the power consumption attack process, a certain mapping relation needs to be established between the intermediate result of the encryption or decryption operation and the power consumption consumed by the cryptographic chip, so that the value of the key is estimated according to the power consumption data analysis. Currently, common Power attacks can be classified into Simple Power Attack (SPA), differential Power Attack (DPA), and High-Order Differential Power Attack (HO-DPA). The power consumption attack is simple to realize, expensive professional equipment is not needed, and the key search space is small, so that the power consumption attack is the most important and most common attack means in the bypass attack and is also a bypass attack technology which forms the most serious threat to a crypto chip.
For power consumption attack and the requirement of some extreme condition application environments on high reliability of equipment, the traditional defense approaches can be roughly divided into two categories: firstly, the fluctuation of a power consumption curve is reduced, and the useful information quantity is reduced, so that the signal-to-noise ratio is reduced; secondly, the purpose of reducing the signal to noise ratio is achieved by increasing random noise and redundant power consumption. Common power attack defense measures mainly include a random mask technology, a constant power consumption technology and the like.
The error injection attack is a bypass attack mode aiming at a cryptosystem, an attacker injects errors into a cryptosystem hardware circuit through means of electromagnetism, laser and the like to enable a cryptosystem to generate error messages, so that a decryption party cannot obtain correct information authentication to reject service, and further, the attacker can obtain a system key through differential error analysis. And in addition, the other extreme condition application environments, such as high-altitude environment and deep sea environment, have higher requirements on equipment reliability.
For the requirements of error injection attacks and application environments with extreme conditions on high reliability of equipment, the conventional solution mainly adopts a structural redundancy error detection mechanism, that is, a plurality of circuits with the same function are adopted, the same group of data is processed at the same time, and result data is compared.
Disclosure of Invention
The invention aims to solve the technical problem of providing an AES encryption circuit capable of detecting errors based on a two-way complementary structure, which can solve the problem that the existing AES encryption circuit cannot defend against power consumption attack and error injection attack.
In order to solve the above technical problem, the present invention provides an AES encryption circuit based on a two-way complementary structure and capable of detecting errors, including: the device comprises a key expansion unit, a conventional AES encryption circuit unit, a complementary AES encryption circuit unit and a selector; the conventional AES encryption circuit unit is of a full expansion structure and comprises N r A wheel conversion unit, wherein N r The number of round conversion operations specified by the AES standard; the complementary AES encryption circuit unit comprises N r A complementary wheel changing unit; the initial key input key expansion unit performs key expansion to obtain the round keys of the current round transformation unit and the complementary round transformation unit and respectively input the round keys into a key addition unit and a complementary round key addition unit of the two units; <xnotran> AES C AES C ' , C ⊕ C ' =128'h ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff; </xnotran> The output of the conventional AES encryption circuit unit and the output of the complementary AES encryption circuit unit are subjected to exclusive OR operation, and the result value is used as a control signal of the selector; one input end of the selector is connected with the output of the conventional AES encryption circuit unit, and the other input end of the selector is inputted with 128' b0; the output of the selector is the output ciphertext of the designed AES encryption circuit.
Preferably, the input plaintext and the output ciphertext of the complementary AES encryption circuit unit are 128 bits respectively, and comprise N r A complementary wheel changing unit, wherein N r The input of complementary round transform 1 is the data obtained after the input plaintext is bitwise inverted and is XOR-operated with the initial key, 1 st to Nth r The 1 round of complementary round transformation units have the same structure and are respectively composed of a complementary byte replacement unit, a complementary row shifting unit, a complementary column mixing unit and a complementary key adding unit which are connected in sequence; n th r The round complementary round conversion unit comprises a complementary byte replacement unit, a complementary row shifting unit and a complementary key adding unit which are connected in sequence, and does not comprise a complementary column mixing unit.
Preferably, the complementary byte replacement unit realizes the byte replacement function through a complementary S-box circuit, and the complementary byte replacement unit comprises 16 complementary S-box circuits connected in parallel; the complementary S-boxes are implemented using LUT structures.
Preferably, the input data of the complementary round conversion 1 is the input of the complementary AES encryption circuit unit, which is divided into 16 8-bit data packets, and the 16 data packets are input into the 16 complementary S-box circuits respectively to implement complementary byte replacement operation; the output results of the 16 complementary S-box circuits are combined into 128-bit data, and the data is used as the result of the complementary byte replacement unit in the complementary round conversion unit of the current round and is sent to the complementary row shifting unit in the complementary round conversion unit of the current round.
Preferably, the complementary row shifting unit processes the input 128-bit data according to the row shifting operation rule specified by the AES standard, and the result is input to the complementary column mixing unit; the complementary column mixing unit processes the input 128-bit data according to the column mixing operation rule specified by the AES standard, and the result is input into the complementary key adding unit; the complementary key adding unit outputs the input data and the round key after carrying out XOR; n th r And the output result of the round complementary round conversion unit is the complementary ciphertext output by the complementary AES encryption circuit.
Preferably, the conventional AES encryption circuit unit is a general AES encryption circuit specified by the AES standard and has a full expansion structure; the conventional AES encryption circuit unit corresponds to the complementary AES encryption circuit unit in structure, and comprises N r Wheel changing units, 1 st to N th r The 1-round wheel transformation units have the same structure and are composed of a byte replacement unit, a row shifting unit, a column mixing unit and a key adding unit which are connected in sequence; n th r The round wheel conversion unit comprises a byte replacement unit, a row shift unit and a key addition unit which are connected in sequence, and does not comprise a column mixing unit.
Preferably, the complementary AES encryption circuit unit and the conventional AES encryption circuit unit are complementary, and if the inputs are complementary, the complementary two circuits will produce complementary outputs, while their internal units are also complementary, i.e. the complementary byte replacement unit is complementary to the byte replacement unit, the complementary round transformation unit is complementary to the round transformation unit, the complementary S-box is complementary to the S-box, the complementary column mixing unit is complementary to the column mixing unit, and the complementary key addition unit is complementary to the key addition unit.
The invention has the beneficial effects that: the AES encryption circuit can defend power consumption attack and also can defend error injection attack; by designing the complementary AES encryption unit, the Hamming weight of data in the circuit is kept unchanged when the circuit processes different data; whether the encryption circuit is abnormal or not is judged through the result value of the output of the conventional AES encryption circuit unit and the output of the complementary AES encryption circuit unit after the XOR operation, so that the output of the selector is controlled, and the error injection attack is effectively prevented.
Drawings
Fig. 1 is a schematic diagram of a complementary AES encryption circuit unit.
Fig. 2 is a schematic diagram of an AES encryption circuit with error detection based on a two-way complementary structure according to the present invention.
FIG. 3 (a) is a schematic diagram of a loop expansion structure of an AES encryption circuit.
Fig. 3 (b) is a schematic diagram of a fully expanded structure of the AES encryption circuit.
FIG. 4 shows the present invention N r The schematic diagram of a part of simulation of the AES encryption circuit based on two-way complementary structure with error detection disclosed in = 10.
Detailed Description
As shown in FIG. 1, an AES encryption circuit with error detection capability based on a two-way complementary structure, wherein the input plaintext and the output ciphertext C' are 128-bit data packets, and the key is the number of key bits specified by the AES standard and comprises N r (N r Number of round conversion operations specified for AES standard) complementary round conversion units (complementary round conversion 1, complementary round conversion 2, \ 8230;, complementary round conversion N r ) The input of the complementary round transform 1 is the data obtained by performing XOR operation on the input plaintext after bitwise negation and the initial secret key, from the 1 st to the Nth r The 1 round of complementary wheel transformation units have the same structure and are composed of a complementary byte replacement unit, a complementary row shifting unit, a complementary column mixing unit and a complementary key adding unit which are connected in sequence; n th r The round complementary round conversion unit comprises a complementary byte replacement unit, a complementary row shifting unit and a complementary key adding unit which are connected in sequence, and does not comprise a complementary column mixing unit.
The complementary byte replacement unit realizes a byte replacement function through a complementary S box circuit, and comprises 16 complementary S box circuits connected in parallel; the complementary S box is realized by adopting an LUT structure; the values obtained by subjecting the data to the complementary S-box process are shown in table 1, and it can be seen from table 1 that: in the case where the inputs of the complementary S-boxes are complementary to the inputs of the normal S-boxes, their output results are also complementary (e.g., S (00) =63, complementary S (ff) =9 c).
Table 1 values of data obtained by complementary S-box processing
The input data of the complementary wheel transformation 1 unit is the input of a complementary AES encryption circuit unit, is divided into 16 8-bit data packets, and is respectively input into the 16 complementary S-box circuits to realize complementary byte replacement operation; the output results of the 16 complementary S-box circuits are combined into 128-bit data, and the 128-bit data is used as the result of the complementary byte replacement unit in the complementary round conversion unit of the current round and is sent to the complementary row shifting unit in the complementary round conversion unit of the current round.
For linear transformation, complementary input can generate complementary output, and the complementary row shifting unit processes the input 128-bit data according to the row shifting operation rule specified by the AES standard, and the result is input into the complementary column mixing unit; the complementary column mixing unit processes the input 128-bit data according to the column mixing operation rule specified by the AES standard, and the result is input into the complementary key adding unit; the complementary key adding unit outputs the input data and the round key after carrying out XOR; n th r The output result of the round complementary round conversion unit is the complementary ciphertext C' output by the complementary AES encryption circuit.
Referring to fig. 2, an error-detectable AES encryption circuit based on two-way complementation includes a key expansion unit and a conventional AES encryption circuitThe device comprises a meta encryption circuit unit, a complementary AES encryption circuit unit and a selector. The conventional AES encryption circuit unit is of a full expansion structure and comprises N r (N r Number of round conversion operations specified by AES Standard) round conversion units (round conversion 1, round conversion 2, \8230;, round conversion N r ) (ii) a The initial key input key expansion unit performs key expansion to obtain round keys of the current round transformation unit and the complementary round transformation unit and respectively input the round keys into a key addition unit and a complementary round key addition unit in the two units; the internal units of the conventional AES encryption circuit unit and the complementary AES encryption circuit unit are all complementary, that is, there are HW (row shift) + HW (complementary row shift) = HW (column mix) + HW (complementary column mix) = HW (byte replace) + HW (complementary byte replace) = HW (key plus) + HW (complementary key plus) =128 (where HW represents hamming weight); the output C of the conventional AES encryption circuit unit is complementary to the output C 'of the complementary AES encryption circuit unit, namely C ^ C' =128 '(C) + HW (C') =128; the result value of the output C of the conventional AES encryption circuit unit and the output C' of the complementary AES encryption circuit unit after the XOR operation is used as a control signal of the selector; one input end of the selector is connected with the output of the conventional AES encryption circuit unit, and the other input end of the selector is inputted with 128' b0; the output of the selector is the output ciphertext of the designed AES encryption circuit; <xnotran> C ⊕ C ' ≠ 128'h ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff , , , 128'b0; </xnotran> <xnotran> C ⊕ C '=128'h ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff , , C. </xnotran>
Referring to FIG. 4, FIG. 4 is N r The patent number =10 discloses a partial simulation diagram of an AES encryption circuit based on a two-way complementary structure and capable of detecting errors. Wherein, round _ data _ out1, round _ data _ out2, round _ data _ out9 and Round _ data _ out10 are respectively the output of Round transform 1, round transform 2, round transform 9 and Round transform 10 in the conventional AES encryption circuit unit, while Round _ data _ out1, round _ data _ out2, round _ data _ out9 and Round _ data _ out10 are respectively complementary Round transform 1, complementary Round transform 2, complementary Round transform 9 and complementary Round transform 10 in the complementary AES encryption circuit unitThe output of the wheel transform 10. As can be seen from fig. 4: round _ data _ out1 is complementary to Round _ data _ out1, round _ data _ out2 is complementary to Round _ data _ out2, round _ data _ out9 is complementary to Round _ data _ out9, and Round _ data _ out10 is complementary to Round _ data _ out 10.
The invention provides an error-detectable AES encryption circuit based on a double-path complementary structure, which is characterized in that by using a designed complementary AES encryption circuit and a conventional AES encryption circuit, when a target AES encryption circuit processes the same group of data, the Hamming weight of data processed inside the circuit is constant, the theoretical basis of power consumption attack based on a Hamming weight model is destroyed, the power consumption of the circuit is balanced and unchanged, and the correlation between the data processed by the circuit and a circuit key is destroyed, so that the goal of defending the power consumption attack is realized; whether the encryption circuit is abnormal or not is judged through the result value of the output of the conventional AES encryption circuit unit and the output of the complementary AES encryption circuit unit after the XOR operation, the output of the selector is further controlled, the output of the error ciphertext when the error injection attack occurs is effectively blocked, the error injection attack is effectively prevented, and the safety of the encryption circuit is improved.
Claims (7)
1. An AES encryption circuit capable of detecting errors based on a two-way complementary structure is characterized by comprising: the encryption device comprises a key expansion unit, a conventional AES encryption circuit unit, a complementary AES encryption circuit unit and a selector; the conventional AES encryption circuit unit is of a full expansion structure and comprises N r A wheel conversion unit, wherein N r The number of round transform operations specified by the AES standard; the complementary AES encryption circuit unit comprises N r A complementary wheel changing unit; the initial key input key expansion unit performs key expansion to obtain the round keys of the current round transformation unit and the complementary round transformation unit and respectively input the round keys into a key addition unit and a complementary round key addition unit of the two units; <xnotran> AES C AES C ' , C ⊕ C ' =128'h ffff_ffff_ffff_ffff_ffff_ffff_ffff_ffff; </xnotran> The output of the conventional AES encryption circuit unit and the output of the complementary AES encryption circuit unit are subjected to exclusive OR operationThe result value is used as a control signal of the selector; one input end of the selector is connected with the output of the conventional AES encryption circuit unit, and the other input end of the selector is inputted with 128' b0; the output of the selector is the output ciphertext of the designed AES encryption circuit.
2. The AES encryption circuit with two-way complementary structure and capable of detecting errors as claimed in claim 1, wherein the input plaintext and the output ciphertext of the complementary AES encryption circuit unit are 128 bits each, including N r A complementary wheel changing unit, wherein N r The input of the complementary round transform 1 is the data obtained by the XOR operation of the input plaintext after bit-wise negation and the initial key, the 1 st to the Nth round r The 1 round of complementary wheel transformation units have the same structure and are composed of a complementary byte replacement unit, a complementary row shifting unit, a complementary column mixing unit and a complementary key adding unit which are connected in sequence; n th r The round complementary round conversion unit comprises a complementary byte replacement unit, a complementary row shifting unit and a complementary key adding unit which are connected in sequence, and does not comprise a complementary column mixing unit.
3. The two-way complementary structure-based error-detectable AES encryption circuit as claimed in claim 2, wherein the complementary byte substitution unit implements a byte substitution function by a complementary S-box circuit, the complementary byte substitution unit including 16 parallel complementary S-box circuits; the complementary S-boxes are implemented using LUT structures.
4. The AES encryption circuit with error detection capability based on two-way complementary structure as claimed in claim 2, wherein the input data of complementary round transform 1 is the input of the complementary AES encryption circuit unit, which is divided into 16 8-bit data packets, which are respectively input into the 16 complementary S-box circuits to implement complementary byte replacement operation; the output results of the 16 complementary S-box circuits are combined into 128-bit data, and the data is used as the result of the complementary byte replacement unit in the complementary round conversion unit of the current round and is sent to the complementary row shifting unit in the complementary round conversion unit of the current round.
5. The AES encryption circuit with two-way complementary structure based error detectable in claim 2, wherein the complementary row shift unit processes the input 128-bit data according to the row shift operation rule specified by the AES standard, and the result is input to the complementary column mixing unit; the complementary column mixing unit processes the input 128-bit data according to the column mixing operation rule specified by the AES standard, and the result is input into the complementary key adding unit; the complementary key adding unit outputs the input data and the round key after carrying out XOR; n th r And the output result of the round complementary round conversion unit is the complementary ciphertext output by the complementary AES encryption circuit.
6. The AES encryption circuit with two-way complementary structure capable of detecting errors as claimed in claim 1, wherein the conventional AES encryption circuit unit is a general AES encryption circuit specified by AES standard and is of a fully expanded structure; the conventional AES encryption circuit unit corresponds to the complementary AES encryption circuit unit in structure, and comprises N r Wheel changing units, 1 st to N th r The 1 round of wheel transformation units have the same structure and are composed of a byte replacement unit, a row shifting unit, a column mixing unit and a key adding unit which are connected in sequence; n th r The round wheel conversion unit comprises a byte replacement unit, a row shift unit and a key addition unit which are connected in sequence, and does not comprise a column mixing unit.
7. The double-way complementary structure-based error-detectable AES encryption circuit as claimed in claim 1, wherein the complementary AES encryption circuit unit and the conventional AES encryption circuit unit are complementary, if the inputs are complementary, the complementary two circuits will produce complementary outputs, while their internal units are also complementary, i.e., the complementary byte replacing unit and the byte replacing unit are complementary, the complementary round transforming unit and the round transforming unit are complementary, the complementary S-box and the S-box are complementary, the complementary column mixing unit and the column mixing unit are complementary, and the complementary key adding unit and the key adding unit are complementary.
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