CN110059019B - Memory address allocation method and device, computing equipment and storage medium - Google Patents

Memory address allocation method and device, computing equipment and storage medium Download PDF

Info

Publication number
CN110059019B
CN110059019B CN201910308438.9A CN201910308438A CN110059019B CN 110059019 B CN110059019 B CN 110059019B CN 201910308438 A CN201910308438 A CN 201910308438A CN 110059019 B CN110059019 B CN 110059019B
Authority
CN
China
Prior art keywords
memory
class
memory unit
label
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201910308438.9A
Other languages
Chinese (zh)
Other versions
CN110059019A (en
Inventor
赵博强
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangzhou Xishanju Network Technology Co ltd
Zhuhai Kingsoft Digital Network Technology Co Ltd
Original Assignee
Guangzhou Xishanju Network Technology Co ltd
Zhuhai Kingsoft Online Game Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangzhou Xishanju Network Technology Co ltd, Zhuhai Kingsoft Online Game Technology Co Ltd filed Critical Guangzhou Xishanju Network Technology Co ltd
Priority to CN201910308438.9A priority Critical patent/CN110059019B/en
Publication of CN110059019A publication Critical patent/CN110059019A/en
Application granted granted Critical
Publication of CN110059019B publication Critical patent/CN110059019B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/0223User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023Free address space management
    • G06F12/0238Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory

Abstract

The application provides a memory address allocation method and device, a computing device and a storage medium, wherein the method comprises the following steps: defining a label of each class, and allocating a corresponding first memory unit list to the label of each class, wherein the first memory unit list comprises a plurality of first memory unit addresses; and generating a first memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding first memory unit list, wherein the label of the class can be obtained only by combining the address of the memory unit during reading, and the class label does not need to be marked separately as in the prior art, so that the storage space for the part of the labels is saved, and the data access and processing efficiency is greatly improved.

Description

Memory address allocation method and device, computing equipment and storage medium
Technical Field
The present application relates to the field of internet technologies, and in particular, to a method and an apparatus for allocating memory addresses, a computing device, and a storage medium.
Background
Reflection is the ability of a program to access, detect, and modify its own state or behavior, and is supported in many languages, such as Java, C + +, and the like.
Taking Java as an example: in the running state, the Java reflection mechanism in the prior art can obtain all the properties and methods of any class and can call any property and method of any object. This functionality of dynamically obtaining information and dynamically invoking methods of objects at runtime is referred to as the Java's reflection mechanism.
The Class supports the concept of reflection together with the java. These types of objects are created at runtime by a JVM (Java Virtual Machine) to represent the corresponding members in the unknown class. These type objects also become class labels, and when creating each class, the corresponding label of the class must be created at the same time for marking the class. When a data read call is made, the contents of the tag must be read before the specific contents of the class can be identified.
The class in the C + + language includes an ID (tag of the class) for identifying the content of the class, or an RTTI (Run-Time Type Identification) and a V-table (virtual function table) for storing the class. However, the labels of the class occupy a large storage space, for example, in C + + language, the storage space occupied by a class is usually 128 bits, and the space with 64 bits therein is the label content of the class. In this way, the tag occupies half of the memory space, thus resulting in very inefficient data access.
Disclosure of Invention
In view of this, embodiments of the present application provide a method and an apparatus for allocating a memory address, a computing device, and a storage medium, so as to solve technical defects in the prior art.
The embodiment of the application provides a memory address allocation method, which comprises the following steps:
defining a label of each class, and allocating a corresponding first memory unit list to the label of each class, wherein the first memory unit list comprises a plurality of first memory unit addresses;
and generating a first memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding first memory unit list.
Optionally, the method further comprises:
under the condition of receiving an object generation instruction, determining a class corresponding to the object;
searching a corresponding first memory allocation instruction according to the class label, and determining a first memory unit list corresponding to the class label according to the first memory allocation instruction;
and allocating an unoccupied first memory cell address in the first memory cell list to the object.
Optionally, the method further comprises:
generating specification parameters of the class according to the label of the class;
generating a corresponding first memory block size parameter according to the number of first memory unit addresses in the first memory unit list;
and generating a first memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the first memory block and the first memory unit list.
Optionally, the first memory cell list includes N first memory cell addresses, where N is greater than or equal to 2;
assigning an unoccupied first memory cell address in the first memory cell list to the object, including:
s1, checking whether the ith first memory cell address in the first memory cell list is occupied, if so, executing S2, otherwise, executing S3, wherein i is more than or equal to 1 and less than or equal to N;
s2, adding 1 to i, judging whether i after adding 1 is smaller than N, if yes, executing step S1, and if not, executing step S4;
s3, allocating the ith first memory unit address to the object;
and S4, returning a distribution failure notice.
Optionally, the method further comprises:
under the condition that the first memory unit addresses in the first memory unit list corresponding to the class are all occupied, a corresponding second memory unit list is distributed for the labels of the class again, wherein the second memory unit list comprises a plurality of second memory unit addresses;
and generating a second memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding second memory unit list.
Optionally, the method further comprises:
under the condition of receiving an object generation instruction, determining a class corresponding to the object;
searching a corresponding second memory allocation instruction according to the class label, and determining a second memory unit list corresponding to the class label according to the second memory allocation instruction;
and allocating an unoccupied second memory cell address in the second memory cell list to the object.
Optionally, the method further comprises:
generating specification parameters of the class according to the label of the class;
generating a second memory block size parameter according to the number of second memory unit addresses in the second memory unit list;
and generating a second memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the second memory block and the second memory unit list.
Optionally, each of the first memory unit addresses includes a plurality of memory addresses, and the plurality of first memory unit addresses in the first memory unit list are consecutive memory addresses;
each of the second memory cell addresses includes a plurality of memory addresses, and the plurality of second memory cell addresses in the second memory cell list are consecutive memory addresses.
The embodiment of the application discloses a memory address allocation device, the device comprises:
a memory unit allocation module configured to define a tag of each class and allocate a corresponding first memory unit list to the tag of each class, wherein the first memory unit list includes a plurality of first memory unit addresses;
and the memory allocation instruction generating module is configured to generate a first memory allocation instruction corresponding to the tag of each class according to the tag of each class and the corresponding first memory unit list.
Optionally, the apparatus further comprises:
the first class determination module is configured to determine a class corresponding to an object under the condition that an object generation instruction is received;
the first searching module is configured to search a corresponding first memory allocation instruction according to the class label, and determine a first memory unit list corresponding to the class label according to the first memory allocation instruction;
a first object allocation module configured to allocate an unoccupied first memory cell address in the first memory cell list to the object.
Optionally, the memory allocation instruction generating module is further configured to:
generating specification parameters of the class according to the label of the class;
generating a corresponding first memory block size parameter according to the number of first memory unit addresses in the first memory unit list;
and generating a first memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the first memory block and the first memory unit list.
Optionally, the first memory cell list includes N first memory cell addresses, where N is greater than or equal to 2;
the first object assigning module is specifically configured to:
s1, checking whether the ith first memory cell address in the first memory cell list is occupied, if so, executing S2, otherwise, executing S3, wherein i is more than or equal to 1 and less than or equal to N;
s2, adding 1 to i, judging whether i after adding 1 is smaller than N, if yes, executing step S1, and if not, executing step S4;
s3, allocating the ith first memory unit address to the object;
and S4, returning a distribution failure notice.
Optionally, the memory unit allocation module is further configured to: under the condition that the first memory unit addresses in the first memory unit list corresponding to the class are all occupied, a corresponding second memory unit list is distributed for the labels of the class again, wherein the second memory unit list comprises a plurality of second memory unit addresses;
the memory allocation instruction generation module is further configured to: and generating a second memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding second memory unit list.
Optionally, the apparatus further comprises:
the second class determination module is configured to determine a class corresponding to the object under the condition that an object generation instruction is received;
the second searching module is configured to search a corresponding second memory allocation instruction according to the class label, and determine a second memory unit list corresponding to the class label according to the second memory allocation instruction;
a second object allocation module configured to allocate an unoccupied second memory cell address in the second memory cell list to the object.
Optionally, the memory allocation instruction generating module is further configured to: generating specification parameters of the class according to the label of the class; generating a second memory block size parameter according to the number of second memory unit addresses in the second memory unit list; and generating a second memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the second memory block and the second memory unit list.
Optionally, each of the first memory unit addresses includes a plurality of memory addresses, and the plurality of first memory unit addresses in the first memory unit list are consecutive memory addresses;
each of the second memory cell addresses includes a plurality of memory addresses, and the plurality of second memory cell addresses in the second memory cell list are consecutive memory addresses.
The embodiment of the application discloses computing equipment, which comprises a storage, a processor and computer instructions which are stored on the storage and can run on the processor, wherein the processor executes the instructions to realize the steps of the memory address allocation method.
The embodiment of the application discloses a computer readable storage medium, which stores computer instructions, and the instructions are executed by a processor to realize the steps of the memory address allocation method.
According to the memory address allocation method and device, the corresponding first memory unit list is allocated through each class of tag, then the first memory allocation instruction corresponding to each class of tag is generated according to each class of tag and the corresponding first memory unit list, the class of tag can be obtained only by combining the memory unit address during reading, and the class of tag does not need to be marked by using an ID or a V-table as in the prior art, so that the storage space for the part of the class of tag is saved, and the data access and processing efficiency is greatly improved.
In addition, under the condition that the first memory cell address is completely occupied, the method of this embodiment may further allocate a corresponding second memory cell list according to the class label, so as to ensure that each object of the class may be allocated to a corresponding memory cell address.
Drawings
FIG. 1 is a schematic block diagram of a computing device according to an embodiment of the present application;
fig. 2 is a schematic flowchart illustrating a memory address allocation method according to an embodiment of the present application;
fig. 3 is a schematic flowchart illustrating a memory address allocation method according to an embodiment of the present application;
fig. 4 is a schematic flowchart illustrating a memory address allocation method according to an embodiment of the present application;
FIG. 5 is a diagram illustrating a first memory allocation instruction according to an embodiment of the present application;
fig. 6 is a schematic flowchart of a memory address allocation method according to another embodiment of the present application;
FIG. 7 is a diagram illustrating a first memory allocation command and a second memory allocation command according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of an apparatus for allocating memory addresses according to another embodiment of the present application.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of implementation in many different ways than those herein set forth and of similar import by those skilled in the art without departing from the spirit of this application and is therefore not limited to the specific implementations disclosed below.
The terminology used in the description of the one or more embodiments is for the purpose of describing the particular embodiments only and is not intended to be limiting of the description of the one or more embodiments. As used in one or more embodiments of the present specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used in one or more embodiments of the present specification refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein in one or more embodiments to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, a first can also be referred to as a second and, similarly, a second can also be referred to as a first without departing from the scope of one or more embodiments of the present description. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
First, the noun terms to which one or more embodiments of the present invention relate are explained.
Class (class): an abstraction of an object with the same properties (data elements) and behaviors (functions) is a class. A class is actually a type of data. A class is a static concept, and does not carry any data itself. When no objects are created for a class, the class itself is not present in the memory space. Classes have tags, which are abstractions of the state of objects, with data structures describing the properties of the class.
Object (object): an object is anything one wants to research on, which can represent not only concrete things, but also abstract rules, plans or events. An object has a state, and an object describes its state with a data value. The relationship of a class to an object is as for a mold and a casting, the materialization of a class results in an object, and the abstraction of an object results in a class.
In the present application, a memory address allocation method and apparatus, a computing device, and a storage medium are provided, and details are described in the following embodiments one by one.
Fig. 1 is a block diagram illustrating a configuration of a computing device 100 according to an embodiment of the present specification. The components of the computing device 100 include, but are not limited to, memory 110 and processor 120. The processor 120 is coupled to the memory 110 via a bus 130 and a database 150 is used to store data.
Computing device 100 also includes access device 140, access device 140 enabling computing device 100 to communicate via one or more networks 160. Examples of such networks include the Public Switched Telephone Network (PSTN), a Local Area Network (LAN), a Wide Area Network (WAN), a Personal Area Network (PAN), or a combination of communication networks such as the internet. Access device 140 may include one or more of any type of network interface (e.g., a Network Interface Card (NIC)) whether wired or wireless, such as an IEEE802.11 Wireless Local Area Network (WLAN) wireless interface, a worldwide interoperability for microwave access (Wi-MAX) interface, an ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a bluetooth interface, a Near Field Communication (NFC) interface, and so forth.
In one embodiment of the present description, the above-described components of computing device 100 and other components not shown in FIG. 1 may also be connected to each other, such as by a bus. It should be understood that the block diagram of the computing device architecture shown in FIG. 1 is for purposes of example only and is not limiting as to the scope of the description. Those skilled in the art may add or replace other components as desired.
Computing device 100 may be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (e.g., tablet, personal digital assistant, laptop, notebook, netbook, etc.), a mobile phone (e.g., smartphone), a wearable computing device (e.g., smartwatch, smartglasses, etc.), or other type of mobile device, or a stationary computing device such as a desktop computer or PC. Computing device 100 may also be a mobile or stationary server.
Wherein the processor 120 may perform the steps of the method shown in fig. 2. Fig. 2 is a schematic flowchart illustrating a memory address allocation method according to an embodiment of the present application, including steps 201 to 202.
201. Defining a tag of each class, and allocating a corresponding first memory cell list to the tag of each class, wherein the first memory cell list comprises a plurality of first memory cell addresses.
In this embodiment, the Memory unit address may be allocated by a Memory Allocator (Memory Allocator).
When creating a class, a label of the class must be created at the same time for marking the class. For example, the "Person" class is labeled "human", which may contain many individuals (objects), and the "Person" is a label for the class.
Memory addresses are typically represented using 4-bit 16-ary and 8-bit 16-ary. Taking a 4-bit 16-ary system as an example, the memory address 0x0001 represents a memory address numbered 1; for example, the 8-bit 16-ary memory address 0x00000001 represents the memory address numbered 1.
Specifically, each of the first memory unit addresses includes a plurality of memory addresses, and the first memory unit addresses included in the first memory unit list corresponding to the tag of each class may be continuous or discontinuous. In a specific implementation scheme, a label of a class is a, a memory address of a first memory unit corresponding to the class is 0x 0001-0 x0005, and a memory address of a second memory unit is 0x 0006-0 x 0010.
202. And generating a first memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding first memory unit list.
According to the memory address allocation method provided by the embodiment, the first memory allocation instruction corresponding to the tag of each class is generated according to the tag of each class and the corresponding first memory unit list, the tag of the class can be obtained only by combining the memory unit address during reading, and the tag of the class does not need to be marked by using an ID or a V-table as in the prior art, so that the storage space for the tag of the class is saved, and the data access and processing efficiency is greatly improved.
After the first memory allocation command is generated, an object is further generated for each class in a specific application. Referring to fig. 3, the method further comprises:
301. and under the condition of receiving an object generation instruction, determining a class corresponding to the object.
302. And searching a corresponding first memory allocation instruction according to the class label, and determining a first memory unit list corresponding to the class label according to the first memory allocation instruction.
303. And allocating an unoccupied first memory cell address in the first memory cell list to the object.
It should be noted that, for each object, only one first memory location address is allocated at a time. Thus, in the process of initially generating the memory allocation instruction, the number of the memory addresses included in each first memory unit address needs to be set in advance, for example, each first memory unit address includes 8 memory addresses.
Specifically, the first memory cell list includes N first memory cell addresses, where N is greater than or equal to 2, and step 303 includes the following steps 401 to 404:
401. and checking whether the ith first memory unit address in the first memory unit list is occupied, if so, executing step 402, otherwise, executing step 403, wherein i is more than or equal to 1 and is less than or equal to N.
402. And adding 1 to i, judging whether i after the 1 is added is smaller than N, if so, executing the step 401, and if not, executing the step 404.
403. Assigning the ith first memory cell address to the object.
404. And returning a distribution failure notice.
In addition, the generated first memory allocation instruction includes a class specification parameter and a first memory block size parameter, in addition to the class label and the first memory unit list corresponding to the label, which respectively represent the size of the space occupied by the class label and the size of the first memory unit.
The method further comprises the following steps:
and S11, generating the specification parameters of the class according to the label of the class.
S12, generating a corresponding first memory block size parameter according to the number of the first memory cell addresses in the first memory cell list.
S13, generating a first memory allocation command according to the label of each class, the specification parameter of the class, the size parameter of the first memory block and the first memory unit list.
Referring to fig. 5, fig. 5 is a schematic diagram of a first memory allocation instruction generated by using the allocation method of the present embodiment. In the illustrated first memory allocation instruction, the first memory allocation instruction includes:
class label (Type): a;
specification parameter (Typesize) of class: 17;
first memory chunk size parameter (countperchunk): 6;
first memory cell list (freecell): 0x10000000 to (0x10000000+6 17).
An embodiment of the present application discloses a method for allocating memory addresses, referring to fig. 6, including:
601. defining a tag of each class, and allocating a corresponding first memory cell list to the tag of each class, wherein the first memory cell list comprises a plurality of first memory cell addresses.
602. And generating a first memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding first memory unit list.
Steps 601 to 602 are the same as steps 201 to 202 of the previous embodiment, and the description of this embodiment is omitted.
603. And under the condition of receiving an object generation instruction, determining a class corresponding to the object.
604. And searching a corresponding first memory allocation instruction according to the class label, and determining a first memory unit list corresponding to the class label according to the first memory allocation instruction.
605. Checking whether the first memory cell addresses in the first memory cell list are all occupied, if so, executing step 606, and if not, executing step 607.
606. And allocating an unoccupied first memory cell address in the first memory cell list to the object.
It should be noted that, for each object, only one second memory location address is allocated at a time. Thus, in the process of initially generating the memory allocation instruction, the number of the memory addresses included in each second memory unit address needs to be set in advance, for example, each second memory unit address includes 8 memory addresses.
Specifically, the second memory cell list includes M second memory cell addresses, where M is greater than or equal to 2, and step 606 includes the following steps S6061 to S6064:
s6061, checking whether the jth second memory unit address in the second memory unit list is occupied, if so, executing step S6062, otherwise, executing step S6063, wherein j is more than or equal to 1 and is less than or equal to M.
S6062, self-increment j by 1, determine whether j after self-increment 1 is less than M, if yes, execute step S6061, if no, execute step S6064.
S6063, assign the jth second memory cell address to the object.
S6064 returns an assignment failure notification.
And under the condition that the second memory cell addresses of the second memory cell list are all occupied, a third memory cell list corresponding to the class label can be further generated. The generation method of the third memory cell list is similar to that of the second memory cell list, and details are not repeated in this embodiment.
607. And re-allocating a corresponding second memory cell list for the class of tags, wherein the second memory cell list comprises a plurality of second memory cell addresses.
Optionally, each second memory cell address includes a plurality of memory addresses, and the plurality of second memory cell addresses in the second memory cell list are consecutive memory addresses.
608. And generating a second memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding second memory unit list.
In addition, the generated second memory allocation instruction includes a class specification parameter and a second memory block size parameter, in addition to the class label and the second memory unit list corresponding to the label, which respectively represent the size of the space occupied by the class label and the size of the first memory unit.
The method further comprises the following steps:
and S21, generating the specification parameters of the class according to the label of the class.
S22, generating a second memory block size parameter according to the number of second memory cell addresses in the second memory cell list.
And S23, generating a second memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the second memory block and the second memory unit list.
Referring to fig. 7, fig. 7 is a schematic diagram of a first memory allocation command and a second memory allocation command generated by the allocation method of the present embodiment. In the illustrated first memory allocation instruction, the first memory allocation instruction includes:
class label (Type): b;
specification parameter (Typesize) of class: 30, of a nitrogen-containing gas;
first memory chunk size parameter (countperchunk): 3;
first memory cell list (freecell): 0. 1 and 2.
Wherein, 0, 1, 2 are the first memory unit serial number.
The second memory allocation instruction includes:
class label (Type): b;
specification parameter (Typesize) of class: 30, of a nitrogen-containing gas;
second memory chunk size parameter (countperchunk): 3;
second memory cell list (freecell): 3. 4 and 5.
Wherein 3, 4, and 5 are first memory unit serial numbers.
As can be seen, for the second memory allocation instruction, the tag of the class, the specification parameter of the class, and the second memory block size parameter are all consistent with the tag of the class, the specification parameter of the class, and the first memory block size parameter of the first memory allocation instruction.
According to the memory address allocation method, the corresponding first memory unit list is allocated through each class of tag, then the first memory allocation instruction corresponding to each class of tag is generated according to each class of tag and the corresponding first memory unit list, the class of tag can be obtained only by combining the memory unit address during reading, ID or V-table labeling class tags are not needed as in the prior art, and therefore storage space for the part of the class of tags is saved, and data access and processing efficiency is greatly improved.
In addition, although the field of the class label is added in the memory distributor in the application, a part of memory is occupied, compared with the prior art that the label of each class is marked by an extra ID or V-table, especially under the condition that the number of the classes is large, the memory is saved.
In addition, under the condition that the first memory cell address is completely occupied, the method of this embodiment may further allocate a corresponding second memory cell list according to the class label, so as to ensure that each object of the class may be allocated to a corresponding memory cell address.
An embodiment of the present application further discloses a device for allocating memory addresses, referring to fig. 8, where the device includes:
a memory unit allocation module 801 configured to define a tag of each class and allocate a corresponding first memory unit list to each tag of the class, where the first memory unit list includes a plurality of first memory unit addresses;
a memory allocation instruction generating module 802, configured to generate a first memory allocation instruction corresponding to the tag of each class according to the tag of each class and the corresponding first memory unit list.
Optionally, the apparatus further comprises:
a first class determining module 803, configured to determine, in a case that an object generating instruction is received, a class corresponding to the object;
a first searching module 804, configured to search for a corresponding first memory allocation instruction according to the class label, and determine a first memory unit list corresponding to the class label according to the first memory allocation instruction;
a first object assignment module 805 configured to assign an unoccupied first memory cell address in the first memory cell list to the object.
Optionally, the memory allocation instruction generating module 802 is further configured to:
generating specification parameters of the class according to the label of the class;
generating a corresponding first memory block size parameter according to the number of first memory unit addresses in the first memory unit list;
and generating a first memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the first memory block and the first memory unit list.
Optionally, the first memory cell list includes N first memory cell addresses, where N is greater than or equal to 2;
the first object assigning module 805 is specifically configured to:
s1, checking whether the ith first memory cell address in the first memory cell list is occupied, if so, executing S2, otherwise, executing S3, wherein i is more than or equal to 1 and less than or equal to N;
s2, adding 1 to i, judging whether i after adding 1 is smaller than N, if yes, executing step S1, and if not, executing step S4;
s3, allocating the ith first memory unit address to the object;
and S4, returning a distribution failure notice.
Optionally, the memory unit allocation module 801 is further configured to: under the condition that the first memory unit addresses in the first memory unit list corresponding to the class are all occupied, a corresponding second memory unit list is distributed for the labels of the class again, wherein the second memory unit list comprises a plurality of second memory unit addresses;
the memory allocation instruction generation module 802 is further configured to: and generating a second memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding second memory unit list.
Optionally, the apparatus further comprises:
a second class determination module 806 configured to, in a case where an object generation instruction is received, determine a class to which the object corresponds;
a second lookup module 807 configured to lookup a corresponding second memory allocation instruction according to the class tag, and determine a second memory unit list corresponding to the class tag according to the second memory allocation instruction;
a second object allocation module 808 configured to allocate an unoccupied second memory cell address in the second memory cell list to the object.
Optionally, the memory allocation instruction generating module 802 is further configured to: generating specification parameters of the class according to the label of the class; generating a second memory block size parameter according to the number of second memory unit addresses in the second memory unit list; and generating a second memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the second memory block and the second memory unit list.
Optionally, each of the first memory unit addresses includes a plurality of memory addresses, and the plurality of first memory unit addresses in the first memory unit list are consecutive memory addresses; each of the second memory cell addresses includes a plurality of memory addresses, and the plurality of second memory cell addresses in the second memory cell list are consecutive memory addresses.
According to the memory address allocation device provided by the embodiment, the first memory allocation instruction corresponding to the tag of each class is generated according to the tag of each class and the corresponding first memory unit list, the tag of the class can be obtained only by combining the memory unit address during reading, and the tag of the class does not need to be marked by using an ID or a V-table as in the prior art, so that the storage space for the tag of the class is saved, and the data access and processing efficiency is greatly improved.
An embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions, and the computer instructions, when executed by a processor, implement the steps of the memory address allocation method described above.
The above is an illustrative scheme of a computer-readable storage medium of the present embodiment. It should be noted that the technical solution of the storage medium and the technical solution of the memory address allocation method belong to the same concept, and details that are not described in detail in the technical solution of the storage medium can be referred to the description of the technical solution of the memory address allocation method.
The computer instructions comprise computer program code which may be in the form of source code, object code, an executable file or some intermediate form, or the like. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like.
It should be noted that, for the sake of simplicity, the above-mentioned method embodiments are described as a series of acts or combinations, but those skilled in the art should understand that the present application is not limited by the described order of acts, as some steps may be performed in other orders or simultaneously according to the present application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The preferred embodiments of the present application disclosed above are intended only to aid in the explanation of the application. Alternative embodiments are not exhaustive and do not limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and the practical application, to thereby enable others skilled in the art to best understand and utilize the application. The application is limited only by the claims and their full scope and equivalents.

Claims (16)

1. A method for allocating memory addresses, the method comprising:
defining a label of each class, and allocating a corresponding first memory unit list to the label of each class, wherein the first memory unit list comprises a plurality of first memory unit addresses, and the classes are sets of objects with the same characteristics and behaviors;
generating a first memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding first memory unit list;
under the condition of receiving an object generation instruction, determining a class corresponding to the object;
searching a corresponding first memory allocation instruction according to the class label, and determining a first memory unit list corresponding to the class label according to the first memory allocation instruction;
and allocating an unoccupied first memory cell address in the first memory cell list to the object.
2. The method of claim 1, wherein the method further comprises:
generating specification parameters of the class according to the label of the class;
generating a corresponding first memory block size parameter according to the number of first memory unit addresses in the first memory unit list;
and generating a first memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the first memory block and the first memory unit list.
3. The method of claim 1, wherein the first memory cell list includes N first memory cell addresses, where N ≧ 2;
assigning an unoccupied first memory cell address in the first memory cell list to the object, including:
s1, checking whether the ith first memory cell address in the first memory cell list is occupied, if so, executing S2, otherwise, executing S3, wherein i is more than or equal to 1 and less than or equal to N;
s2, adding 1 to i, judging whether i after adding 1 is smaller than N, if yes, executing step S1, and if not, executing step S4;
s3, allocating the ith first memory unit address to the object;
and S4, returning a distribution failure notice.
4. The method of claim 1, wherein the method further comprises:
under the condition that the first memory unit addresses in the first memory unit list corresponding to the class are all occupied, a corresponding second memory unit list is distributed for the labels of the class again, wherein the second memory unit list comprises a plurality of second memory unit addresses;
and generating a second memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding second memory unit list.
5. The method of claim 4, wherein the method further comprises:
under the condition of receiving an object generation instruction, determining a class corresponding to the object;
searching a corresponding second memory allocation instruction according to the class label, and determining a second memory unit list corresponding to the class label according to the second memory allocation instruction;
and allocating an unoccupied second memory cell address in the second memory cell list to the object.
6. The method of claim 4, wherein the method further comprises:
generating specification parameters of the class according to the label of the class;
generating a second memory block size parameter according to the number of second memory unit addresses in the second memory unit list;
and generating a second memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the second memory block and the second memory unit list.
7. The method of claim 4,
each first memory unit address comprises a plurality of memory addresses, and the plurality of first memory unit addresses in the first memory unit list are continuous memory addresses;
each of the second memory cell addresses includes a plurality of memory addresses, and the plurality of second memory cell addresses in the second memory cell list are consecutive memory addresses.
8. An apparatus for allocating memory addresses, the apparatus comprising:
a memory unit allocation module configured to define a tag of each class and allocate a corresponding first memory unit list to the tag of each class, where the first memory unit list includes a plurality of first memory unit addresses, and the classes are sets of objects having the same characteristics and behaviors;
a memory allocation instruction generating module configured to generate a first memory allocation instruction corresponding to the tag of each class according to the tag of each class and the corresponding first memory unit list;
the first class determination module is configured to determine a class corresponding to an object under the condition that an object generation instruction is received;
the first searching module is configured to search a corresponding first memory allocation instruction according to the class label, and determine a first memory unit list corresponding to the class label according to the first memory allocation instruction;
a first object allocation module configured to allocate an unoccupied first memory cell address in the first memory cell list to the object.
9. The apparatus of claim 8, wherein the memory allocation instruction generation module is further configured to:
generating specification parameters of the class according to the label of the class;
generating a corresponding first memory block size parameter according to the number of first memory unit addresses in the first memory unit list;
and generating a first memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the first memory block and the first memory unit list.
10. The apparatus of claim 8, wherein the first list of memory cells includes N first memory cell addresses, wherein N ≧ 2;
the first object assigning module is specifically configured to:
s1, checking whether the ith first memory cell address in the first memory cell list is occupied, if so, executing S2, otherwise, executing S3, wherein i is more than or equal to 1 and less than or equal to N;
s2, adding 1 to i, judging whether i after adding 1 is smaller than N, if yes, executing step S1, and if not, executing step S4;
s3, allocating the ith first memory unit address to the object;
and S4, returning a distribution failure notice.
11. The apparatus of claim 8, wherein the memory unit allocation module is further configured to: under the condition that the first memory unit addresses in the first memory unit list corresponding to the class are all occupied, a corresponding second memory unit list is distributed for the labels of the class again, wherein the second memory unit list comprises a plurality of second memory unit addresses;
the memory allocation instruction generation module is further configured to: and generating a second memory allocation instruction corresponding to the label of each class according to the label of each class and the corresponding second memory unit list.
12. The apparatus of claim 11, wherein the apparatus further comprises:
the second class determination module is configured to determine a class corresponding to the object under the condition that an object generation instruction is received;
the second searching module is configured to search a corresponding second memory allocation instruction according to the class label, and determine a second memory unit list corresponding to the class label according to the second memory allocation instruction;
a second object allocation module configured to allocate an unoccupied second memory cell address in the second memory cell list to the object.
13. The apparatus of claim 11, wherein the memory allocation instruction generation module is further configured to:
generating specification parameters of the class according to the label of the class;
generating a second memory block size parameter according to the number of second memory unit addresses in the second memory unit list;
and generating a second memory allocation instruction according to the label of each class, the specification parameter of the class, the size parameter of the second memory block and the second memory unit list.
14. The apparatus of claim 11,
each first memory unit address comprises a plurality of memory addresses, and the plurality of first memory unit addresses in the first memory unit list are continuous memory addresses;
each of the second memory cell addresses includes a plurality of memory addresses, and the plurality of second memory cell addresses in the second memory cell list are consecutive memory addresses.
15. A computing device comprising a memory, a processor, and computer instructions stored on the memory and executable on the processor, wherein the processor implements the steps of the method of any one of claims 1-7 when executing the instructions.
16. A computer-readable storage medium storing computer instructions, which when executed by a processor, perform the steps of the method of any one of claims 1 to 7.
CN201910308438.9A 2019-04-17 2019-04-17 Memory address allocation method and device, computing equipment and storage medium Active CN110059019B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910308438.9A CN110059019B (en) 2019-04-17 2019-04-17 Memory address allocation method and device, computing equipment and storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910308438.9A CN110059019B (en) 2019-04-17 2019-04-17 Memory address allocation method and device, computing equipment and storage medium

Publications (2)

Publication Number Publication Date
CN110059019A CN110059019A (en) 2019-07-26
CN110059019B true CN110059019B (en) 2021-12-10

Family

ID=67319327

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910308438.9A Active CN110059019B (en) 2019-04-17 2019-04-17 Memory address allocation method and device, computing equipment and storage medium

Country Status (1)

Country Link
CN (1) CN110059019B (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109508317A (en) * 2018-10-31 2019-03-22 武汉光谷联众大数据技术有限责任公司 A kind of Large Volume Data and service management system

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6088777A (en) * 1997-11-12 2000-07-11 Ericsson Messaging Systems, Inc. Memory system and method for dynamically allocating a memory divided into plural classes with different block sizes to store variable length messages
CN103324582A (en) * 2013-06-17 2013-09-25 华为技术有限公司 Memory migration method, memory migration device and equipment
CN107045436B (en) * 2016-02-05 2019-09-10 龙芯中科技术有限公司 Access processing method and device
CN107818118B (en) * 2016-09-14 2019-04-30 北京百度网讯科技有限公司 Date storage method and device
CN107728937B (en) * 2017-09-15 2020-09-04 上海交通大学 Key value pair persistent storage method and system using nonvolatile memory medium

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109508317A (en) * 2018-10-31 2019-03-22 武汉光谷联众大数据技术有限责任公司 A kind of Large Volume Data and service management system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
A secure and efficient authentication protocol for passive RFID tags;C. Kolias;《2009 6th International Symposium on Wireless Communication Systems》;20091013;36-40 *

Also Published As

Publication number Publication date
CN110059019A (en) 2019-07-26

Similar Documents

Publication Publication Date Title
CN109325195B (en) Rendering method and system for browser, computer device and computer storage medium
CN105426223B (en) Using loading method and device
US11366925B2 (en) Methods and apparatuses for chaining service data
CN105550345A (en) File operation method and apparatus
CN111143446A (en) Data structure conversion processing method and device of data object and electronic equipment
JP2019517700A (en) Data processing method and device
CN107205015A (en) The implementation method and device of open interface
CN111767047A (en) Micro-service component management method and device
CN109582458A (en) Resource information loading method, device, storage medium and processor
CN114089975A (en) Expansion method and device of computing software, nonvolatile storage medium and processor
CN109918118B (en) Service line registration method and related equipment
CN110059019B (en) Memory address allocation method and device, computing equipment and storage medium
CN114500549A (en) Method, apparatus, and medium to deploy k8s hosting cluster for users in public cloud
CN107451203A (en) Data bank access method and device
CN1645856B (en) Deterministic rule-based dispatch of objects to code
CN110968333A (en) Configuration information replacement method and device, machine-readable storage medium and processor
CN114584482B (en) Method, device and network card for storing detection data based on memory
CN102184105A (en) Data processing method based on modularity and data center system
CN105577707A (en) Remote call method and remote call device
US11640414B2 (en) Generating workflow, report, interface, conversion, enhancement, and forms (WRICEF) objects for enterprise software
CN110266596B (en) Message processing method, device, equipment and computer readable storage medium
CN109918147B (en) Expansion method and device for drive under OpenStack and electronic equipment
CN113329096A (en) Message transmission method and device, electronic equipment and storage medium
CN116107764B (en) Data processing method and system
CN111949296A (en) Data updating method and device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: 519000 Room 102, 202, 302 and 402, No. 325, Qiandao Ring Road, Tangjiawan Town, high tech Zone, Zhuhai City, Guangdong Province, Room 102 and 202, No. 327 and Room 302, No. 329

Applicant after: ZHUHAI KINGSOFT ONLINE GAME TECHNOLOGY Co.,Ltd.

Applicant after: Guangzhou Xishanju Network Technology Co.,Ltd.

Address before: 519000 Room 102, 202, 302 and 402, No. 325, Qiandao Ring Road, Tangjiawan Town, high tech Zone, Zhuhai City, Guangdong Province, Room 102 and 202, No. 327 and Room 302, No. 329

Applicant before: ZHUHAI KINGSOFT ONLINE GAME TECHNOLOGY Co.,Ltd.

Applicant before: GUANGZHOU SEASUN ENTERTAINMENT NETWORK TECHNOLOGY Co.,Ltd.

CB02 Change of applicant information
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: 519000 Room 102, 202, 302 and 402, No. 325, Qiandao Ring Road, Tangjiawan Town, high tech Zone, Zhuhai City, Guangdong Province, Room 102 and 202, No. 327 and Room 302, No. 329

Patentee after: Zhuhai Jinshan Digital Network Technology Co.,Ltd.

Patentee after: Guangzhou Xishanju Network Technology Co.,Ltd.

Address before: 519000 Room 102, 202, 302 and 402, No. 325, Qiandao Ring Road, Tangjiawan Town, high tech Zone, Zhuhai City, Guangdong Province, Room 102 and 202, No. 327 and Room 302, No. 329

Patentee before: ZHUHAI KINGSOFT ONLINE GAME TECHNOLOGY Co.,Ltd.

Patentee before: Guangzhou Xishanju Network Technology Co.,Ltd.

CP01 Change in the name or title of a patent holder