CN110054145B - MEMS device and method of manufacturing the same - Google Patents
MEMS device and method of manufacturing the same Download PDFInfo
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- CN110054145B CN110054145B CN201910325569.8A CN201910325569A CN110054145B CN 110054145 B CN110054145 B CN 110054145B CN 201910325569 A CN201910325569 A CN 201910325569A CN 110054145 B CN110054145 B CN 110054145B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/02—Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00047—Cavities
Abstract
The application discloses a MEMS device and a manufacturing method thereof, wherein the manufacturing method comprises the following steps: forming at least one first cavity extending into the semiconductor substrate from a designated surface of the semiconductor substrate; forming a first sacrificial layer, wherein the first cavity is filled with the first sacrificial layer; forming a first structural layer with first channel holes, wherein the first structural layer covers the first sacrificial layer, and each first cavity corresponds to the position of the corresponding first channel hole; and removing the first sacrificial layer in the first cavity through the first via hole. The manufacturing method reduces the manufacturing cost by avoiding the use of a DRIE process, an ICP process and a wafer bonding process to form a cavity and a structural layer.
Description
Technical Field
The present disclosure relates to the field of semiconductor device manufacturing, and more particularly, to a MEMS device and a method for manufacturing the same.
Background
At present, Micro-Electro-Mechanical systems (MEMS) technology is rapidly developing, and in general MEMS products, it is often necessary to fabricate a cavity structure and perform a film coating on the cavity to form a structure layer.
In the prior art, a first common process of coating a film on a cavity is shown in fig. 1, first, a structural layer 12 is formed on the front surface of a semiconductor substrate 11, and then, a cavity (a dashed frame) is formed by etching from the back surface of the semiconductor substrate 11 to the front surface of the semiconductor substrate 11. However, this method requires the semiconductor substrate 11 to be completely etched, and thus, a relatively expensive process such as an Inductively Coupled Plasma (ICP) and/or a Deep Reactive Ion Etching (DRIE) process is used. In addition, since the inside of the cavity is communicated with the external environment, if the air pressure inside the cavity needs to be controlled, a noble gas with high use cost is needed in the packaging stage, and even the air pressure inside the cavity needs to be controlled by controlling the pressure of the packaging environment, so that the implementation is difficult, and the manufacturing cost is further increased.
As shown in fig. 2, a second common process for coating a film on a cavity includes first forming a cavity 23 extending from a surface of a first semiconductor substrate 21 into the first semiconductor substrate 21, then bonding a second semiconductor substrate 22 to the first semiconductor substrate 21 under a vacuum environment by using a wafer bonding process, and finally removing a portion of the second semiconductor substrate 22 (a dashed frame) by using a thinning process, and forming a structural layer 24 on the remaining second semiconductor substrate 22. However, this method requires a high thickness tolerance for the thinning process, for example, the thickness of the second semiconductor substrate 22 is 200 μm, and the thinning process is required to be as thin as 2 μm, and if the thinning tolerance is 0.2um, i.e., 0.1%, the relative tolerance to the thickness of 2 μm of the structural layer 24 actually remaining is 10%, and the fluctuation in rigidity thereof is equivalent to the third power of the thickness, i.e., about as high as +/-30%, thereby reducing the reliability of the device. In addition, the use of wafer bonding processes further increases manufacturing costs.
Disclosure of Invention
Accordingly, the present invention provides a MEMS device and a method for fabricating the same, which reduces a fabrication cost by avoiding formation of a cavity and a structure layer using a DRIE process, an ICP process, and a wafer bonding process.
According to an aspect of an embodiment of the present invention, there is provided a method of manufacturing a MEMS device, including: forming at least one first cavity extending into a semiconductor substrate from a designated surface of the semiconductor substrate; forming a first sacrificial layer, wherein the first cavity is filled with the first sacrificial layer; forming a first structural layer having first via holes, the first structural layer covering the first sacrificial layer, each of the first cavities corresponding to a position of a corresponding one of the first via holes; and removing the first sacrificial layer in the first cavity through the first via hole.
Preferably, the step of forming the at least one first cavity comprises: and removing part of the semiconductor substrate by adopting an anisotropic wet etching process or an isotropic wet etching process or a non-deep silicon dry etching process, wherein the etching is stopped when reaching a preset depth in the semiconductor substrate from the specified surface.
Preferably, the predetermined depth is not more than half of the thickness of the semiconductor substrate.
Preferably, the predetermined depth is not less than 2 μm.
Preferably, the step of forming the first sacrificial layer includes: and covering the designated surface and filling the first cavity to form the first sacrificial layer, wherein the thickness of the first sacrificial layer is not less than the preset depth.
Preferably, the thickness of the first sacrificial layer is greater than the predetermined depth.
Preferably, when the at least one first cavity is formed by a wet etching process, the process for forming the first sacrificial layer includes a plasma enhanced chemical vapor deposition process or a process using TEOS as a raw material.
Preferably, before forming the first structural layer, the manufacturing method further includes: and removing the first sacrificial layer at least partially covering the designated surface by adopting a thinning process, wherein the thinning is stopped when the first sacrificial layer reaches the vicinity of the designated surface, and the error of the thinning is positively correlated with the thickness of the first sacrificial layer.
Preferably, the step of removing the first sacrificial layer in the first cavity comprises: and removing the first sacrificial layer in the first cavity through the first channel hole by adopting a wet etching process so as to re-expose the first cavity.
Preferably, the manufacturing method further includes: and closing at least part of the first channel hole to form an external expansion layer so as to isolate at least part of the interior of the first cavity from the external air pressure environment.
Preferably, the step of forming the flaring layer comprises: and when the atmospheric pressure environment inside the first cavity is set to be a normal pressure environment or a high pressure environment, growing the external expansion layer at the first channel hole by adopting a thermal oxidation process, wherein the material of the external expansion layer comprises an oxide.
Preferably, the step of forming the flaring layer further comprises: depositing an epitaxial material at the first via hole by a chemical vapor deposition process; and forming the external expansion layer by extending the epitaxial material by adopting a thermal oxidation process, wherein the epitaxial material comprises polycrystalline silicon.
Preferably, the step of forming the flaring layer comprises: when the atmospheric pressure environment inside the first cavity is set to be the normal pressure environment or the low pressure environment, the external expansion layer is deposited on the inner surface of the first cavity, the upper surface and the lower surface of the first structural layer and the side wall of the first channel hole by respectively adopting the normal pressure chemical vapor deposition process and the low pressure chemical process, wherein the material of the external expansion layer comprises silicon nitride.
Preferably, before depositing the diffusion layer, the manufacturing method further comprises: and growing an oxide layer at the first channel hole by adopting a thermal oxidation process.
Preferably, after the forming of the first passage hole, the manufacturing method further includes: and forming at least one second sacrificial layer and a second structural layer with a second channel hole on the first structural layer, wherein the first sacrificial layer and the second sacrificial layer are alternately stacked and are communicated through the first channel hole or the first channel hole and the second channel hole, and the first sacrificial layer and the second sacrificial layer are made of the same material.
Preferably, the step of removing the first sacrificial layer in the first cavity comprises: removing the first sacrificial layer in the first cavity through the first and second via holes; and removing at least a portion of the second sacrificial layer through the second via hole to form at least one second cavity.
Preferably, the manufacturing method further includes: and closing at least part of the second channel hole to form the external expansion layer.
Preferably, the manufacturing method further includes: and removing part of the external expansion layer to enable part of the first cavity to be communicated with the second cavity and/or removing part of the external expansion layer to enable part of the second cavity to be communicated with the outside.
Preferably, the material of the first sacrificial layer comprises silicon dioxide or phosphosilicate glass.
Preferably, the material of the first structural layer comprises polysilicon.
According to another aspect of embodiments of the present invention, there is provided a MEMS device including: a semiconductor substrate; at least one first cavity extending into a semiconductor substrate from a designated surface of the semiconductor substrate; a first structural layer having first via holes, the first structural layer covering the first cavities, each of the first cavities corresponding to a position of a corresponding one of the first via holes; and the external expanding layer is used for closing at least part of the first channel hole so as to isolate the interior of at least part of the first cavity from the external air pressure environment.
Preferably, the depth of the first cavity is no more than half the thickness of the semiconductor substrate.
Preferably, the depth of the first cavity is not less than 2 μm.
Preferably, the method further comprises the following steps: a first sacrificial layer between the designated surface and the first structural layer for supporting the first structural layer.
Preferably, the method further comprises the following steps: at least one second sacrificial layer; at least one second cavity in the second sacrificial layer; and at least one second structural layer having a second via hole, the at least one second sacrificial layer and the at least one second structural layer being alternately stacked on the first structural layer, wherein the second sacrificial layer is used to support the second structural layer.
Preferably, the outer expanding layer closes at least part of the second passage hole.
Preferably, a part of the first cavity and the second cavity communicate with each other through the first passage hole, and a part of the second cavity communicates with the outside through the second passage hole.
Preferably, the material of the first sacrificial layer comprises silicon dioxide or phosphosilicate glass.
Preferably, the material of the first structural layer comprises polysilicon.
According to the MEMS device and the manufacturing method thereof, the first cavity is filled with the first sacrificial layer, the first structural layer with the first channel hole is formed by covering the first sacrificial layer, the first sacrificial layer in the first cavity is removed through the first channel hole, the first cavity is exposed again, the purposes of manufacturing the cavity structure and forming the structural layer by laminating above the cavity are achieved, compared with the prior art, the manufacturing method of the embodiment of the invention avoids using the processes with higher cost, such as DRIE, ICP, wafer bonding and the like, and therefore the manufacturing cost of the MEMS device is saved.
Furthermore, the anisotropic wet etching process is adopted to remove part of the semiconductor substrate to form the first cavity, compared with the DRIE and ICP processes in the prior art, the cost is saved, the etching consistency can be improved by adopting the wet process, and the inner wall of the formed first cavity is smoother.
Furthermore, by forming the external expansion layer to seal part of the first channel hole and part of the second channel, the internal and external air pressure environments of part of the first cavity and the internal and external air pressure environments of part of the second cavity are isolated, and the high-cost process for controlling the air pressure in the cavity in the packaging stage is avoided, so that the manufacturing cost of the MEMS device is further saved.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.
Fig. 1 and 2 are schematic diagrams illustrating a process of laminating a film on a cavity in the prior art.
Fig. 3a shows a schematic structural diagram of a MEMS device according to a first embodiment of the invention.
Fig. 3b shows a schematic view of an alternative embodiment of the first embodiment of the invention.
Fig. 4 to 10b show schematic cross-sectional views of a part of stages in a method of manufacturing a MEMS device according to a first embodiment of the invention.
Fig. 11 shows a schematic structural diagram of a MEMS device according to a second embodiment of the present invention.
Fig. 12 to 23 are schematic cross-sectional views showing a part of stages in a method for manufacturing a MEMS device according to a second embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, a semiconductor device obtained after several steps can be described in one drawing.
It will be understood that when a layer or region is referred to as being "on" or "over" another layer or region in describing the structure of the device, it can be directly on the other layer or region or intervening layers or regions may also be present. And, if the device is turned over, that layer, region, or regions would be "under" or "beneath" another layer, region, or regions.
If for the purpose of describing the situation directly above another layer, another region, the expressions "directly above … …" or "above and adjacent to … …" will be used herein.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of the devices are described in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
The present invention may be embodied in various forms, some examples of which are described below.
Fig. 3a shows a schematic structural diagram of a MEMS device according to a first embodiment of the invention.
As shown in fig. 3a, the MEMS device of the first embodiment of the present invention includes: the semiconductor device includes a semiconductor substrate 101, one or more first cavities 102, a first sacrificial layer 110, a first structural layer 120, and an extension layer 140, wherein the first structural layer 120 has a plurality of first via holes 103.
The first cavity 102 extends from a designated surface of the semiconductor substrate 101, such as the upper surface shown in fig. 3, into the semiconductor substrate 101, wherein the depth of the first cavity 102 is no greater than half of the thickness of the semiconductor substrate 101, and in some preferred embodiments, the depth of the first cavity 102 is no less than 2 μm.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings for the depth of the first cavity 102 as needed.
The first structural layer 120 covers the designated surface of the semiconductor substrate 101 and the first cavity 102, the first structural layer 120 has a plurality of first via holes 103, each first cavity 102 corresponds to a position of a corresponding first via hole 103, wherein a material of the first structural layer 120 includes polysilicon.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements on the material of the first structural layer 120 as needed.
The first sacrificial layer 110 is located between the designated surface of the semiconductor substrate 101 and the first structural layer 120, and is used for supporting the first structural layer 120 when the first sacrificial layer 110 inside the first cavity 102 is removed, wherein the material of the first sacrificial layer 110 comprises silicon dioxide or phosphosilicate glass.
However, the embodiment of the present invention is not limited thereto, and those skilled in the art may perform other arrangements on the material of the first sacrificial layer 110 as needed.
The flaring layer 140 is positioned to adhere to a sidewall of the first channel hole 103 to close at least a portion of the first channel hole 103 to isolate at least a portion of the interior of the first cavity 102 from the external atmospheric pressure environment. In the present embodiment, the material of the flaring layer 140 includes an oxide, and is formed by a thermal oxidation process, and when the inner surface of the first cavity 102 is not subjected to any treatment, the flaring layer 140 is also formed on the inner surface of the first cavity 102.
However, embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements for the material of the flaring layer 140 as desired.
In some other embodiments, the flaring layer 140 is formed by a deposition process, not only closing off a portion of the first passage hole 103, but also adhering to both the upper and lower surfaces of the first structural layer 120 and the inner surface of the first cavity 102, as shown in fig. 3 b. Wherein, the material of the flaring layer 140 includes nitride and/or oxide, preferably silicon nitride.
Fig. 4 to 10b are schematic cross-sectional views showing a part of stages in a method for manufacturing a MEMS device according to a first embodiment of the present invention, which will be described in detail with reference to fig. 4 to 10 b.
As shown in fig. 4, at least one first cavity 102 is formed in a semiconductor substrate 101.
In this step, for example, a photoresist is first coated on the semiconductor substrate 101, and the photoresist is patterned using a photolithography process to form a resist mask. Then, a part of the semiconductor substrate 101 is removed through the resist mask by using an anisotropic wet etching process, and the first cavity 102 is formed to extend from the prescribed surface of the semiconductor substrate 101 into the semiconductor substrate 101, and during the etching, the etching is stopped by controlling the etching time from the prescribed surface when reaching a predetermined depth h1 in the semiconductor substrate 101. Finally, the resist mask is removed by solvent dissolution or ashing.
In the present embodiment, the prescribed surface is the upper surface of the semiconductor substrate 101 as shown in fig. 4. Wherein the predetermined depth h1 is not more than half the thickness of the semiconductor substrate 101, and in some preferred embodiments, the predetermined depth h1 is not less than 2 μm.
In this step, the first cavity 102 is formed by using an anisotropic wet etching process, which not only saves cost, but also makes the etching consistency higher and the inner wall of the formed first cavity smoother by using the wet process.
In some other embodiments, if a first cavity with a complex pattern needs to be formed, the first cavity 102 may be formed by using an isotropic wet etching process or a non-deep silicon dry etching process.
Further, a first sacrificial layer 110 is formed covering the prescribed surface of the semiconductor substrate 101 and filling the first cavity 102, as shown in fig. 5.
In this step, the first sacrificial layer 110 is formed, for example, by using a deposition process while covering a designated surface of the semiconductor substrate 101 and filling the first cavity 102, wherein the material of the first sacrificial layer 110 includes silicon dioxide or phosphosilicate glass, and the thickness h2 of the first sacrificial layer 110 is not less than the predetermined depth h1, so that the first cavity 102 can be filled with the first sacrificial layer 110. In some preferred embodiments, the thickness h2 of the first sacrificial layer 110 is greater than the predetermined depth h 1.
When the first cavity 102 is formed by a wet etching process, the process for forming the first sacrificial layer 110 includes a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or a process using TEOS as a raw material (including a TEOS hydrolysis process, a TEOS source growth process, etc.), thereby achieving the purpose of saving cost.
However, the embodiment of the present invention is not limited thereto, and those skilled in the art may perform other arrangements on the material of the first sacrificial layer 110 as needed.
Further, a thinning process is used to remove the first sacrificial layer 110 at least partially covering the designated surface, as shown in fig. 6 a.
In this step, thinning is stopped when the vicinity of the prescribed surface of the semiconductor substrate 101 is reached until the prescribed surface is exposed. In this case, there is an error in thinning, so that the first sacrificial layer 110 above the designated surface cannot be completely removed, as shown in fig. 6b, the error in thinning is positively correlated to the thickness of the first sacrificial layer 110, and therefore the problem of error amplification can be avoided.
Further, a first structural layer 120 is formed overlying the first sacrificial layer 110, as shown in fig. 7 a.
In this step, the first structural layer 120 is formed, for example, using a deposition process, wherein the material of the first structural layer 120 comprises polysilicon.
In some preferred embodiments, a first protection layer 131 may be further formed between the first structural layer 120 and the first sacrificial layer 110, and a second protection layer 132 is further formed on the surface of the first structural layer 120, as shown in fig. 7b, wherein the materials of the first protection layer 131 and the second protection layer 132 include dense materials, and in particular, the materials of the first protection layer 131 and the second protection layer 132 include silicon nitride.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements on the materials of the first structure layer 120, the first protection layer 131, and the second protection layer 132 as needed.
Further, removing a portion of the first structural layer 120 forms at least one first via hole 103, as shown in fig. 8.
In this step, for example, a photoresist is first coated on the first structure layer 120, and the photoresist is patterned using a photolithography process to form a resist mask. And then, for example, forming the first channel hole 103 by using an etching process, wherein the position of the first channel hole 103 corresponds to the first cavity, so that a part of the first sacrificial layer 110 in the first cavity is exposed through the first channel hole 103, and in the etching process, the etching is stopped when the first sacrificial layer 110 is exposed by controlling the etching time. Finally, the resist mask is removed by solvent dissolution or ashing.
Further, the first sacrificial layer 110 in the first cavity 102 is removed through the first via hole 103, as shown in fig. 9.
In this step, the first sacrificial layer 110 in the first cavity 102 is removed through the first via hole 103, for example, using a wet etching process, to re-expose the first cavity 102. Among them, the sacrificial layer 110 located at a designated surface of the semiconductor substrate 101 may be used to support the first structural layer 120. In this step, the first sacrificial layer 110 is removed by a wet etching process, so as to achieve the purpose of saving cost.
Further, at least a portion of the first channel hole 103 is closed to form an external expanding layer 140 to isolate the interior of at least a portion of the first cavity 102 from the external atmospheric pressure environment, as shown in fig. 10 a.
In this step, when the atmospheric pressure environment inside the first cavity 102 needs to be set to an atmospheric pressure environment or a high pressure environment, the flaring layer 140 is grown at the first channel hole 103, for example, by using a thermal oxidation process, wherein the material of the flaring layer 140 includes an oxide. If the inner surface of the first cavity 102 is not treated, the flaring layer 140 is also formed on the inner surface of the first cavity 102.
In some preferred embodiments, a silicon nitride protection layer is formed on each of the upper and lower surfaces of the first structure layer 120 in advance to cover the first structure layer 120 made of polysilicon material, so as to prevent the upper and lower surfaces of the first structure layer 120 from being oxidized, thereby ensuring that the thickness and strength of the first structure layer 120 are not affected by the fluctuation of the oxidation process.
In other preferred embodiments, a thermal oxidation process is used to grow some oxide layer (e.g., silicon dioxide) at the first via hole 103, then a chemical vapor deposition process is used to deposit epitaxial material at the first via hole 103, and a thermal oxidation process is used to extend the epitaxial material, and then some oxide layer is grown to finally form the epi-extension layer 140 that closes the first via hole 103, wherein the epitaxial material includes polysilicon. By alternately using the above two processes at least once, the problem that the thermal oxidation process cannot be completely relied on to close the first via hole 103 when the opening of the first via hole 103 is large due to consumption of silicon material by the thermal oxidation process is prevented.
In some other embodiments, when the atmospheric pressure environment inside the first cavity 102 needs to be set to be the atmospheric pressure environment or the low pressure environment, the out-diffusion layer 140 is deposited on the inner surface of the first cavity 102, the upper and lower surfaces of the first structural layer 120, and the sidewall of the first via hole 103 by using the atmospheric pressure chemical vapor deposition process and the low pressure chemical process, respectively, as shown in fig. 10b, wherein the material of the out-diffusion layer includes silicon oxide and/or silicon nitride, preferably silicon nitride. More preferably, an oxide layer is grown at the first via hole 103 using a thermal oxidation process before depositing the flaring layer 140, and it is also possible to prevent a problem that the first via hole 103 cannot be completely closed depending on the deposition process when the first via hole 103 is opened large.
Fig. 11 shows a schematic structural diagram of a MEMS device according to a second embodiment of the present invention.
As shown in fig. 11, the MEMS device of the second embodiment of the present invention includes: the semiconductor device comprises a semiconductor substrate 201, a plurality of first cavities 202, a first sacrificial layer 210, a first structural layer 220, at least one second sacrificial layer 230, at least one second structural layer 240 and an external expanding layer, wherein the first structural layer 220 is provided with a plurality of first channel holes 203, the second structural layer 240 is provided with a plurality of second channel holes 204, and the external expanding layer comprises a first external expanding layer 250 and a second external expanding layer 260. For clarity, only one first cavity 202 and one second cavity 205 are shown on the left side and one first cavity 202 and one second cavity 205 are shown on the right side in fig. 11, but the embodiment of the present invention is not limited thereto, and those skilled in the art may make other arrangements for the number of first cavities 202 and second cavities 205 as needed.
The first cavity 202 extends from a designated surface of the semiconductor substrate 201, such as the upper surface shown in fig. 11, into the semiconductor substrate 201, wherein the depth of the first cavity 202 is not greater than half of the thickness of the semiconductor substrate 201, and in some preferred embodiments, the depth of the first cavity 202 is not less than 2 μm.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other settings for the depth of the first cavity 202 as needed.
The first structural layer 220 covers the designated surface of the semiconductor substrate 201 and the first cavity 202, the first structural layer 220 has a plurality of first via holes 203, each first cavity 202 corresponds to a position of a corresponding first via hole 203, wherein a material of the first structural layer 220 includes polysilicon.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements on the material of the first structural layer 220 as needed.
The first sacrificial layer 210 is located between the designated surface of the semiconductor substrate 201 and the first structural layer 220, and is used for supporting the first structural layer 220 when the first sacrificial layer 210 inside the first cavity 202 is removed, wherein the material of the first sacrificial layer 210 comprises silicon dioxide or phosphosilicate glass.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements on the material of the first sacrificial layer 210 as needed.
The second cavities 205 are located in the second sacrificial layer 230, the second structural layer 240 covers the surface of the second sacrificial layer 230 and the second cavities 202, each second cavity 205 corresponds to a corresponding second via hole 204, wherein the second sacrificial layer 230 and the second structural layer 240 are alternately stacked on the first structural layer 220, and the second sacrificial layer 230 is used for supporting the second structural layer 240. For clarity, only one second sacrificial layer 230 and one second structural layer 240 are shown in fig. 11, however, the embodiment of the present invention is not limited thereto, and a person skilled in the art may make other arrangements as needed for the number of second sacrificial layers 230 and second structural layers 240 alternately stacked on the first structural layer 220.
In the present embodiment, the material of the second structure layer 220 includes polysilicon, and the material of the second sacrificial layer 230 is the same as that of the first sacrificial layer 220.
The flaring layer is attached to a sidewall of a portion of the first passage hole 203 to close at least a portion of the first passage hole 203 to isolate at least a portion of the interior of the first cavity 202 from the outside atmospheric pressure environment or the atmospheric pressure environment of the first cavity 202 from the second cavity 205, as shown in the left portion of fig. 11. The flaring layer is attached to a portion of the sidewall of the second via hole 204 to close at least a portion of the second via hole 204 to isolate at least a portion of the interior of the second cavity 202 from the external atmospheric pressure environment, such as the right portion of fig. 11. Wherein a part of the first cavity 202 and the second cavity 205 communicate with each other through the first passage hole 203, as shown in the right portion of fig. 11, and a part of the second cavity 205 communicates with the outside through the second passage hole 204, as shown in the left portion of fig. 11. The material and formation process of the flaring layer are substantially the same as those of the first embodiment, and are not described herein again.
Fig. 12 to 23 are schematic cross-sectional views showing a part of stages in a method for manufacturing a MEMS device according to a second embodiment of the present invention, which will be described in detail with reference to fig. 12 to 23.
As shown in fig. 12, at least one first cavity 202 is formed in a semiconductor substrate 201.
In this step, for example, a photoresist is first coated on the semiconductor substrate 201, and the photoresist is patterned using a photolithography process to form a resist mask. Then, a part of the semiconductor substrate 201 is removed through the resist mask by using an anisotropic wet etching process, and a first cavity 202 is formed to extend from the specified surface of the semiconductor substrate 201 into the semiconductor substrate 201, and in the etching process, by controlling the etching time, the etching is stopped from the specified surface when reaching a predetermined depth h3 in the semiconductor substrate 201. Finally, the resist mask is removed by solvent dissolution or ashing.
In the present embodiment, the prescribed surface is the upper surface of the semiconductor substrate 201 as shown in fig. 12. Wherein the predetermined depth h3 is not more than half the thickness of the semiconductor substrate 201, and in some preferred embodiments, the predetermined depth h3 is not less than 2 μm.
In this step, the first cavity 202 is formed by using an anisotropic wet etching process, which not only saves cost, but also makes the etching consistency higher and the inner wall of the formed first cavity 202 smoother by using a wet process.
In some other embodiments, if a first cavity with a complex pattern is to be formed, the first cavity 202 may be formed by using an isotropic wet etching process or a non-deep silicon dry etching process.
Further, a first sacrificial layer 210 is formed covering the prescribed surface of the semiconductor substrate 201 and filling the first cavity 202, as shown in fig. 13.
In this step, the first sacrificial layer 210 is formed, for example, by using a deposition process while covering a designated surface of the semiconductor substrate 201 and filling the first cavity 202, wherein the material of the first sacrificial layer 210 includes silicon dioxide or phosphosilicate glass, and the thickness h4 of the first sacrificial layer 210 is not less than the predetermined depth h3, so that the first cavity 202 may be filled with the first sacrificial layer 210. In some preferred embodiments, the thickness h4 of the first sacrificial layer 210 is greater than the predetermined depth h 3.
When the at least one first cavity 202 is formed by a wet etching process, a process for forming the first sacrificial layer 210 includes a Plasma Enhanced Chemical Vapor Deposition (PECVD) process or a process using TEOS as a raw material (including a TEOS hydrolysis process, a TEOS source growth process, etc.), so as to achieve the purpose of saving cost.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may make other arrangements on the material of the first sacrificial layer 210 as needed.
Further, a thinning process is used to remove the first sacrificial layer 110 at least partially covering the designated surface, as shown in fig. 14.
In this step, thinning is stopped when the vicinity of the prescribed surface of the semiconductor substrate 201 is reached until the prescribed surface is exposed. In the above, there is an error in thinning, which results in that the first sacrificial layer 210 above the designated surface cannot be completely removed, and the error in thinning is positively correlated to the thickness of the first sacrificial layer 210, so that the error amplification problem can be avoided.
Further, a layer covers the first sacrificial layer 210 to form a first structural layer 220, as shown in fig. 15.
In this step, the first structural layer 220 is formed, for example, using a deposition process, wherein the material of the first structural layer 220 comprises polysilicon.
In some preferred embodiments, a first protection layer may be further formed between the first structural layer 220 and the first sacrificial layer 210, and a second protection layer may be further formed on the surface of the first structural layer 220, where the materials of the first protection layer and the second protection layer include dense materials, and in particular, the materials of the first protection layer and the second protection layer include silicon nitride.
However, the embodiments of the present invention are not limited thereto, and those skilled in the art may perform other arrangements on the materials of the first structure layer 220, the first protection layer, and the second protection layer as needed.
Further, removing a portion of the first structural layer 220 forms at least one first via hole 203, as shown in fig. 16.
In this step, for example, a photoresist is first coated on the first structure layer 220, and the photoresist is patterned using a photolithography process to form a resist mask. Then, for example, an etching process is used to form the first via hole 203 through the resist mask, the position of the first via hole 203 corresponds to the first cavity, so that the first sacrificial layer 210 partially located in the first cavity is exposed through the first via hole 203, and during the etching process, the etching is stopped by controlling the etching time to expose the first sacrificial layer 210. Finally, the resist mask is removed by solvent dissolution or ashing.
Further, at least one second sacrificial layer 230 and at least one second structural layer 240 are alternately stacked over the first structural layer 210, as shown in fig. 17.
In this step, the first sacrificial layer 210 and the first structural layer 220 are covered, for example, by a deposition process, wherein the first sacrificial layer 210 and the second sacrificial layer 220 are in contact via the first via hole. A second structural layer 240 is then formed overlying the second sacrificial layer 230 using a deposition process. Then, for example, a photoresist is coated on the second structure layer 240, and the photoresist is patterned using a photolithography process to form a resist mask. The second via hole 204 is then formed through the resist mask, for example, using an etching process in which etching is stopped at the time of exposing the second sacrificial layer 230 by controlling the etching time. Finally, the resist mask is removed by solvent dissolution or ashing.
In this step, for clarity, only one second sacrificial layer 230 and one second structural layer 240 are shown in fig. 17, however, the embodiment of the present invention is not limited thereto, and a person skilled in the art may perform other arrangements on the number of the second sacrificial layers 230 and the number of the second structural layers 240 alternately stacked on the first structural layer 220 as required, for example, alternately stacking a plurality of second sacrificial layers 230 and a plurality of second structural layers 240, each second structural layer 240 having a second channel hole 204, and the upper second sacrificial layer 230 being capable of communicating with the first sacrificial layer 210 through the second channel holes 204 and the first channel holes.
In the present embodiment, the material of the second structure layer 220 includes polysilicon, and the material of the second sacrificial layer 230 is the same as that of the first sacrificial layer 220.
Further, the first sacrificial layer 110 in the first cavity 202 is removed through the second via hole 204 and the first via hole 203 in sequence to re-expose the first cavity 202, and a portion of the second sacrificial layer 230 is removed through the second via hole 204 to form at least one second cavity 205, as shown in fig. 18.
In this step, the first sacrificial layer 210 and the second sacrificial layer 230 are removed, for example, using a wet etching process. The first sacrificial layer 210 on the designated surface of the semiconductor substrate 201 may be used to support the first structural layer 220, and the second sacrificial layer 230 may be used to support the second structural layer 240. In this step, a wet etching process is employed to achieve the purpose of cost saving.
Further, the layer expands outward with partial second via hole formation in the first via hole of seal part, because made a plurality of cavitys (including first cavity and second cavity) in this embodiment, some cavity insides need set up to the ordinary pressure, some cavity insides need set up to high pressure or low pressure, can be through rationally setting up the trompil size, let first via hole and second via hole seal under different high pressure, low pressure or ordinary pressure condition, or seal the mode trompil of accomplishing back rethread to expanding the layer sculpture outward and make the cavity become the ordinary pressure. The multi-layer structure layer (including the first structure layer and the second structure layer) can be manufactured by reasonably setting the sizes of the first channel hole and the second via hole, the sequence and the parameters of the sealing process, and the first channel hole and/or the second via hole of one layer are/is appointed above some cavities in the sealing process under certain pressure. If multi-step sealing process is involved, the sealing process should be continuously performed to avoid the influence of other intermediate processes on the final sealing effect.
In some embodiments, the first flaring layer 250 is formed by closing the first channel holes and a portion of the second channel holes, as shown in fig. 19.
In this step, a chemical vapor deposition process or a thermal oxidation process may be used to deposit the first outer diffusion layer 250 on the inner surface of the first cavity 202, the upper and lower surfaces of the first structure layer 220, and the sidewall of the first via hole according to the setting of the atmospheric pressure environment inside the first cavity 202, and the process of forming the first outer diffusion layer 250 is similar to that of the first embodiment, and is not repeated herein.
Further, removing a portion of the first flaring layer 250 re-forms a portion of the first channel 203 and the second channel 204, as shown in FIG. 20.
In this step, a part of the second cavity 205 is isolated from the air pressure environment of the first cavity 202, as shown in the left part of fig. 20, and a part of the second cavity 205 communicates with the first cavity 202 via the first passage hole 203, as shown in the right part of fig. 20.
Further, the second external expanding layer 260 is formed by closing the first via hole and a part of the second via hole, as shown in fig. 21.
In this step, a chemical vapor deposition process or a thermal oxidation process may be performed according to the pressure environment inside the first cavity 202 and the second cavity 205 to deposit the second outer diffusion layer 260 on the inner surface of the first cavity 202, the inner surface of the second cavity 205, the surface of the first outer diffusion layer 250, and the sidewalls of the first channel hole and the second channel hole, which are not sealed, and the process for forming the second outer diffusion layer is similar to the first embodiment, and is not described herein again.
Further, removing portions of the first and second flaring layers 250 and 260 re-forms portions of the first and second channels 203 and 204, as shown in FIG. 22.
In this step, a part of the second cavity 205 is isolated from the air pressure environment of the first cavity 202, as shown in the left part of fig. 22, and a part of the second cavity 205 is communicated with the first cavity 202 through the first passage hole 203, as shown in the right part of fig. 22.
Further, a part of the second passage hole 204 is closed, so that the inside of the second cavity 205 is isolated from the external atmospheric pressure environment, as shown in fig. 23.
According to the MEMS device and the manufacturing method thereof, the first cavity is filled with the first sacrificial layer, the first structural layer with the first channel hole is formed by covering the first sacrificial layer, the first sacrificial layer in the first cavity is removed through the first channel hole, the first cavity is exposed again, the purposes of manufacturing the cavity structure and forming the structural layer by laminating above the cavity are achieved, compared with the prior art, the manufacturing method of the embodiment of the invention avoids using the processes with higher cost, such as DRIE, ICP, wafer bonding and the like, and therefore the manufacturing cost of the MEMS device is saved.
Furthermore, the anisotropic wet etching process is adopted to remove part of the semiconductor substrate to form the first cavity, compared with the DRIE and ICP processes in the prior art, the cost is saved, the etching consistency can be improved by adopting the wet process, and the inner wall of the formed first cavity is smoother.
Furthermore, by forming the external expansion layer to seal part of the first channel hole and part of the second channel, the internal and external air pressure environments of part of the first cavity and the internal and external air pressure environments of part of the second cavity are isolated, and the high-cost process for controlling the air pressure in the cavity in the packaging stage is avoided, so that the manufacturing cost of the MEMS device is further saved.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, the person skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present invention have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the invention, and these alternatives and modifications are intended to fall within the scope of the invention.
Claims (27)
1. A method of fabricating a MEMS device, comprising:
forming at least one first cavity extending into a semiconductor substrate from a designated surface of the semiconductor substrate;
forming a first sacrificial layer covering the designated surface and filling in the first cavity;
forming a first structural layer having first via holes, the first structural layer covering the first sacrificial layer, each of the first cavities corresponding to a location of a corresponding one of the first via holes;
removing the first sacrificial layer in the first cavity through the first via hole and leaving the sacrificial layer on the prescribed surface to support the first structural layer; and
forming an flaring layer that closes at least a portion of the first passage aperture and extends from a sidewall of the first cavity toward the first structural layer to support the first structural layer.
2. The method of manufacturing of claim 1, wherein the step of forming the at least one first cavity comprises:
removing part of the semiconductor substrate by adopting an anisotropic wet etching process or an isotropic wet etching process or a non-deep silicon dry etching process,
wherein the etching stops when a predetermined depth in the semiconductor substrate is reached from the prescribed surface.
3. The manufacturing method according to claim 2, wherein the predetermined depth is not more than half of a thickness of the semiconductor substrate.
4. The manufacturing method according to claim 2, wherein the predetermined depth is not less than 2 μm.
5. The manufacturing method according to claim 2, wherein the step of forming the first sacrificial layer includes:
forming the first sacrificial layer by covering the designated surface and filling the first cavity,
wherein a thickness of the first sacrificial layer is not less than the predetermined depth.
6. The manufacturing method according to claim 5, wherein a thickness of the first sacrificial layer is larger than the predetermined depth.
7. The manufacturing method according to claim 5, wherein when the at least one first cavity is formed using a wet etching process,
the first sacrificial layer is formed by a plasma enhanced chemical vapor deposition process or a process using TEOS as a raw material.
8. The method of manufacturing of claim 5, further comprising, prior to forming the first structural layer:
removing the first sacrificial layer at least partially covering the prescribed surface using a thinning process, the thinning stopping when reaching the vicinity of the prescribed surface,
wherein the thinning error is positively correlated with the thickness of the first sacrificial layer.
9. The method of manufacturing according to claim 1, wherein the step of removing the first sacrificial layer in the first cavity comprises:
and removing the first sacrificial layer in the first cavity through the first channel hole by adopting a wet etching process so as to re-expose the first cavity.
10. The method of manufacturing according to claim 1, wherein the step of forming the flaring layer comprises:
when the atmospheric pressure environment in the first cavity is set to be the normal pressure environment or the high pressure environment, the thermal oxidation process is adopted to grow the external expansion layer at the first channel hole,
wherein the material of the flaring layer comprises an oxide.
11. The method of manufacturing according to claim 10, wherein the step of forming the flaring layer further comprises:
depositing an epitaxial material at the first via hole by a chemical vapor deposition process; and
the epitaxial material is made to epitaxially form the external expansion layer by adopting a thermal oxidation process,
wherein the epitaxial material comprises polysilicon.
12. The method of manufacturing according to claim 1, wherein the step of forming the flaring layer comprises:
when the atmospheric pressure environment inside the first cavity is set to be the normal pressure environment or the low pressure environment, respectively adopting the normal pressure chemical vapor deposition process and the low pressure chemical process to deposit the external expansion layer on the inner surface of the first cavity, the upper and lower surfaces of the first structural layer and the side wall of the first channel hole,
wherein the material of the outer expanding layer comprises silicon nitride and/or oxide.
13. The method of manufacturing of claim 12, wherein prior to depositing the outdated layer, the method of manufacturing further comprises:
and growing an oxide layer at the first channel hole by adopting a thermal oxidation process.
14. The manufacturing method according to claim 1, wherein after forming the first passage hole, the manufacturing method further comprises:
forming at least one second sacrificial layer and a second structural layer having a second via hole alternately stacked on the first structural layer,
wherein the first sacrificial layer and the second sacrificial layer are communicated through the first channel hole or the first channel hole and the second channel hole, and the first sacrificial layer and the second sacrificial layer are made of the same material.
15. The method of manufacturing of claim 14, wherein the step of removing the first sacrificial layer in the first cavity comprises:
removing the first sacrificial layer in the first cavity through the first and second via holes; and
removing at least a portion of the second sacrificial layer through the second via hole forms at least one second cavity.
16. The method of manufacturing according to claim 15, further comprising:
and closing at least part of the second channel hole to form the external expansion layer.
17. The manufacturing method according to claim 16, further comprising:
and removing part of the external expansion layer to enable part of the first cavity to be communicated with the second cavity and/or removing part of the external expansion layer to enable part of the second cavity to be communicated with the outside.
18. The manufacturing method according to any one of claims 1 to 17, wherein a material of the first sacrificial layer includes silicon dioxide or phosphosilicate glass.
19. The method of manufacturing according to any one of claims 1 to 17, wherein the material of the first structural layer comprises polysilicon.
20. A MEMS device, comprising:
a semiconductor substrate;
at least one first cavity extending into a semiconductor substrate from a designated surface of the semiconductor substrate;
a first structural layer having first via holes, the first structural layer covering the first cavities, each of the first cavities corresponding to a position of a corresponding one of the first via holes; and
an external expanding layer closing at least part of the first passage hole and extending from a sidewall of the first cavity toward the first structural layer to support the first structural layer; and
a first sacrificial layer between the designated surface and the first structural layer for supporting the first structural layer.
21. The MEMS device, as recited in claim 20, wherein the depth of the first cavity is no greater than half the thickness of the semiconductor substrate.
22. The MEMS device, as recited in claim 20, wherein the first cavity has a depth of no less than 2 μm.
23. The MEMS device, as recited in claim 20, further comprising:
at least one second sacrificial layer;
at least one second cavity in the second sacrificial layer; and
at least one second structural layer having second via holes, the at least one second sacrificial layer being alternately stacked with the at least one second structural layer on the first structural layer,
the second sacrificial layer is used for supporting the second structural layer.
24. The MEMS device, as recited in claim 23, wherein the flaring layer closes at least a portion of the second via holes.
25. The MEMS device of claim 24, wherein a portion of the first cavity communicates with the second cavity via the first via hole,
part of the second cavity is communicated with the outside through the second passage hole.
26. The MEMS device, as recited in any one of claims 20 through 25, wherein the material of the first sacrificial layer comprises silicon dioxide or phosphosilicate glass.
27. The MEMS device of any one of claims 20 through 25, wherein the material of the first structural layer comprises polysilicon.
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| CN115367694A (en) * | 2022-08-15 | 2022-11-22 | 瑞声声学科技(深圳)有限公司 | Manufacturing method of MEMS device and MEMS device |
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