CN110047764B - System-in-package method integrating FPGA chip and artificial intelligence chip - Google Patents
System-in-package method integrating FPGA chip and artificial intelligence chip Download PDFInfo
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- CN110047764B CN110047764B CN201910257501.0A CN201910257501A CN110047764B CN 110047764 B CN110047764 B CN 110047764B CN 201910257501 A CN201910257501 A CN 201910257501A CN 110047764 B CN110047764 B CN 110047764B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/8212—Aligning
Abstract
The invention discloses a system-in-package method for integrating an FPGA chip and an artificial intelligence chip, wherein the artificial intelligence bare chip is arranged on the FPGA bare chip; adding an FPGA silicon wafer through hole TSV at a proper position of the FPGA bare chip, and adding the TSV of the artificial intelligent bare chip at a position corresponding to the FPGA TSV on the artificial intelligent bare chip; establishing a corresponding relation between the IO of the artificial intelligent bare chip and the TSV and/or the bonding pad of the artificial intelligent bare chip, and deriving the corresponding relation; and limiting the TSV and/or the FPGA IO on the position of the optimal TSV and/or the position of the bonding pad of the FPGA bare chip corresponding to the TSV and/or the bonding pad of the artificial intelligent bare chip according to the corresponding relation, sequencing the FPGA IO according to the IO of the artificial intelligent bare chip to form an optimal connection relation, and then winding. The TSV and/or the bonding pad of the FPGA bare chip can be designed by referring to the TSV and/or the bonding pad of the artificial intelligent bare chip, the overall winding length, the winding difficulty and the signal load can be effectively reduced, and the timing performance of the winding is improved.
Description
Technical Field
The invention relates to the technical field of semiconductor device packaging, in particular to a system-level packaging method for integrating an FPGA chip and an artificial intelligence chip.
Background
Many products are overwhelmed compared to the brand new SoC that consumes a lot of time and money. For example, some socs have a time to market of up to 18 months, whereas the system-in-package method SiP can cut this time by 50% or less.
The SiP can integrate a plurality of packages, thereby significantly reducing package mention and weight, reducing the number of IO pins, shortening the connection lines between elements, and effectively transmitting signals. The SiP may incorporate a microprocessor, memory (e.g., EPROM and DRAM), FPGA, resistors, capacitors, and inductors in a package that holds up to four or five chips.
At present, the SiP of the FPGA die and the artificial intelligence die are packaged in a stacking or parallel arrangement manner. However, due to mutual independence in design, the pad of the FPGA die and the pad of the artificial intelligence die to be connected may be too far away or cross lines may be generated during the packaging process, thereby affecting the energy efficiency of the chip.
Disclosure of Invention
The invention aims to solve the defects in the prior art.
In order to achieve the purpose, the invention discloses a system-in-package method based on TSV. Comprises the following steps:
the method comprises the following steps that an FPGA silicon wafer through hole TSV is arranged on an FPGA bare chip, and the TSV of an artificial intelligent bare chip is arranged on the artificial intelligent bare chip; determining the properties of each TSV and/or bonding pad of the artificial intelligence bare chip according to the function of the artificial intelligence bare chip to be realized; fixing the position relation of the artificial intelligence bare chip relative to the FPGA bare chip according to the function of the system-in-package chip to be realized; connecting the TSV and/or the bonding pad of the artificial intelligence bare chip with the TSV and/or the bonding pad of the FPGA bare chip; configuring the properties of each TSV and/or bonding pad of each correspondingly connected FPGA bare chip according to the properties of each TSV and/or bonding pad of the artificial intelligent bare chip; and (3) according to the configured properties of the TSV and/or the bonding pad of each FPGA bare chip, laying out the internal logic of the FPGA to realize the function of the system-in-package chip.
Preferably, before determining the properties of each TSV and/or pad of the artificial intelligence die according to the function of the artificial intelligence die to be implemented, the function of the system-in-package chip to be implemented needs to be divided into an artificial intelligence die implementation function and an artificial intelligence die implementation function.
Preferably, the artificial intelligence off-die implementation function is implemented by the FPGA die in combination with other functional dies.
Preferably, the TSV and/or pad properties are such that the TSV and/or pad is used for input signals or output signals.
Preferably, the positional relationship of the artificial intelligence die relative to the FPGA die is fixed, the positional relationship comprising: the FPGA bare chip and the artificial intelligence bare chip are stacked or placed in parallel; wherein the content of the first and second substances,
defining the upper surfaces of the FPGA bare chip and the artificial intelligence bare chip with the bonding pads, and based on the TSV technology, the stacking relation comprises the following steps: the upper surface of the FPGA bare chip is jointed with the lower surface of the artificial intelligence bare chip, the lower surface of the FPGA bare chip is jointed with the lower surface of the artificial intelligence bare chip, and the lower surface of the FPGA bare chip is jointed with the upper surface of the artificial intelligence bare chip; the bonding includes the partial bonding of two surfaces and the complete coverage of one surface over the other.
Preferably, when the function of the system-in-package chip to be realized includes that the connection signal delay of the artificial intelligence bare chip and the FPGA bare chip is smaller than a certain threshold, the position relation of the artificial intelligence bare chip relative to the FPGA bare chip is fixed, so that the connection between each TSV and/or bonding pad of the artificial intelligence bare chip and each TSV and/or bonding pad of the FPGA bare chip to be connected is connected in an equal length, and further, the signal delay difference is lower than a certain threshold.
The invention has the advantages that: the TSV and/or the bonding pad of the FPGA bare chip can be designed by referring to the TSV and/or the bonding pad of the artificial intelligent bare chip, the overall winding length, the winding difficulty and the signal load can be effectively reduced, and the timing performance of the winding is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a TSV-based system-in-package structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention is described in detail below with reference to the figures and the specific embodiments.
The invention discloses a system-in-package method for integrating an FPGA chip and an artificial intelligence chip. Before implementing the method, the functions of the system-in-package chip to be implemented need to be divided in advance, wherein part of the functions are implemented by the artificial intelligence bare chip, and the rest of the functions are implemented by other bare chips besides the artificial intelligence bare chip. Other dies than the artificial intelligence die mentioned here mainly include FPGA dies, and in addition, according to the details of the remaining functions, it is possible to further include FLASH dies, Processor dies, SRAM dies, etc., but not limited to the mentioned kinds of dies.
Step S101 of the invention: the FPGA die is provided with an FPGA silicon wafer through hole TSV, and the artificial intelligence die is provided with the TSV.
Step S102: and determining the properties of each TSV and/or bonding pad of the artificial intelligence bare chip according to the function of the artificial intelligence bare chip to be realized.
Such as defining a certain TSV or pad for input signals, another TSV or pad for output signals, etc.
Step S103: and fixing the position relation of the artificial intelligence bare chip relative to the FPGA bare chip according to the function of the system-in-package chip to be realized.
For example, according to the function of the system-in-package chip to be realized and the function of the artificial intelligence bare chip to be realized, the lengths of the wires connected between the TSV and/or the bonding pad of the artificial intelligence bare chip and the TSV and/or the bonding pad of the FPGA bare chip are equal, so that the signal delay difference between the bonding pads of the artificial intelligence bare chip is minimized.
Specifically, the position relationship of the artificial intelligence die relative to the FPGA die may include a position relationship in which two dies are stacked or placed in parallel, and may also include a position relationship in which two dies are partially overlapped.
Further, in the stacking relationship, due to the existence of the TSVs, the connection relationship is simple from the connection between the pads, and the connection between the TSVs and the connection between the pads should be provided.
For example, defining one side of the artificial intelligence die and the FPGA die having the bonding pads as the upper surface and the other side as the lower surface, in the case of stacking, there are the following possibilities:
the artificial intelligence bare chip upper surface is jointed and overlapped with the FPGA bare chip lower surface, under the condition, the first connection mode is that the artificial intelligence bare chip is connected with the TSV on the FPGA lower surface through a bonding pad, the second connection mode is that the artificial intelligence bare chip is connected with the TSV on the FPGA lower surface through the TSV on the upper surface, the third connection mode is that when the area of the artificial intelligence bare chip is larger than that of the FPGA bare chip or the two bare chips are partially overlapped, namely the bonding pad part on the upper surface of the artificial intelligence bare chip is not shielded by the FPGA bare chip, the artificial intelligence bare chip is connected with the FPGA bonding pad through the bonding pad, under the condition, the three connection modes can exist independently or simultaneously, and other connection modes can exist.
And (II) the lower surface of the artificial intelligent bare chip is jointed and overlapped with the upper surface of the FPGA bare chip, under the condition, the first connection mode is that the artificial intelligent bare chip is connected with the FPGA bonding pad through the bonding pad, the second connection mode is that the artificial intelligent bare chip is connected with the corresponding FPGA bonding pad covered by the artificial intelligent bare chip through the TSV on the lower surface, and the third connection mode is that the artificial intelligent bare chip is connected with the TSV on the corresponding FPGA upper surface covered by the artificial intelligent bare chip through the TSV on the lower surface, as shown in figure 1, under the condition, the three connection modes can exist independently or simultaneously, and other connection modes can also exist.
And thirdly, the lower surface of the artificial intelligent bare chip is jointed and overlapped with the lower surface of the FPGA bare chip, in this case, the artificial intelligent bare chip is connected with the TSV corresponding to the lower surface of the FPGA through the TSV on the lower surface, and other connection modes can exist.
Step S104: connecting the TSV and/or the bonding pad of the artificial intelligence bare chip with the TSV and/or the bonding pad of the FPGA bare chip; and configuring the properties of each TSV and/or bonding pad of each correspondingly connected FPGA die according to the properties of each TSV and/or bonding pad of the artificial intelligence die.
For example, a certain TSV or pad defined on the artificial intelligence die is used for inputting signals, and the TSV or pad on the FPGA die connected to the TSV or pad is used for outputting signals, so as to form a corresponding relationship with the TSV or pad of the artificial intelligence die.
The connection can be made through an interposing interposer substrate and/or an underlying substrate, and is not limited to the two mentioned substrate connection methods.
Step S105: and (3) according to the configured properties of the TSV and/or the bonding pad of each FPGA bare chip, laying out the internal logic of the FPGA to realize the function of the system-in-package chip.
Specifically, hardware description languages for laying out the internal logic of the FPGA can be selected and used, including but not limited to VHDL and Verilog languages.
At present, the connection of interface signals between an FPGA bare chip and an artificial intelligence bare chip inside the DDR3 generally requires that a delay error between signals of the DDR3 interface is less than or equal to 10 ps.
When the existing traditional method is adopted for connection, a certain bonding pad of the FPGA bare chip is connected to a certain bonding pad of the nearest artificial intelligence bare chip, and the other bonding pad of the FPGA bare chip is connected to a certain bonding pad of the farther artificial intelligence bare chip, so that the difference between the two connecting lines is larger than or equal to 10 mm. If the output voltage is 2.5v, the output current is 2mA, and the resistance is 50 Ω, the signal delay difference between the two wires can reach 60ps when the difference between the two wires is greater than or equal to 10 mm.
When the method provided by the patent is adopted for connection, in a specific embodiment, according to the requirement of DDR3 for each interface delay error, each interface delay error threshold is set to be 6ps, selecting the optimal artificial intelligence bare chip placement position on the FPGA bare chip connected with the artificial intelligence bare chip according to the TSV and/or the bonding pad of the artificial intelligence bare chip, the placement positions of the artificial intelligence bare chips with the same length of the connecting lines between the TSV and/or the bonding pads of the artificial intelligence bare chips and the TSV and/or the bonding pads of the FPGA bare chips can be realized, and fixing the position relationship between the artificial intelligence bare chip and the FPGA bare chip, determining the properties of the TSV and/or the bonding pad on the artificial intelligence bare chip according to the function to be realized on the artificial intelligence bare chip by the DDR3, and configuring the properties of the TSV and/or the bonding pad on each FPGA which is connected with the TSV and/or the bonding pad in the same length as the artificial intelligence bare chip. The difference in the distances between the respective connection lines is 1mm or less. If the output voltage is 2.5v, the output current is 2mA, and the resistance is 50 Ω, the signal delay difference between the two wires is less than or equal to 6ps under the condition that the difference between the two wires is less than or equal to 1 mm.
The invention provides a system-in-package method for integrating an FPGA chip and an artificial intelligence chip. The TSV and/or the bonding pad of the FPGA bare chip are designed by referring to the TSV and/or the bonding pad of the artificial intelligent bare chip, the overall winding length, the winding difficulty and the signal load can be effectively reduced, and the timing sequence performance of the winding is improved.
The above embodiments are provided to further explain the objects, technical solutions and advantages of the present invention in detail, it should be understood that the above embodiments are merely exemplary embodiments of the present invention and are not intended to limit the scope of the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (4)
1. A system-in-package method for integrating an FPGA chip and an artificial intelligence chip is characterized by comprising the following steps:
arranging TSV of the artificial intelligence bare chip on the artificial intelligence bare chip; setting a through hole TSV of an FPGA silicon chip on the FPGA die according to the position of the TSV of the artificial intelligence die;
determining the properties of each TSV and/or bonding pad of the artificial intelligence bare chip according to the function of the artificial intelligence bare chip to be realized;
fixing the position relation of the artificial intelligence bare chip relative to the FPGA bare chip according to the function of the system-in-package chip to be realized; defining one side of the FPGA bare chip and the artificial intelligence bare chip provided with the bonding pads as an upper surface, and enabling the lower surface of the artificial intelligence bare chip to be jointed and overlapped with the upper surface of the FPGA bare chip, wherein the artificial intelligence bare chip exposes part of the bonding pads on the upper surface of the FPGA bare chip; the mode of connecting the artificial intelligence bare chip and the FPGA bare chip comprises that the artificial intelligence bare chip is connected with a bonding pad of the FPGA bare chip through a bonding pad, the artificial intelligence bare chip is connected with the bonding pad of the corresponding FPGA bare chip covered by the artificial intelligence bare chip through a TSV on the lower surface, and the artificial intelligence bare chip is connected with the TSV on the upper surface of the corresponding FPGA bare chip covered by the artificial intelligence bare chip through the TSV on the lower surface; when the functions of the system-in-package chip to be realized comprise that the delay time of a connecting line signal of the artificial intelligent bare chip and the FPGA bare chip is smaller than a certain threshold value, connecting lines between each TSV and/or bonding pad of the artificial intelligent bare chip and each TSV and/or bonding pad of the FPGA bare chip to be connected according to the position relation of the fixed artificial intelligent bare chip relative to the FPGA bare chip, and further enabling the delay time of the signal to be lower than the certain threshold value;
configuring the properties of each TSV and/or bonding pad of each correspondingly connected FPGA bare chip according to the properties of each TSV and/or bonding pad of the artificial intelligence bare chip;
and laying out internal logic of the FPGA according to the configured properties of the TSV and/or the bonding pad of each FPGA bare chip, and connecting the TSV and/or the bonding pad of the artificial intelligent bare chip with the TSV and/or the bonding pad of the FPGA bare chip to realize the functions of the system-in-package chip.
2. The system-in-package method according to claim 1, wherein before determining the TSV and/or pad properties of the artificial intelligence die according to the artificial intelligence die function to be implemented, the method further comprises:
and dividing the functions of the system-in-package chip to be realized into an artificial intelligence bare chip realization function and an artificial intelligence bare chip external realization function.
3. The system-in-package method of claim 2, wherein the artificial intelligence off-die implementation function is implemented jointly by the FPGA die and other functional dies.
4. The system-in-package method according to claim 1, wherein the TSV and/or pad properties are that the TSV and/or pad is used for input signals or output signals.
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