CN110045992B - Universal system and method suitable for multi-core board card - Google Patents
Universal system and method suitable for multi-core board card Download PDFInfo
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Abstract
The invention provides a general system and a method suitable for a multi-core board card, and provides an automatic configuration tool for configuring hardware resources, wherein an ARCH (architecture and configuration protocol) layer and a BSP (base station protocol) layer are abstracted from a platform applying the general system, whether other CPUs (central processing units) normally operate is detected through a heartbeat packet, and inter-core broadcasting is eliminated through cache division and general register setting, so that configuration intellectualization, diversification of a hardware platform and system stability are realized.
Description
Technical Field
The invention relates to the field of mixed multi-system, in particular to a universal system and a method suitable for a multi-core board card.
Background
With the updating and upgrading of embedded products, more and more functions are concentrated on the same piece of hardware, and the functions are often interconnected and influenced with each other. In order to better process real-time tasks and non-real-time tasks, the mixed multi-system can enable the tasks to be divided into more finely and flexibly adapt to different situations.
At present, a known hybrid multi-System is an AMP (Accelerated Mobile Pages) technology based on a dual-core CPU, and is mostly implemented by using Linux and μ COS (Micro-controller Operating System, real-time multi-task Operating System) in a matching manner, that is, the CPU0 runs Linux, and the CPU1 runs μ COS. This method has major drawbacks and disadvantages:
① consume unnecessary resources and time
Memory resources need to be divided in the code stage in advance, a running CPU is specified, and the loading work is carried out after recompilation. The code implementation is often distributed in different kernel components, and the modification is time-consuming and labor-consuming;
② binding hardware, mostly limited to ARM
The existing method is only suitable for a dual-core processor of an ARM system architecture, and along with the increase of functional complexity, the performance of a hardware processor is improved, and hardware replacement cannot be suitable for the dual-core processor, for example, an intel processor of an X86 architecture and an MPSOC processor of a quad-core ARM Cortex A53 cannot be suitable for the dual-core processor.
③ high complexity and difficult maintenance
In the operation process, whether other CPU cores normally operate cannot be judged, which easily causes errors in providing data and functions for applications.
④ have a significant impact on other running applications in the system, causing real-time task jitter
If the task on one CPU has bug to restart, the other CPU will be restarted, which will cause the CPU in normal operation to be restarted; if a task on one of the CPUs performs a large number of system calls and the like to enter a kernel privileged state, a large jitter is caused to the operation of a task on the other CPU.
Disclosure of Invention
In order to overcome the defects of the application program, the invention provides a universal system suitable for a multi-core board card. The platform not only reduces the mutual interference among the cores, but also provides a plurality of functional components which can be directly used, and is convenient for programmers to use.
The technical scheme of the invention is as follows:
a general system suitable for multi-core board cards is characterized by comprising an ARCH layer and a board level Support package (BSP) (Board Support Package) layer, and an automatic configuration tool modifies resources of a platform applying the general system, wherein:
the main core CPU0 runs Linux, other CPUs run SylixOS, a compiling chain of the SylixOS is deployed on Linux, an ARCH layer and a BSP layer provide different mirror image libraries, and the SylixOS is a domestic large embedded real-time operating system;
the automatic configuration tool modifies the script, automatically positions the configuration code to select and modify memory resources, CPU resources, interrupt resources, hardware architecture and the like, and automatically runs after compiling.
Further, an ARCH layer and a BSP layer are abstracted, wherein the ARCH layer and the BSP layer are designed by a general interface provided by an operating system for upper-layer application, and an application programming interface is directly called in the application writing process; when the specific implementation of the ARCH layer and the BSP layer is not available, the application calls only the empty function interface, and when the operating system links the specific implementation of the ARCH layer and the BSP layer to the programming interface, the application completes the call.
A user operation method of a universal system suitable for a multi-core board card is characterized by comprising the following steps:
and starting a program by a user, opening the configuration tool, selecting a framework and the BSP, configuring hardware resources, and automatically compiling Operating Systems (OS) on all CPUs (central processing units), so as to start a platform applying the general system.
An operation method of a universal system suitable for a multi-core board card is characterized by comprising the following steps:
and the general system starting program opens the configuration tool, automatically imports a source code project, automatically searches a directory to modify a related system file, and automatically compiles Operating Systems (OSs) on all CPUs (central processing units), thereby starting a platform applying the general system.
A method for realizing independent restart among multiple cores of a universal system suitable for a multi-core board card is characterized by comprising the following steps:
when a task on one CPU has bug to cause restart operation, because the binding of interruption is carried out through a configuration file in advance, namely private interruption, whether the slave core is abnormally restarted or not is judged when the slave core needs to be started, namely non-power-down restart; if not, initializing all hardware resources; if the CPU is abnormally restarted, judging whether the CPU is the resource used by the CPU, and if the CPU is the resource used by the CPU, initializing a hardware resource; if the CPU resource is not the resource used by the CPU, the initialization operation is not carried out, namely, the operating system resources on other CPUs are not reinitialized, so that the independent restart among multiple cores is realized, and the normal operation of tasks on other CPUs is not influenced.
Furthermore, a heartbeat detection function needs to be provided in the platform and is used for judging whether other CPU cores run normally or not; specifically, the CPU sends a heartbeat packet to another CPU in a normal operation state, the other CPU queries heartbeat data after receiving the heartbeat packet, and if it is determined that the CPU is operating normally, the heartbeat detection function is continued.
Dividing the last level cache, locking on each CPU, operating the hardware auxiliary register, and shielding the broadcast operation generated by the consistency of the translation detection buffer TLB (translation Lookaside buffer); if the task on one CPU is in the operation of entering the kernel privilege state such as a large number of system calls, other CPUs cannot be influenced.
A computer readable storage medium comprising a processor and a memory, the memory having stored therein computer program instructions which, when executed by the processor, are adapted to carry out the method.
Compared with the prior art, the invention has the beneficial effects that:
① is convenient to use and saves time
Quota modification on hardware and resources is easily realized through an intelligent configuration tool; the intelligent configuration can be realized, the hardware processor is diversified, and the use scenes of enough users are met.
② hardware enrichment
The diversification of the hardware platform can be realized by abstracting the ARCH layer and the BSP layer of the platform of the application system, and the application system can be adapted to various hardware platforms.
③ Intelligent detection of software integrity
Through the heartbeat detection function, the robustness and the completeness of the platform are guaranteed, and the normal operation of the upper-layer application is guaranteed.
④ has good stability
The stability of the platform is ensured by processing the influence among multiple cores, such as cache lock, broadcast shielding and other operations.
Drawings
Fig. 1 is a schematic diagram of a general system suitable for a multi-core board card in the embodiment of the present invention.
Fig. 2 is an architecture diagram of a general system suitable for a multi-core board card in the embodiment of the present invention.
Fig. 3 is a schematic diagram of a user operation method and a platform operation method of a general system suitable for a multi-core board card in the embodiment of the present invention.
Fig. 4 is a flowchart of a general system applicable to a multi-core board card in an embodiment of the present invention to implement independent reboot between multiple cores.
Fig. 5 is a flowchart of internal heartbeat detection of a general system suitable for a multi-core board card in the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantageous technical effects of the present invention clearer, the present invention is further described in detail with reference to the following embodiments. It should be understood that the embodiments described in this specification are only for the purpose of explaining the present invention and can be implemented, but the embodiments are not to be construed as limiting the present invention.
Example 1
As shown in fig. 1 and fig. 2, the general system applicable to multi-core boards in the embodiment of the present invention is characterized by including an ARCH layer and a board level Support package bsp (board Support package) layer, and an automatic configuration tool modifies resources of a platform to which the general system is applied, where:
the master core and the slave core may be any operating systems, and both the master core and the slave core in fig. 1 are SylixOS, and both the master core and the slave core include universal asynchronous receiver transmitter URAR1, a media access control MAC, an embedded multimedia card eMMC and a register CACHE; the hardware common part comprises an interrupt controller GIC and an on-chip memory OCM.
In the following, taking an example that a main core runs Linux, and other cores run SylixOS, wherein SylixOS is a domestic large-scale embedded real-time operating system;
the main core CPU0 runs Linux, other core CPUs run SylixOS, a compiling chain of the SylixOS is deployed on Linux, and the ARCH layer and the BSP layer provide different mirror image libraries;
the automatic configuration tool modifies the script, automatically positions the configuration code to select and modify the memory resource, the CPU resource, the interrupt resource and the hardware architecture, and automatically runs after compiling.
Abstracting an ARCH layer and a BSP layer, wherein the ARCH layer and the BSP layer are designed by a general interface provided by an operating system for upper-layer application, and directly calling an application programming interface in the process of writing the application; when the specific implementation of the ARCH layer and the BSP layer is not available, the application calls only the empty function interface, and when the operating system links the specific implementation of the ARCH layer and the BSP layer to the programming interface, the application completes the call.
Example 2
As shown in fig. 3, a user operation method of a generic system suitable for a multi-core board card and an operation method of the generic system according to the present invention are characterized in that,
the user operation method comprises the following steps: a user starts a program, opens the configuration tool, selects a framework and the BSP, configures hardware resources, and automatically compiles Operating Systems (OS) on all CPUs (central processing units), so as to start a platform applying the general system;
the general system operation method comprises the following steps: and the general system starting program opens the configuration tool, automatically imports a source code project, automatically searches a directory to modify a related system file, and automatically compiles Operating Systems (OSs) on all CPUs (central processing units), thereby starting a platform applying the general system.
Example 3
As shown in fig. 4, a method for implementing independent reboot between multiple cores for a general system suitable for multiple core boards according to the present invention is characterized in that,
when a task on one CPU has bug to cause restart operation, because the binding of interruption is carried out through a configuration file in advance, namely private interruption, whether the slave core is abnormally restarted or not is judged when the slave core needs to be started, namely non-power-down restart; if not, initializing all hardware resources; if the CPU is abnormally restarted, judging whether the CPU is the resource used by the CPU, and if the CPU is the resource used by the CPU, initializing a hardware resource; if the CPU resource is not the resource used by the CPU, the initialization operation is not carried out, namely, the operating system resources on other CPUs are not reinitialized, so that the independent restart among multiple cores is realized, and the normal operation of tasks on other CPUs is not influenced.
Example 4
As shown in fig. 5, the method for detecting the heartbeat in the general system applicable to the multi-core board card is characterized in that a heartbeat detection function needs to be provided in the platform to determine whether other CPUs are operating normally; specifically, the CPU sends a heartbeat packet to another CPU in a normal operation state, the other CPU queries heartbeat data after receiving the heartbeat packet, and if it is determined that the CPU core is operating normally, the heartbeat detection function is continued.
Furthermore, the last level cache is divided in advance, locked on each CPU, and the hardware auxiliary register is operated to shield the broadcast operation generated by the consistency of the translation detection buffer TLB (translation Lookaside buffer). If the task on one CPU is in a large amount of system calls and other operations entering the kernel privilege state, other CPUs cannot be influenced, and the task is really more independent.
In the design of a processor, a general last level cache is shared by all CPU cores, a corresponding register is provided in an ARMv7 architecture, the cache can be set to be used to ensure that the cache is not cleared by other cores, and specific codes are as follows:
REG _ WRITE (L2CACHE _ BAR + L2CACHE _ OFFSET _ LOCKDOWN +0x0,0xFFF 0); icache with cpu0 set
REG _ WRITE (L2CACHE _ BAR + L2CACHE _ OFFSET _ LOCKDOWN +0x4,0xFFF 0); set the dcache of cpu0
REG _ WRITE (L2CACHE _ BAR + L2CACHE _ OFFSET _ LOCKDOWN +0x8,0xFF 0F); icache with cpu1 set
REG _ WRITE (L2CACHE _ BAR + L2CACHE _ OFFSET _ LOCKDOWN +0xC,0xFF 0F); set the dcache of cpu1
In addition, in the ARMv7 architecture, when we operate the cache, we broadcast the CPU in the same cluster, thereby interfering with the operating efficiency of the CPU, mainly controlled by the ACTLR register, and shut off the broadcast by operating the cp15 register, with the following specific codes:
according to the technical scheme, the invention provides an automatic configuration tool to configure hardware resources, an ARCH and BSP layer is abstracted from a platform applying the system, whether other CPUs (central processing units) normally operate or not is detected through heartbeat packets, inter-core broadcasting is eliminated through cache division and general register setting, and the stability of the system is improved.
Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those skilled in the art.
Claims (5)
1. A general system suitable for multi-core board cards is characterized by comprising an ARCH layer and a board level support package (BSP) layer, and an automatic configuration tool modifies resources of a platform applying the general system, wherein:
the main core CPU0 runs Linux, other CPUs run SylixOS, a compiling chain of the SylixOS is deployed on Linux, an ARCH layer and a BSP layer provide different mirror image libraries, and the SylixOS is a domestic large embedded real-time operating system;
the automatic configuration tool modifies the script, automatically positions the configuration code to select and modify the memory resource, the CPU resource, the interrupt resource and the hardware architecture, and automatically runs after compiling;
the method for realizing independent restart among multiple cores of the universal system suitable for the multiple-core board card comprises the following steps:
when a task on one CPU has bug to cause restart operation, because the binding of interruption is carried out through a configuration file in advance, namely private interruption, whether the slave core is abnormally restarted or not is judged when the slave core needs to be started, namely non-power-down restart; if not, initializing all hardware resources; if the CPU is abnormally restarted, judging whether the CPU is the resource used by the CPU, and if the CPU is the resource used by the CPU, initializing a hardware resource; if the resource is not the resource used by the CPU, the initialization operation is not carried out, namely, the operating system resources on other CPUs are not reinitialized, so that the independent restart among the multiple cores is realized, and the normal operation of the tasks on other CPUs is not influenced;
a heartbeat detection function is required to be provided in the system and is used for judging whether other CPUs are normally operated; specifically, the CPU sends a heartbeat packet to other CPUs in a normal operation state, the other CPUs query heartbeat data after receiving the heartbeat packet, and if it is determined that the CPU core is operating normally, the heartbeat detection function is continued;
dividing the last level cache, locking the last level cache on each CPU, operating a hardware auxiliary register at the same time, and shielding the broadcast operation generated by the consistency of the translation detection buffer TLB; if the task on one CPU is in the operation of entering the kernel privilege state such as a large number of system calls, other CPUs cannot be influenced.
2. The universal system applicable to multi-core boards as claimed in claim 1, wherein the ARCH layer and the BSP layer are abstracted, wherein the ARCH layer and the BSP layer are designed by a universal interface provided by an operating system for upper layer applications, and an application programming interface is directly called in an application writing process; when the specific implementation of the ARCH layer and the BSP layer is not available, the application calls only the empty function interface, and when the operating system links the specific implementation of the ARCH layer and the BSP layer to the programming interface, the application completes the call.
3. A user operation method for applying the general system applicable to the multi-core board card according to any one of claims 1-2, comprising the following steps:
and starting a program by a user, opening the configuration tool, selecting a framework and the BSP, configuring hardware resources, and automatically compiling Operating Systems (OS) on all CPUs (central processing units), thereby starting a platform applying the general system.
4. An operation method of the general system applicable to the multi-core board card according to any one of claims 1-2 is characterized by comprising the following steps:
and the general system starting program opens the configuration tool, automatically imports a source code project, automatically searches a directory to modify a related system file, and automatically compiles Operating Systems (OSs) on all CPUs (central processing units), thereby starting a platform applying the general system.
5. A computer readable storage medium having stored therein computer program instructions which, when executed by a processor, are adapted to carry out the method of any one of claims 3 to 4.
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| CN112559190B (en) * | 2020-12-23 | 2022-01-11 | 科东(广州)软件科技有限公司 | Resource allocation method, system, device, equipment and medium among heterogeneous systems |
| CN113495781B (en) * | 2021-06-30 | 2023-03-03 | 东风商用车有限公司 | Task scheduling method, device, equipment and readable storage medium |
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