CN110034847B

CN110034847B - Cascade coding method and device

Info

Publication number: CN110034847B
Application number: CN201810032429.7A
Authority: CN
Inventors: 黄科超; 梁伟光; 马会肖
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-01-12
Filing date: 2018-01-12
Publication date: 2022-01-14
Anticipated expiration: 2038-01-12
Also published as: CN110034847A

Abstract

The application discloses cascade coding device includes: a first stage code interleaver and a second stage encoder. The first-level code interleaver comprises a first buffer and a second buffer, wherein the first buffer stores information data at the current moment, and the second buffer stores data stored in the first buffer at the previous moment; a first-stage code interleaver performs first-stage coding on mth row data in a first cache and nth row data in a second cache to obtain mth check data, and stores the mth check data in the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n; and then interleaving the data in the first cache according to a preset mode to obtain a first code word, and performing second-level coding on the first code word by using a second-level coder to obtain a second code word and sending the second code word. The interleaving adopting the preset mode can reduce the error code correlation between the code words generated by the two stages of coding devices.

Description

Cascade coding method and device

Technical Field

The present application relates to the field of coding, and in particular, to a method and an apparatus for cascade coding.

Background

At present, high-speed optical transmission networks are developing towards high-capacity, packetized and intelligent. High-speed optical transmission networks need to use efficient Forward Error Correction (FEC) codes to combat optical impairments (such as uncompensated chromatic dispersion, polarization mode dispersion, and nonlinear effects) during optical transmission and maintain a sufficiently low bit Error rate over long distances. In the existing transmission network, the concatenated code can balance the coding gain performance and the coding and decoding complexity, so that the method is widely applied. Concatenated codes are implemented in the form of a combination of two or more coding methods, the most common of which is two-level concatenated codes.

However, in a commonly used two-stage concatenated code system, the error code correlation between two different code words may cause system performance degradation, and the present application provides a concatenated coding method and apparatus, which can remove the error code correlation between different code words and have low complexity.

Disclosure of Invention

The present application aims to provide a method and an apparatus for concatenated coding, which solve the problem of system performance degradation caused by error code correlation between two different code words in a concatenated code system.

In a first aspect, a concatenated coding apparatus is provided, including: the encoder comprises a first-level code interleaver and a second-level encoder, wherein the first-level code interleaver comprises a first cache and a second cache, the first cache stores information data at the current moment, and the second cache stores data stored in the first cache at the previous moment; the first-stage code interleaver is used for performing first-stage coding on mth row data in the first cache and nth row data in the second cache to obtain mth check data, and storing the mth check data in the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n; the first-stage code interleaver interleaves the data in the first buffer according to a preset mode to obtain a first code word, wherein the preset mode is any one of the following four modes:

(1) w x r + k-th of the first codeword₁The data is the jth data in the first buffer memory₁Line kth₁The column values;

(2) w x r + k-th of the first codeword₁The data is the R-1-j in the first buffer memory₁Line kth₁The column values;

(3) w x r + k-th of the first codeword₁The data is the jth data in the first buffer memory₁Line W-1-k₁The column values;

(4) w x r + k-th of the first codeword₁The data is the R-1-j in the first buffer memory₁Line W-1-k₁The column values;

wherein W is the number of columns of data in the first cache, R is the number of rows of data in the first cache, W, R, R, k₁，j₁Is an integer, 0 ≦ R ≦ R-1, 0 ≦ k₁≦W-1，j₁＝(r+k₁)mod R；

And the second-level encoder is used for carrying out second-level encoding on the first code word to obtain a second code word and sending the second code word.

According to the embodiment of the application, data interleaving is performed according to a preset mode, so that any two data contained in the second code word cannot come from the same row or the same column in the first cache, the error code correlation between two different code words is reduced, and the coding complexity is low.

In a second aspect, a concatenated coding apparatus is provided, including: the encoder comprises a first-level code interleaver and a second-level encoder, wherein the first-level code interleaver comprises a first cache and a second cache, the first cache stores information data at the current moment, and the second cache stores data stored in the first cache at the previous moment; the first-stage code interleaver is used for performing first-stage coding on mth row data in the first cache and nth row data in the second cache to obtain mth check data, and storing the mth check data in the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n; interleaving information data in the 0 th column to the W-P-1 th column in the first cache according to a first preset mode to obtain an information sequence, wherein the first preset mode is any one of the following four modes:

(1) (W-P) x r + k of the information sequence₂The data is the jth data in the first buffer memory₂Line kth₂The column values;

(2) (W-P) x r + k of the information sequence₂The data is the R-1-j in the first buffer memory₂Line kth₂The column values;

(3) (W-P) x r + k of the information sequence₂The data is the jth data in the first buffer memory₂Line W-P-1-k₂The column values;

(4) (W-P) x r + k of the information sequence₂The data is the R-1-j in the first buffer memory₂Line W-P-1-k₂The column values;

wherein W is the number of columns of data in the first cache, R is the number of rows of data in the first cache, W, R, P, R, k₂，j₂Is an integer, 0 ≦ R ≦ R-1, 0 ≦ k₂≦W-P-1，j₂＝(r+k₂)mod(W-P)；

Interleaving the check data from the W-P column to the W-1 column in the first cache according to a second preset mode to obtain a check sequence, wherein the second preset mode is any one of the following four modes:

(1) the Pxr + k-th of the check sequence₃The data is the jth data in the first buffer memory₃Line kth₃Column + W-P values;

(2) the Pxr + k-th of the check sequence₃The data is the R-1-j in the first buffer memory₃Line kth₃Column + W-P values;

(3) the Pxr + k-th of the check sequence₃The data is the jth data in the first buffer memory₃Line W-1-k₃The column values;

(4) the Pxr + k-th of the check sequence₃The data is the R-1-j in the first buffer memory₃Line W-1-k₃The column values;

wherein k is₃，j₃Is an integer, 0 ≦ k₃≦P-1，j₃＝(r+k₃)mod P；

Combining the information sequence and the check sequence to obtain a first code word; and the second-level encoder is used for carrying out second-level encoding on the first code word to obtain a second code word and sending the second code word.

The information data and the check data are respectively interleaved and then combined into the first code word, the positions of the information data and the check data can be simply distinguished from the first code word, the systematized form of the first code word is kept, and under the normal condition, the number of columns of the information data in the first cache is larger than the length of the code word of the second-level code, so that the error code correlation between two different code words can be reduced, and the code performance is improved.

With reference to the first aspect or the second aspect, in a first possible implementation manner of the first aspect or the second aspect, the second-level encoder includes an insertion module and an encoding module, where the insertion module is configured to insert a preset sequence with a length of d bits at a tail of the first codeword to obtain a third codeword with a length of s, where s and d are positive integers, and s is a positive integer multiple of an information length of the second codeword; and the coding module is used for carrying out second-level coding on the third code word to obtain a second code word and sending the second code word out. In this embodiment, by filling the preset sequence with a certain length, the code length of the third codeword for the second-level encoding is an integral multiple of the information length of the second codeword, thereby ensuring that all data can be encoded.

With reference to the first aspect or the first possible implementation manner of the second aspect, in a second possible implementation manner of the first aspect or the second aspect, the information data in the first cache includes 512 rows × 478 columns, the check data in the first cache includes 512 rows × 32 columns, the second-level encoding includes hamming (128,119) encoding, and d ═ 85+119 × i, i is a non-negative integer.

With reference to the first aspect or the second aspect, in a third possible implementation manner of the first aspect or the second aspect, the first-level coding includes ladder coding, and the second-level coding includes hamming (128,119) coding; the information data in the first cache comprises 512 rows × 478 columns, and the check data in the first cache comprises 512 rows × 32 columns.

With reference to the first aspect or the third possible implementation manner of the second aspect, in a fourth possible implementation manner of the first aspect or the second aspect, the concatenated coding apparatus further includes a CRC encoder, a first insertion module, and a deletion module; the CRC encoder is used for carrying out 32-bit CRC encoding on the 244664-bit first sequence to obtain a second sequence with the length of 244696 bits; the first inserting module is configured to insert a 6-bit padding sequence at the end of the second sequence to obtain a third sequence of 244702 bits, and insert a 34-bit all-0 sequence at the end of the third sequence to obtain 244736 bits of the information data; sending the information data to the first-stage code interleaver; the deleting module is configured to delete the data of the 34-bit all-0 sequence included in the received 261120-bit first codeword, so as to obtain a fourth sequence with a length of 261086;

the second-level encoder comprises a second insertion module and an encoding module; the second inserting module is configured to insert a 714-bit preset sequence at the tail of a fifth sequence of 1305430 bits to obtain a sixth sequence of 1306144 bits in length, where the fifth sequence includes five consecutive fourth sequences; the encoding module is configured to hamming (128,119) encode the sixth sequence.

With reference to the first aspect or the third possible implementation manner of the second aspect, in a fifth possible implementation manner of the first aspect or the second aspect, the concatenated coding apparatus further includes a CRC encoder and a first insertion module; the CRC encoder is used for carrying out 32-bit CRC encoding on the 244664-bit first sequence to obtain a second sequence with the length of 244696 bits; the first inserting module is configured to insert a 6-bit padding sequence at the end of the second sequence to obtain a third sequence of 244702 bits, and insert a 34-bit all-0 sequence at the end of the third sequence to obtain 244736 bits of the information data; sending the information data to the first-stage code interleaver;

the second-level encoder comprises a second insertion module and an encoding module; the second inserting module is configured to insert a 544-bit preset sequence at the tail of an 1305600-bit fourth sequence to obtain a 1306144-bit fifth sequence, where the fourth sequence includes five consecutive first codewords of length 261120; the encoding module is configured to hamming (128,119) encode the fifth sequence.

In a third aspect, a concatenated coding method is provided, including: receiving information data of the current moment, wherein the information data of the current moment is stored in a first cache, and data stored in the first cache at the previous moment is stored in a second cache; performing first-level coding on the mth row of data in the first cache and the nth row of data in the second cache to obtain mth check data, and storing the mth check data in the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n; interleaving the data in the first cache according to a preset mode to obtain a first code word, wherein the preset mode is any one of the following four modes:

And carrying out second-level coding on the first code word to obtain a second code word, and sending out the second code word.

In a fourth aspect, a concatenated coding method is provided, including: receiving information data of the current moment, wherein the information data of the current moment is stored in a first cache, and data stored in the first cache at the previous moment is stored in a second cache; performing first-level coding on the mth row of data in the first cache and the nth row of data in the second cache to obtain mth check data, and storing the mth check data in the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n;

interleaving information data in the 0 th column to the W-P-1 th column in the first cache according to a first preset mode to obtain an information sequence, wherein the first preset mode is any one of the following four modes:

(4) the Pxr + k-th of the check sequence₃The data is the firstThe R-1-j in the cache₃Line W-1-k₃The column values;

wherein k is₃，j₃Is an integer, 0 ≦ k₃≦P-1，j₃＝(r+k₃)mod P；

Combining the information sequence and the check sequence to obtain a first code word; and carrying out second-level coding on the first code word to obtain a second code word, and sending out the second code word.

With reference to the third aspect or the fourth aspect, in a first possible implementation manner of the third aspect or the fourth aspect, the performing second-level coding on the first codeword specifically includes: and inserting a preset sequence with the length of d bits into the tail of the first code word to obtain a third code word with the length of s, and performing second-level coding on the third code word, wherein s and d are positive integers, and s is a positive integer multiple of the information length of the second code word. In this embodiment, by filling the preset sequence with a certain length, the code length of the third codeword for the second-level encoding is an integral multiple of the information length of the second codeword, thereby ensuring that all data can be encoded.

With reference to the third aspect or the first possible implementation manner of the fourth aspect, in a second possible implementation manner of the third aspect or the fourth aspect, the information data in the first cache includes 512 rows × 478 columns, the check data in the first cache includes 512 rows × 32 columns, the second-level encoding includes hamming (128,119) encoding, and d ═ 85+119 × i, i is a non-negative integer.

With reference to the third aspect or the fourth aspect, in a third possible implementation manner of the third aspect or the fourth aspect, the first-level coding includes ladder coding, and the second-level coding includes hamming (128,119) coding; the information data in the first cache comprises 512 rows × 478 columns, and the check data in the first cache comprises 512 rows × 32 columns.

With reference to the third aspect or the third possible implementation manner of the fourth aspect, in a fourth possible implementation manner of the third aspect or the fourth aspect, before receiving the information data at the current time, the method further includes: performing 32-bit CRC coding on the 244664-bit first sequence to obtain a 244696-bit second sequence; inserting a 6-bit padding sequence at the end of the second sequence to obtain a third sequence of 244702 bits, and inserting a 34-bit all-0 sequence at the end of the third sequence to obtain 244736 bits of the information data;

after obtaining the first codeword, the method further comprises: deleting data of the 34-bit all-0 sequence included in the received 261120-bit first code word to obtain a fourth sequence with the length of 261086;

the performing second-level coding on the first codeword specifically includes: inserting a 714-bit preset sequence at the tail of a fifth sequence of 1305430 bits to obtain a sixth sequence with the length of 1306144 bits, wherein the fifth sequence comprises five continuous fourth sequences; hamming (128,119) encoding the sixth sequence.

With reference to the third aspect or the third possible implementation manner of the fourth aspect, in a fifth possible implementation manner of the third aspect or the fourth aspect, before receiving the information data at the current time, the method further includes: performing 32-bit CRC coding on the 244664-bit first sequence to obtain a 244696-bit second sequence; inserting a 6-bit padding sequence at the end of the second sequence to obtain a third sequence of 244702 bits, and inserting a 34-bit all-0 sequence at the end of the third sequence to obtain 244736 bits of the information data;

the performing second-level coding on the first codeword specifically includes: inserting a 544-bit preset sequence at the tail of a fourth sequence of 1305600 bits to obtain a fifth sequence of 1306144 bits, wherein the fourth sequence comprises five consecutive first code words of 261120 bits; hamming (128,119) encoding the fifth sequence.

According to the embodiment of the application, data interleaving is performed according to a preset mode, so that the effect of reducing the error code correlation between two different code words can be achieved, the coding complexity is low, and the implementation is easy.

Drawings

Fig. 1 is a block diagram of a communication system;

fig. 2 is a flowchart of a concatenated coding method according to an embodiment of the present application;

fig. 3 is a schematic diagram of an interleaving manner according to another embodiment of the present application;

fig. 4 is a schematic diagram of an interleaving manner according to another embodiment of the present application;

FIG. 5 is a flowchart of a method for concatenated coding according to another embodiment of the present application;

fig. 6 is a schematic diagram of an interleaving manner according to another embodiment of the present application;

fig. 7 is a schematic diagram of an interleaving manner according to another embodiment of the present application;

fig. 8 is a flowchart illustrating an implementation of a concatenated coding method according to another embodiment of the present application;

fig. 9 is a schematic diagram illustrating an arrangement of data in a first cache and a second cache according to another embodiment of the present application;

fig. 10 is a flowchart illustrating an implementation of a concatenated coding method according to another embodiment of the present application;

fig. 11 is a flowchart illustrating an implementation of a concatenated coding method according to another embodiment of the present application;

fig. 12 is a block diagram of a concatenated coding apparatus according to another embodiment of the present application;

fig. 13 is a block diagram of a concatenated coding apparatus according to another embodiment of the present application.

Fig. 14 is a block diagram of a concatenated coding apparatus according to another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

Fig. 1 shows a block diagram of a communication system, where at a transmitting end, a source provides a data stream to be transmitted; the encoder receives the data stream, encodes the data stream and sends the encoded data stream to the transmitter; the transmitter converts the coded data stream into an actual signal and sends the actual signal into a channel; at the receiving end, the receiver converts the received signal to obtain a data stream, and sends the data stream to a decoder for decoding, so as to recover the original data and send the original data to the information sink. Among them, the concatenated coding method provided in the present application is applied to the encoder shown in fig. 1, and is a very important ring in a communication system.

An embodiment of the present application provides a concatenated coding method, as shown in fig. 2, including:

201. receiving information data of the current moment;

specifically, the concatenated coding device includes a first buffer and a second buffer, where the information data at the current time is stored in the first buffer, and the data stored in the first buffer at the previous time is stored in the second buffer. Assuming that the current time is t, the information data received at the time t is stored in the first cache, and all the data stored in the first cache at the time t-1 is transferred to the second cache.

202. Performing first-level coding on the mth row of data in the first cache and the nth row of data in the second cache to obtain mth check data, and storing the mth check data in the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n;

specifically, assuming that the information data is 256 rows × 244 columns, and m is 3, and n is 1, the 3 rd row of data in the first buffer and the 1 st column of data in the second buffer together form 244+ 256-500 bit data, and the 500 bit data is subjected to (Bose-Chaudhuri-Hocquenghem, BCH) encoding to obtain a BCH codeword with a length of 510 bits, where the extra 10 bit information is the 3 rd parity data, and the 3 rd parity data is stored in the 3 rd row of the first buffer; by analogy, 256 check data with 10 bits are obtained and are respectively stored in 256 lines of the first cache, wherein the value of m corresponds to the unique value of n, and the corresponding relation is written in advance.

It is noted that the second cache stores all the data stored in the first cache at the previous time, that is, the second cache includes the information data and the check data stored in the first cache at the previous time, that is, the data in the second cache is 256 rows × 254 columns. At this time, the number of rows 256 of the data in the first buffer is greater than the number of columns 254 of the data in the second buffer, and the number of columns of the data in the second buffer is two columns less, then 2 additional columns of all-0 data are added to the data in the second buffer, and the number of columns in the second buffer is filled up, so that 256 10-bit check data can be obtained at the current time.

203. Interleaving data in the first cache according to a preset mode to obtain a first code word, wherein the preset mode is any one of the following four modes:

(1) w x r + k th of first codeword₁The data is the jth data in the first buffer₁Line kth₁The column values;

(2) w x r + k th of first codeword₁The data is the R-1-j in the first buffer memory₁Line kth₁The column values;

(3) w x r + k th of first codeword₁The data is the jth data in the first buffer₁Line W-1-k₁The column values;

(4) w x r + k th of first codeword₁The data is the R-1-j in the first buffer memory₁Line W-1-k₁The column values;

wherein W is the number of columns of data in the first buffer, R is the number of rows of data in the first buffer, W, R, R, k₁，j₁Is an integer, 0 ≦ R ≦ R-1, 0 ≦ k₁≦W-1，j₁＝(r+k₁)mod R；

Specifically, for example, in the first preset manner, if the data in the first buffer is 256 rows × 254 columns, i.e. W equals 254 and R equals 256, then R equals 0 and k equals 256₁When 0 is satisfied, (W × r + k)₁0), the 0 th data of the first code word is the value of the 0 th row and the 0 th column in the first buffer; when r is 0, k₁In the case of 1, the first codeThe 1 st data of the word is the numerical value of the 1 st line and the 1 st column in the first cache; when r is 0, k₁In the case of 2, the 2 nd data of the first codeword is the value of the 2 nd row and the 2 nd column in the first buffer; the preset mode is as shown in fig. 3, data on the line marked as 0 is read from left to right in sequence, data on the line marked as 1 is read again, and so on, the data in the first cache is interleaved according to the mode to obtain a first codeword. Similarly, taking the second preset manner as an example, when r is 0, k₁When 0 is satisfied, (W × r + k)₁0), the 0 th data of the first code word is the value of the 255 th row and the 0 th column in the first buffer; when r is 0, k₁In the case of 1, the 1 st data of the first codeword is the value in the 254 th row and 1 st column in the first buffer; when r is 0, k₁In the case of 2, the 2 nd data of the first codeword is the value of the 253 rd row and 2 nd column in the first buffer; at this time, the preset mode is as shown in fig. 4, and the data on the line marked as 0 is read from right to left, and then the data on the line marked as 1 is read, and so on. The third predetermined manner is similar to the second predetermined manner, except that: when the data on each connecting line with the mark in fig. 4 is read in sequence, the reading direction is from left to right; the fourth predetermined manner is similar to the first predetermined manner, except that: when the data on each marked line in fig. 3 is read sequentially, the reading direction is from right to left.

Optionally, interleaving data in the first buffer according to a preset manner to obtain a first codeword, which specifically includes: reading the data stored in the first cache by row or column; storing the read data into a third cache by rows or columns; and reading the data in the third cache according to a preset mode to obtain a first code word. This alternative is a variation of this embodiment of the present application, and the data in the first buffer is stored into a new buffer, that is, a third buffer, and the data in the third buffer is interleaved according to any one of the preset manners shown in step 203 in the third buffer to obtain the first codeword. It should be noted that, when the first buffer can be read out by row or column and then stored in the third buffer, one of the rows or columns may be selected optionally, and there are four combinations, which is not limited in this embodiment.

204. And performing second-level coding on the first code word to obtain a second code word, and sending out the second code word, wherein any two bits in the same row or the same column in the first cache are mapped into different second code words. Because of interleaving in the preset manner shown in step 203, adjacent bits in the first codeword cannot come from the same row or the same column in the first buffer, and further, data on the connection lines with the same labels in fig. 3 or fig. 4 are neither located in the same row nor the same column in the first buffer; any two data contained in the second codeword cannot come from the same row or column in the first buffer as long as the length of the information in the second codeword is less than the total number of data on the line with the same tag.

Optionally, performing second-level coding on the first codeword specifically includes: and inserting a preset sequence with the length of d bits into the tail part of the first code word to obtain a third code word with the length of s, and carrying out second-stage coding on the third code word, wherein s and d are positive integers, and s is a positive integer multiple of the information length of the second code word. In this embodiment, by filling a preset sequence with a certain length, the code length of the third codeword for the second-level encoding is an integer multiple of the information length of the second codeword, so as to ensure that all data can be encoded, where the preset sequence may be all 0, or may be in any other form.

Another embodiment of the present application provides a concatenated coding method, as shown in fig. 5, including:

501. receiving information data at the current moment, wherein the information data at the current moment are stored in a first cache, and data stored in the first cache at the previous moment are stored in a second cache;

502. and performing first-level coding on the mth row of data in the first cache and the nth row of data in the second cache to obtain mth check data, and storing the mth check data into the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n. The specific manner of the first-level encoding has already been described in the previous embodiment, and is not described herein again in this embodiment.

503. Interleaving information data in the 0 th column to the W-P-1 th column in the first cache according to a first preset mode to obtain an information sequence, wherein the first preset mode is any one of the following four modes:

(1) (W-P). times.r + k of information sequence₂The data is the jth data in the first buffer₂Line kth₂The column values;

(2) (W-P). times.r + k of information sequence₂The data is the R-1-j in the first buffer memory₂Line kth₂The column values;

(3) (W-P). times.r + k of information sequence₂The data is the jth data in the first buffer₂Line W-P-1-k₂The column values;

(4) (W-P). times.r + k of information sequence₂The data is the R-1-j in the first buffer memory₂Line W-P-1-k₂The column values;

wherein W is the number of columns of data in the first buffer, R is the number of rows of data in the first buffer, W, R, P, R, k₂，j₂Is an integer, 0 ≦ R ≦ R-1, 0 ≦ k₂≦W-P-1，j₂＝(r+k₂)mod(W-P)；

504. Interleaving the check data from the W-P column to the W-1 column in the first cache according to a second preset mode to obtain a check sequence, wherein the second preset mode is any one of the following four modes:

(1) the Pxr + k-th of the check sequence₃The data is the jth data in the first buffer₃Line kth₃Column + W-P values;

(2) the Pxr + k-th of the check sequence₃The data is the R-1-j in the first buffer memory₃Line kth₃+(W-P) The column values;

(3) the Pxr + k-th of the check sequence₃The data is the jth data in the first buffer₃Line W-1-k₃The column values;

wherein k is₃，j₃Is an integer, 0 ≦ k₃≦P-1，j₃＝(r+k₃)mod P；

505. And combining the information sequence and the check sequence to obtain a first code word.

Specifically, in

steps

503 and 504 of this embodiment, the information data and the check data are interleaved respectively, and then combined into the first codeword, so that the positions of the information data and the check data can be simply distinguished, and the systematic form of the first codeword is maintained. It should be noted that the first predetermined manner and the second predetermined manner are similar to the predetermined manner mentioned in the previous embodiment, and both ensure that the adjacent bits of the output sequence do not come from the same row or the same column of the first buffer; here, the first implementation is taken as an example for both the first preset mode and the second preset mode, and it is assumed that the data in the first buffer is 256 rows × 254 columns, the information data is 256 rows × 244 columns, and the check data is 256 rows × 10 columns, that is, W is 254, R is 256, and P is 10, and when R is 0, k is 0₂＝0，k₃If the value is 0, the 0 th data of the information sequence is the value in the 0 th row and the 0 th column in the first cache, and the 0 th data of the check sequence is the value in the 0 th row and the 244 th column in the first cache; when r is 0, k₂＝1，k₃In the case of 1, the 1 st data of the information sequence is the value in the 1 st row and the 1 st column in the first cache, and the 1 st data of the check sequence is the value in the 1 st row and the 245 th column in the first cache; when r is 0, k₁＝2，k₃In the case of 2, the 2 nd data of the information sequence is the value in the 2 nd row and the 2 nd column in the first cache, and the 2 nd data of the check sequence is the value in the 2 nd row and the 246 th column in the first cache; at this time, the first preset mode and the second preset mode are as shown in fig. 6, and the bits of the information data are stored in the first cache respectivelyAnd starting from the position for setting and storing the check data, sequentially reading the data on the connecting line marked as 0 from left to right, then reading the data on the connecting line marked as 1, and so on, respectively interleaving the information data and the check data in the first cache, and merging the information sequence and the check sequence obtained after interleaving to obtain the first code word.

Similarly, taking the second implementation manner as an example of the first preset manner and the second preset manner, when r is equal to 0, k is₂＝0，k₃If the value is 0, the 0 th data of the information sequence is the value of the 255 th row and the 0 th column in the first cache, and the 0 th data of the check sequence is the value of the 255 th row and the 244 th column in the first cache; when r is 0, k₂＝1，k₃In the case of 1, the 1 st data of the information sequence is the value in the 254 th row and the 1 st column in the first cache, and the 1 st data of the check sequence is the value in the 254 th row and the 243 st column in the first cache; when r is 0, k₂＝2，k₃In the case of 2, the 2 nd data of the information sequence is the value of the 253 rd row and the 2 nd column in the first buffer, and the 2 nd data of the check sequence is the value of the 253 rd row and the 242 nd column in the first buffer; at this time, as shown in fig. 7, the preset method sequentially reads the data on the line marked as 0 from right to left from the position where the information data is stored and the position where the check data is stored in the first buffer, and then reads the data on the line marked as 1, and so on. The third predetermined manner is similar to the second predetermined manner, except that: when the data on each connecting line with the mark in fig. 7 is read in sequence, the reading direction is from left to right; the fourth predetermined manner is similar to the first predetermined manner, except that: when the data on each of the marked lines in fig. 6 is read sequentially, the reading direction is from right to left.

It should be understood that the first preset mode and the second preset mode are four types, and when the first preset mode and the second preset mode are executed, the first preset mode and the second preset mode are not influenced, and 16 alternative modes are combined, for example, the schemes shown in fig. 6 and fig. 7 are two of the schemes. In addition, if the information data and the check data are respectively stored in a third cache and a fourth cache, and then the information data and the check data in the respective caches are respectively interleaved according to a first preset mode and a second preset mode, the information data occupy lines 0 to 255 and columns 0 to 243 of the third cache, and the check data occupy lines 0 to 255 and columns 0 to 9 of the fourth cache; at this time, since it is not necessary to interleave two types of data in the same buffer, the first preset mode and the second preset mode may be the same as the preset mode described in the previous embodiment, and the difference is only that: w and R are the number of columns and rows of data in the respective buffers, i.e. when interleaving the information data, W equals 244 and R equals 256; when interleaving the check data, W is 10, and R is 256. Further, no matter the information data and the check data are interleaved in the first buffer, or the information data and the check data are stored in a new buffer, and then interleaved, the interleaving manner of the information data and the interleaving manner of the check data do not need to correspond to each other, that is, when the first implementation manner is selected by the first preset manner, any one of the four implementation manners can be still selected by the second preset manner, and no limitation is imposed on each other, and vice versa.

Optionally, the data stored in the first cache may also be read in rows or columns first; storing the read data into a fifth cache by rows or columns; interweaving the information data in the fifth cache according to a first preset mode to obtain an information sequence; interleaving the check data in the fifth cache according to a second preset mode to obtain a check sequence; and combining the information sequence and the check sequence to obtain a first code word. This alternative also is a variation of this embodiment, and the data in the first buffer is stored in a fifth buffer, and the information data and the check data are interleaved in the fifth buffer according to a first preset manner and a second preset manner, and then combined to obtain the first codeword. At this time, the values of W and R are the column number and the row number of the data in the fifth buffer, respectively.

506. And carrying out second-level coding on the first code word to obtain a second code word, and sending out the second code word.

Optionally, performing second-level coding on the first codeword specifically includes: and inserting a preset sequence with the length of d bits into the tail part of the first code word to obtain a third code word with the length of s, and carrying out second-stage coding on the third code word, wherein s and d are positive integers, and s is a positive integer multiple of the information length of the second code word. In this embodiment, by filling a preset sequence with a certain length, the code length of the third codeword for the second-level encoding is an integral multiple of the information length of the second codeword, thereby ensuring that all data can be encoded.

The information data and the check data are respectively interleaved and then combined into the first code word, the positions of the information data and the check data can be simply distinguished from the first code word, the systematized form of the first code word is kept, and under the normal condition, the number of columns of the information data in the first cache is larger than the length of the code word of the second-level code, so that the error code correlation between two different code words can be reduced, and the coding performance is improved.

It should be understood that the present application provides four implementations of the preset mode, the first preset mode and the second preset mode, but the present application does not exclude other embodiments as long as it can be satisfied that any two data included in the second codeword do not come from the same row or the same column in the first cache, or that most data in the second codeword do not belong to the same row or the same column in the first cache. For example, based on the preset mode shown in fig. 3,4,6, and 7, the output positions of several bits are changed to change the connection lines with the same mark into a curve or a broken line or various irregular connection line forms; and still according to the preset modes shown in fig. 3,4,6, and 7, but the reading is random (the data on the line marked as 0 is read just before reading several bits, and then the line is changed to another line), or the reading is started from the line marked as b (b is a positive integer), or the reading is started from the middle of a certain line, etc., all can be used as possible implementations of the present application.

The following two specific examples are used to describe the embodiments of the present application in detail:

the first embodiment is as follows:

the first level encoding comprises ladder encoding, and the second level encoding comprises hamming (128,119) encoding; the information data includes 512 rows × 478 columns, and the check data includes 512 rows × 32 columns, and the basic block diagram thereof is shown in fig. 8. Assuming that the current time is t, the first buffer stores 512 rows × 478 columns of information data at t, the second buffer stores 512 rows × 510 columns of data stored at t-1, and the number of rows 512 of data in the first buffer is 2 greater than the number of columns 510 of data in the second buffer, so the data in the second buffer includes two extra columns of all-0 data, as shown in fig. 9. Then, according to a preset corresponding relation, carrying out BCH (1022,990) coding on any row of data in the first cache and the only column of data in the second cache together to obtain a BCH code word with the code length of 1022; assuming that the third row of data in the first buffer and the corresponding column in the second buffer are BCH-encoded, 32-bit check data in the BCH codeword is stored in the third row of the first buffer, and so on, the first buffer stores the information data and the check data at time t, and there are 512 rows × 510 columns in total.

And interleaving the data in the first buffer according to a preset mode to obtain a first code word, where the preset mode includes (taking the preset mode as an example of the first implementation mode):

the Lth data of the first code word is the kth line of the jth line in the first buffer₁Column number, where W is 510, is the number of columns of data in the first buffer, R is 512, is the number of rows of data in the first buffer, R, k₁J is an integer, 0 ≦ R ≦ R-1, 0 ≦ k₁≦W-1，j＝(r+k₁)mod R，L＝W×r+k₁. When r is 0, k₁When j is 0, L is 0, the 0 th data of the first codeword is the value of the 0 th row and the 0 th column in the first buffer; when r is 0, k₁When j is 1, L is 1, the 1 st data of the first codeword is the value of the 1 st row and the 1 st column in the first buffer; when r is 0, k₁When j equals 509 and L equals 509, the 509 th data of the first codeword is the 509 th row and 509 th column in the first buffer; further, when r is 1, k₁When j is equal to 1 and L is equal to 510, the 510 th data of the first codeword is the value of the 1 st row and 0 th column in the first buffer; when r is 1, k₁When j equals 1, L equals 511, the 511 th data of the first codeword is the 2 nd line in the first buffer1 column of values; the reading mode is shown in fig. 3, and the data on the connecting lines marked 0-511 are read from left to right in sequence.

In order to ensure that each bit in the first codeword is hamming (128,119) encoded, a preset sequence of 85+119 × i bits is added to the tail of the first codeword, the length of the first codeword is increased to 512 × 510+85+119 × i ═ 2195+ i) × 119, and after hamming (128,119) encoding, 2195+ i codewords can be obtained, where the preset sequence may be all 0 or in any other form, and i is a non-negative integer.

It should be understood that whether or not information data and check data are distinguished at the time of interleaving, the length of the resulting first codeword is 512 × 510 — 261120 bits. If the information data and the check data are not distinguished, every 510 bits of the first codeword come from the connecting line with the same label on fig. 3 or fig. 4, that is, every 510 bits are not located in the same row or the same column in the first buffer; if the information length of the second codeword is 119 bits less than 510 bits, any two data included in the second codeword cannot come from the same row or the same column in the first cache, so that the effect of reducing the error code correlation between two different codewords can be achieved, and the encoding complexity is low; if the information data and the check data are distinguished, each 478 bits of the information sequence come from the line with the same mark in fig. 3 or fig. 4, that is, each 478 bits are not located in the same row or the same column of the first buffer; every 32 bits of the check sequence come from the connecting line with the same mark on fig. 3 or fig. 4, that is, every 32 bits are not located in the same row or the same column in the first buffer; because the information sequence occupies a larger proportion in the first code word, the method can also play a role in reducing the error code correlation between two different code words; in addition, the information data and the check data are distinguished, the positions of the information data and the check data can be simply identified in the first code word, and the systematic form of the first code word is kept.

Example two:

the first level encoding comprises ladder encoding, and the second level encoding comprises hamming (128,119) encoding; the information data in the first cache includes 512 rows × 478 columns, and the check data in the first cache includes 512 rows × 32 columns, and the basic block diagram is shown in fig. 10. Before receiving the information data of the current time, the method further comprises:

performing 32-bit (Cyclic redundancy check, CRC) Cyclic redundancy check coding on the 244664-bit first sequence to obtain a 244696-bit second sequence; inserting a 6-bit padding sequence at the tail of the second sequence to obtain a third sequence of 244702 bits, where the 6-bit padding sequence may be in any form, such as a full 0 sequence, a full 1 sequence, and the like, and this embodiment is not limited; inserting a 34-bit all-0 sequence at the tail of the third sequence to obtain 244736-bit information data; the first-level encoding of the first embodiment is performed on the information data to obtain the first codeword with a length of 261120 bits, and the encoding method is described in detail in the first embodiment, which is not described herein again.

Deleting the 34-bit all-0 sequence included in the received first code word to obtain a fourth sequence with the length of 261086; the same operation is sequentially performed on the next four data streams with the length of 244664 bits, so that four fourth sequences with the length of 261086 are sequentially obtained, and the total five fourth sequences are combined into a fifth sequence with the length of 1305430.

Inserting a 714-bit preset sequence into the tail of the fifth sequence to obtain a sixth sequence with the length of 1306144 bits; the sixth sequence is hamming (128,119) encoded. The preset sequence may be all 0, or may be in any other form, which is not limited in this embodiment of the application.

Alternatively, without performing the step of deleting the data of the 34-bit all 0 sequence, after five first code words are obtained successively, the five first code words are combined to obtain a fourth sequence with a length of 1305600 bits; inserting a 544-bit preset sequence at the tail of the fourth sequence to obtain a fifth sequence with the length of 1306144 bits; the fifth sequence is hamming (128,119) encoded, and the basic block diagram is shown in fig. 11.

Another embodiment of the present application provides a concatenated coding apparatus, as shown in fig. 12, including: a first stage code interleaver 1210 and a second stage encoder 1220,

the first-level code interleaver 1210 includes a first buffer and a second buffer, where the first buffer stores information data at a current time, and the second buffer stores data stored in the first buffer at a previous time; the first-stage code interleaver 1210 is configured to perform first-stage coding on mth row of data in the first buffer and nth row of data in the second buffer to obtain mth check data, and store the mth check data in the mth row of the first buffer, where the first buffer stores information data and check data at a current time, m and n are integers, and a value of m corresponds to a unique value of n.

Specifically, assuming that the information data is 512 rows × 478 columns, and m is 3, and n is 1, the 3 rd row of data in the first buffer and the 1 st column of data in the second buffer together form 512+ 478-990 bit data, and BCH (1022,990) encoding is performed on the 990 bit data to obtain a BCH codeword with a length of 1022 bits, where the extra 32-bit information is the 3 rd parity data, and the 3 rd parity data is stored in the 3 rd row of the first buffer; by analogy, 512 32-bit check data are obtained and are respectively stored in 512 lines of the first cache, wherein the value of m corresponds to the unique value of n, and the corresponding relation is written in advance.

It is noted that the second cache stores all the data stored in the first cache at the previous time, that is, the second cache includes the information data and the check data stored in the first cache at the previous time, that is, the data in the second cache is 512 rows × 510 columns. At this time, the row number 512 of the data in the first cache is greater than the column number 510 of the data in the second cache, and the number of the data columns in the second cache is two columns less, then 2 additional columns of all-0 data are added to the data in the second cache, and the columns in the second cache are filled up, so that 512 32-bit check data can be obtained at the current time.

The first stage code interleaver 1210 interleaves the data in the first buffer according to a preset mode to obtain a first codeword, where the preset mode is any one of the following four modes:

(1) w x r + k th of first codeword₁The data is the jth data in the first buffer₁Line kth₁Of columnsA numerical value;

Optionally, the second-stage code interleaver 1210 may further interleave the information data and the check data respectively to obtain an information sequence and a check sequence, and then combine the two sequences to obtain the first codeword. Specifically, the information data in the 0 th column to the W-P-1 th column in the first buffer 1211 is interleaved according to a first preset mode to obtain an information sequence, where the first preset mode is any one of the following four modes:

Interleaving the check data in the W-P column to the W-1 column in the first buffer 1211 according to a second preset mode to obtain a check sequence, wherein the second preset mode is any one of the following four modes:

wherein k is₃，j₃Is an integer, 0 ≦ k₃≦P-1，j₃＝(r+k₃) mod P. The alternative scheme interleaves the information data and the check data respectively, and then merges the information data and the check data into the first code word, so that the positions of the information data and the check data can be simply distinguished in the first code word, and the systematic form of the first code word is maintained.

And the second-stage encoder 1220 is configured to perform second-stage encoding on the first codeword to obtain a second codeword, and send the second codeword.

Optionally, the second-stage encoder 1220 includes an inserting module 1221 and an encoding module 1222, where the inserting module 1221 is configured to insert a preset sequence with a length of d bits at the tail of the first codeword, to obtain a third codeword with a length of s, where s and d are both positive integers, and s is a positive integer multiple of the information length of the second codeword; and the encoding module 1222 is configured to perform second-level encoding on the third codeword to obtain a second codeword, and send the second codeword. In this embodiment, by filling a preset sequence with a certain length, the code length of the third codeword for the second-level coding is an integer multiple of the information length of the second codeword, so as to ensure that all data can be coded, where the preset sequence may be all 0, or may be in any other form, and this embodiment of the present application is not limited.

Specifically, the information data in the first buffer 1211 includes 512 rows × 478 columns, the check data in the first buffer 1211 includes 512 rows × 32 columns, and when the second-stage encoder 1220 performs hamming (128,119), d is 85+119 × i, and i is a non-negative integer.

Optionally, the first level encoding comprises ladder encoding and the second level encoding comprises hamming (128,119) encoding; the information data in the first buffer 1211 includes 512 rows × 478 columns, and the check data in the first buffer 1212 includes 512 rows × 32 columns. The block diagram of the concatenated coding device is shown in fig. 13, and the concatenated coding device includes a first-stage code interleaver 1310, a second-stage encoder 1320, a CRC encoder 1330, and a first insertion module 1340;

the CRC encoder 1330 is configured to perform 32-bit CRC encoding on the 244664-bit first sequence to obtain a second sequence with a length of 244696 bits; a first inserting module 1340, configured to insert a 6-bit padding sequence at the end of the second sequence to obtain a third sequence of 244702 bits, and insert a 34-bit all-0 sequence at the end of the third sequence to obtain 244736 bits of information data; transmitting the information data to a first stage code interleaver 1310;

after the first-stage interleaver 1310 performs the code interleaving, the first codeword with length of 512 × 510 ═ 261120 bits is obtained, and the performing process is described in detail in the foregoing embodiments, and is not described again in this embodiment.

Optionally, the concatenated coding apparatus further includes a deleting module 1350, configured to delete the data of the 34-bit all 0 sequence included in the first codeword, so as to obtain a fourth sequence with a length of 261086; the second level encoder 1320 includes a second inserting module 1321 and an encoding module 1322, where the second inserting module 1321 is configured to insert a predetermined sequence of 714 bits at the end of a fifth sequence of 1305430 bits to obtain a sixth sequence with a length of 1306144 bits, where the fifth sequence includes five consecutive fourth sequences; the encoding module 1322 performs hamming (128,119) encoding on the sixth sequence to obtain the second codeword, and sends it out.

Optionally, the concatenated coding apparatus may further include an deleting module, in which case, the inserting module 1321 is configured to insert a 544-bit preset sequence at the tail of an 1305600-bit fourth sequence to obtain a fifth sequence with a length of 1306144 bits, where the fourth sequence includes five consecutive first codewords with a length of 261120; the encoding module 1322 performs hamming (128,119) encoding on the fifth sequence to obtain a second codeword, and sends out the second codeword.

It should be noted that the added preset sequence may be a sequence of all 0 s, or may be in any other form, and this embodiment is not limited herein.

Another embodiment of the present application provides a concatenated coding apparatus 1400, as shown in fig. 14, including: an input interface 1401, a processor 1402, and an output interface 1403; the processor 1402 is configured to receive the information data through the input interface 1401, send the second codeword through the output interface 1403, and implement the steps and functions implemented by the concatenated coding apparatus 1400 in the above embodiments, which are not described herein again.

The present application provides a computer-readable storage medium or a computer program product for storing a computer program for executing the encoding method involved in the above method embodiments.

It will be appreciated that fig. 14 only shows a simplified design of the encoding device. In practical applications, the encoding apparatus may include any number of interfaces, processors, and the like, and all terminals that can implement the embodiments of the present application are within the scope of the embodiments of the present application.

It is further understood that the processor referred to in the embodiments of the present application may be a Central Processing Unit (CPU), and may also be other general purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), Field Programmable Gate Arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, and so on. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

It should be appreciated that reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In various embodiments of the present invention, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may also be an electric, mechanical or other form of connection.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

In short, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A concatenated coding apparatus, comprising: a first-stage code interleaver and a second-stage encoder,

the first-level code interleaver comprises a first buffer and a second buffer, wherein the first buffer stores information data at the current moment, and the second buffer stores data stored in the first buffer at the previous moment;

the first-stage code interleaver is used for performing first-stage coding on mth row data in the first cache and nth row data in the second cache to obtain mth check data, and storing the mth check data in the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n;

the first-stage code interleaver interleaves the information data and the check data in the first buffer according to a preset mode to obtain a first codeword, where the preset mode is any one of the following four modes:

2. The concatenated encoding apparatus of claim 1, wherein the second-stage encoder comprises an insertion module and an encoding module,

the inserting module is used for inserting a preset sequence with the length of d bits into the tail of the first code word to obtain a third code word with the length of s, wherein s and d are positive integers, and s is a positive integer multiple of the information length of the second code word;

and the coding module is used for carrying out second-level coding on the third code word to obtain a second code word and sending the second code word out.

3. The concatenated coding apparatus of claim 2, wherein the information data in the first buffer comprises 512 rows by 478 columns, the check data in the first buffer comprises 512 rows by 32 columns, the second-level coding comprises hamming (128,119) coding, and d is 85+119 x i, i is a non-negative integer.

4. The concatenated coding apparatus of claim 1, wherein the first level coding comprises a ladder coding, and the second level coding comprises a hamming (128,119) coding; the information data in the first cache comprises 512 rows × 478 columns, and the check data in the first cache comprises 512 rows × 32 columns.

5. The concatenated encoding apparatus of claim 4, further comprising a CRC encoder, a first insertion module and a deletion module,

the CRC encoder is used for carrying out 32-bit CRC encoding on the 244664-bit first sequence to obtain a second sequence with the length of 244696 bits;

the first inserting module is configured to insert a 6-bit padding sequence at the end of the second sequence to obtain a third sequence of 244702 bits, and insert a 34-bit all-0 sequence at the end of the third sequence to obtain 244736 bits of the information data; sending the information data to the first-stage code interleaver;

the deleting module is configured to delete the data of the 34-bit all-0 sequence included in the received 261120-bit first codeword, so as to obtain a fourth sequence with a length of 261086;

the second level encoder includes a second insertion module and an encoding module,

the second inserting module is configured to insert a 714-bit preset sequence at the tail of a fifth sequence of 1305430 bits to obtain a sixth sequence of 1306144 bits in length, where the fifth sequence includes five consecutive fourth sequences;

the encoding module is configured to hamming (128,119) encode the sixth sequence.

6. The concatenated encoding apparatus of claim 4, further comprising a CRC encoder and a first insertion module,

the second inserting module is configured to insert a 544-bit preset sequence at the tail of an 1305600-bit fourth sequence to obtain a 1306144-bit fifth sequence, where the fourth sequence includes five consecutive first codewords of length 261120;

the encoding module is configured to hamming (128,119) encode the fifth sequence.

7. A concatenated coding apparatus, comprising: a first-stage code interleaver and a second-stage encoder,

wherein k is₃，j₃Is an integer, 0 ≦ k₃≦P-1，j₃＝(r+k₃)mod P；

Combining the information sequence and the check sequence to obtain a first code word;

8. The concatenated encoding apparatus of claim 7, wherein the second stage encoder comprises an insertion module and an encoding module,

9. The concatenated coding apparatus of claim 8, wherein the information data in the first buffer comprises 512 rows by 478 columns, the check data in the first buffer comprises 512 rows by 32 columns, the second-level coding comprises hamming (128,119) coding, and d is 85+119 x i, i is a non-negative integer.

10. The concatenated coding apparatus of claim 7, wherein the first level coding comprises a ladder coding, and the second level coding comprises a hamming (128,119) coding; the information data in the first cache comprises 512 rows × 478 columns, and the check data in the first cache comprises 512 rows × 32 columns.

11. The concatenated encoding apparatus of claim 10, further comprising a CRC encoder, a first insertion module and a deletion module,

12. The concatenated encoding apparatus of claim 10, further comprising a CRC encoder and a first insertion module,

13. A method of concatenated coding, comprising:

receiving information data of the current moment, wherein the information data of the current moment is stored in a first cache, and data stored in the first cache at the previous moment is stored in a second cache;

performing first-level coding on the mth row of data in the first cache and the nth row of data in the second cache to obtain mth check data, and storing the mth check data in the mth row of the first cache, wherein m and n are integers, and the value of m corresponds to the unique value of n;

interleaving the information data and the check data in the first cache according to a preset mode to obtain a first code word, wherein the preset mode is any one of the following four modes:

14. The concatenated coding method of claim 13, wherein the second-level coding of the first codeword specifically comprises:

and inserting a preset sequence with the length of d bits into the tail of the first code word to obtain a third code word with the length of s, and performing second-level coding on the third code word, wherein s and d are positive integers, and s is a positive integer multiple of the information length of the second code word.

15. The concatenated coding method of claim 14, wherein the information data in the first buffer comprises 512 rows by 478 columns, the check data in the first buffer comprises 512 rows by 32 columns, the second-level coding comprises hamming (128,119) coding, and d is 85+119 x i, i is a non-negative integer.

16. The concatenated coding method of claim 13, wherein the first level coding comprises ladder coding, and the second level coding comprises hamming (128,119) coding; the information data in the first cache comprises 512 rows × 478 columns, and the check data in the first cache comprises 512 rows × 32 columns.

17. The concatenated coding method of claim 16,

before receiving the information data of the current time, the method further comprises:

performing 32-bit CRC coding on the 244664-bit first sequence to obtain a 244696-bit second sequence;

inserting a 6-bit padding sequence at the end of the second sequence to obtain a third sequence of 244702 bits, and inserting a 34-bit all-0 sequence at the end of the third sequence to obtain 244736 bits of the information data;

after obtaining the first codeword, the method further comprises:

deleting data of the 34-bit all-0 sequence included in the received 261120-bit first code word to obtain a fourth sequence with the length of 261086;

the performing second-level coding on the first codeword specifically includes:

inserting a 714-bit preset sequence at the tail of a fifth sequence of 1305430 bits to obtain a sixth sequence with the length of 1306144 bits, wherein the fifth sequence comprises five continuous fourth sequences;

hamming (128,119) encoding the sixth sequence.

18. The concatenated coding method of claim 16,

the performing second-level coding on the first codeword specifically includes:

inserting a 544-bit preset sequence at the tail of a fourth sequence of 1305600 bits to obtain a fifth sequence of 1306144 bits, wherein the fourth sequence comprises five consecutive first code words of 261120 bits;

hamming (128,119) encoding the fifth sequence.

19. A method of concatenated coding, comprising:

wherein k is₃，j₃Is an integer, 0 ≦ k₃≦P-1，j₃＝(r+k₃)mod P；

20. The concatenated coding method of claim 19, wherein the second-level coding of the first codeword comprises:

21. The concatenated coding method of claim 20, wherein the information data in the first buffer comprises 512 rows by 478 columns, the check data in the first buffer comprises 512 rows by 32 columns, the second-level coding comprises hamming (128,119) coding, and d is 85+119 x i, i is a non-negative integer.

22. The concatenated coding method of claim 19, wherein the first level coding comprises ladder coding, and the second level coding comprises hamming (128,119) coding; the information data in the first cache comprises 512 rows × 478 columns, and the check data in the first cache comprises 512 rows × 32 columns.

23. The concatenated coding method of claim 22,

after obtaining the first codeword, the method further comprises:

the performing second-level coding on the first codeword specifically includes:

hamming (128,119) encoding the sixth sequence.

24. The concatenated coding method of claim 22,

the performing second-level coding on the first codeword specifically includes:

hamming (128,119) encoding the fifth sequence.