CN110032524A - Storage system and its operating method - Google Patents

Storage system and its operating method Download PDF

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Publication number
CN110032524A
CN110032524A CN201811522794.2A CN201811522794A CN110032524A CN 110032524 A CN110032524 A CN 110032524A CN 201811522794 A CN201811522794 A CN 201811522794A CN 110032524 A CN110032524 A CN 110032524A
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China
Prior art keywords
speed buffering
data
queue
controller
memory device
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Granted
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CN201811522794.2A
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Chinese (zh)
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CN110032524B (en
Inventor
郑范*
郑范䧒
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

The present invention relates to a kind of storage system, the storage systems can include: non-volatile memory device, including memory cell array and the page buffer for being connected to memory cell array；Controller, it is configured to connect with non-volatile memory device interface, wherein controller will be moved to speed buffering queue from command queue about the descriptor of speed buffering order, and the descriptor for being moved to speed buffering queue is selectively moved to response queue, wherein the speed buffering order is transferred to non-volatile memory device.

Description

Storage system and its operating method
Cross reference to related applications
This application claims submitted on December 14th, 2017 to Korean Intellectual Property Office application No. is 10-2017- 0172063 Korean application and submitted on October 2nd, 2018 application No. is the Korean application of 10-2018-0117381 Priority, entire contents are incorporated herein by reference.
Technical field
Each embodiment of the invention relates in general to a kind of storage system.Particularly, embodiment is related to a kind of including non- The storage system and its operating method of volatile memory devices.
Background technique
Storage system can be configured in response to the write request from external device (ED), what storage was provided from external device (ED) Data.Moreover, storage system can be configured to be supplied to the data of storage in response to the read requests from external device (ED) External device (ED).External device (ED) as the electronic device for being capable of handling data may include computer, digital camera or mobile phone. Storage system can be operated by being built in external device (ED), or can be by being manufactured and being coupled in the form of separable It is operated to external device (ED).
Because mechanical driving member is not present, the storage system including memory device provides such as excellent The advantages of stability and durability, high message reference speed and low-power consumption.Have the advantages that this storage system includes general Universal serial bus (USB) memory device, the storage card with various interfaces, general flash storage (UFS) device and solid-state driving Device (SSD).
Summary of the invention
Each embodiment is related to a kind of storage system and its operating method, and wherein controller can accurately determine execution The result of cache operations.
In embodiment, storage system can include: non-volatile memory device, including memory cell array and connection It is connected to the page buffer of memory cell array；And controller, it is configured to connect with non-volatile memory device interface It connects, wherein controller will be moved to speed buffering queue from command queue about the descriptor of speed buffering order, and selective The descriptor for being moved to speed buffering queue is moved to response queue by ground, and wherein the speed buffering order is transferred to non-easy The property lost memory device.
In embodiment, the method for storage system is operated can include: will fill to nonvolatile memory by controller The descriptor for the cache operations set is stored in command queue；Descriptor, which is based on, by controller generates speed buffering life It enables, and speed buffering order is transferred to non-volatile memory device；It is slow that high speed is based on by non-volatile memory device Punching order executes cache operations；The state of the result including cache operations is believed by non-volatile memory device Breath is transferred to controller；When receiving status information from non-volatile memory device, controller is by descriptor from order team Column are moved to speed buffering queue.
In embodiment, storage system can include: memory device is configured to execute cache operations, at least Including the subsequent sub-operation according to subsequent speed buffering descriptor by data buffering into page buffer；And controller, quilt It is configured to generate subsequent speed buffering descriptor, and even if also at least delays in processing in the success of previous cache operations Rush data before the success of preceding sub-operation, it is ensured that the subsequent speed buffering descriptor of previous cache operations, in preceding sub- behaviour It is included in subsequent cache operation.
Detailed description of the invention
Fig. 1 is the block diagram for showing storage system according to an embodiment of the present disclosure.
Fig. 2 is the block diagram of the configuration of the controller of Fig. 1.
Fig. 3 is to show that the first speed buffering programming description symbol is moved to height when executing the first speed buffering programming operation The diagram of the process of fast buffering queue.
Fig. 4 is to show that the first speed buffering programming description symbol is moved to sound when executing the second speed buffering programming operation Answer the diagram of the process of queue.
Fig. 5 is to show that the first speed buffering reading descriptor is moved to height when executing the first speed buffering read operation The diagram of the process of fast buffering queue.
Fig. 6 is to show that the first speed buffering reading descriptor is moved to sound when executing the second speed buffering read operation Answer the diagram of the process of queue.
Fig. 7 to Figure 11 B is the flow chart for showing the method for operation storage system according to an embodiment of the present disclosure.
Figure 12 is to show showing for the data processing system according to an embodiment of the present disclosure including solid state drive (SSD) Figure.
Figure 13 and Figure 14 be show it is according to an embodiment of the present disclosure each include storage system data processing The diagram of system.
Figure 15 is the diagram for showing the network system according to an embodiment of the present disclosure including storage system.
Figure 16 is that show according to an embodiment of the present disclosure include the non-volatile memory device in storage system Block diagram.
Specific embodiment
In the present invention, after following exemplary embodiment is read in conjunction with the figure, advantage, feature and the method for realizing it It will become obvious.However, the present invention can embody in different forms, and should not be construed as limited to described in this paper Embodiment.On the contrary, providing these embodiments to describe the present invention in detail, reaching those skilled in the art in the invention can Easily implement the degree of technical concept of the invention.It is noted that the reference of " embodiment " be not necessarily mean that only for One embodiment, and to the different with reference to not necessarily for identical embodiment of " embodiment ".
It will be appreciated that the embodiment of the present invention is not limited to details shown in the drawings, the drawings are not necessarily drawn to scale, In some cases, it can be possible to exaggerate ratio more clearly to describe certain features of the invention.Although having used specific term, It is understood that term as used herein is only used for description specific embodiment, the range being not intended to limit the invention.
As used herein, term "and/or" includes any one of one or more relevant listed items and owns Combination.It will be appreciated that it can be straight when element is referred to as " above ", " being connected to " or " being attached to " another element It connects on other elements, be connected to or coupled to other elements, or intermediary element may be present.As used herein, unless up and down Text is expressly stated otherwise, and otherwise singular is also intended to including plural form.It will be further appreciated that when in the present specification When using term " includes " and/or "comprising", indicate that there are feature, step, operation and/or the elements of at least one statement, but One or more of the other feature, step, operation and/or its element are not precluded the presence or addition of.
Hereinafter, it will be described in detail with reference to the accompanying drawings exemplary embodiment.
Fig. 1 is the block diagram for showing storage system 100 according to an embodiment of the present disclosure, and Fig. 2 is the control for being shown specifically Fig. 1 The block diagram of the configuration of device 200 processed.
Storage system 100 can be stored to the data by host apparatus (not shown) access such as below: mobile phone, MP3 Player, laptop computer, desktop computer, game machine, TV, vehicle-mounted information and entertainment system etc..
According to the host interface for indicating the transport protocol for host apparatus, storage system 100 can be manufactured into various Any one of storage device of type.For example, storage system 100 can be configured to various storage devices such as below Any one of: solid state drive (SSD), the multimedia card of MMC, eMMC, RS-MMC and miniature-MMC form, SD, mini- The safe digital card of SD and miniature-SD form, universal serial bus (USB) storage device, general flash store (UFS) device, Personal Computer Memory Card International Association (PCMCIA) card-type storage device, peripheral component interconnection (PCI) card-type storage device are high Fast PCI (PCI-E) card-type storage device, standard flash memory (CF) card, smart media card, memory stick etc..
Storage system 100 can be manufactured into any one of various encapsulated types.For example, storage system 100 can It is manufactured into any one of various encapsulated types such as below: stacked package (POP), system in package (SIP), on piece System (SOC), multi-chip package (MCP), chip on board encapsulation (COB), wafer scale manufacture encapsulation are (WFP) and crystal circular piled It encapsulates (WSP).
Referring to Fig.1, storage system 100 may include controller 200 and non-volatile memory device 300.Reference Fig. 2, Controller 200 may include Memory Controller 210, random access memory (RAM) 220, host interface 230 and processor 240.
Memory Controller 210 can control non-volatile memory device 300 according to the control of processor 240.Storage Device controller 210 is also referred to as memory interface.Memory Controller 210 can supply control signals to non-volatile memories Device device 300.Control signal may include order, address and the operating control signal for controlling non-volatile memory device 300.It deposits Memory controller 210 can serve data to non-volatile memory device 300 or receive from non-volatile memory device 300 Data.
Memory Controller 210 may include command queue 211, speed buffering queue 212 and response queue 213.
Such as height of speed buffering programming operation or speed buffering read operation can be performed in non-volatile memory device 300 Fast buffer operation.
Speed buffering programming operation can include: page buffer will be stored in by previous speed buffering programming operation Past data in 320 is programmed into the operation of memory cell array 310 and follow-up data is stored in page buffer 320 In operation, wherein follow-up data is programmed into memory cell array 310 after past data.It can be performed simultaneously elder generation Preceding data are programmed into the operation of memory cell array 310 and follow-up data are stored in the operation in page buffer 320.It is non- Volatile memory devices 300 can will program data into the behaviour of memory cell array 310 by speed buffering programming operation Time needed for making minimizes.
Speed buffering read operation can include: by previous data transfer to the operation of Memory Controller 210, wherein previously Data are read and stored in page buffer 320 by previous speed buffering read operation from memory cell array 310 In；And the behaviour in page buffer 320 is stored in from reading follow-up data in memory cell array 310 and by follow-up data Make, wherein follow-up data is transferred in Memory Controller 210 after past data.It can be performed simultaneously and pass past data It defeated operation to Memory Controller 210 and reads follow-up data and stores it in the operation in page buffer 320.It is non-easy The property lost memory device 300 can will read the data being stored in memory cell array 310 by speed buffering read operation Operation needed for the time minimize.
In the present embodiment, the first to the n-th information (hereinafter referred to as " descriptor ") can be description memory control A kind of order of work for the work that device 210 is handled, to control non-volatile memory device 300.Descriptor can Including about to be stored in the data in non-volatile memory device 300 information, indicate data will be in non-volatile memories The address information of the storage location stored in device device 300 and indicate that data to be read are filled in nonvolatile memory Set the address information of the storage location stored in 300.However, the present embodiment is without being limited thereto, descriptor may include non-volatile Various information needed for the operation of property memory device 300.
In order to complete single speed buffering programming operation, it may be necessary to subsequent speed buffering program command and slow in preceding high speed Program command is rushed, wherein the data that are previously programmed that subsequent speed buffering program command is used to buffer are programmed into memory cell battle array In column 310 and by later programmed data buffering into page buffer 320, being used in preceding speed buffering program command will be previous Programming data is buffered in page buffer 320.In order to complete single speed buffering read operation, it may be necessary to which subsequent high speed is slow It rushes reading order and in preceding speed buffering reading order, what wherein subsequent cache reading order was used to buffer is previously read Data, which are transferred to Memory Controller 210 and subsequent reads access evidence is read into the page from memory cell array 310, to be delayed It rushes in device 320, is used to previous read data reading into the page from memory cell array 310 in preceding speed buffering reading order In buffer 320.
It can correspond respectively to compile in preceding speed buffering in preceding speed buffering program command and subsequent speed buffering program command Journey descriptor and subsequent speed buffering programming description symbol.Preceding speed buffering reading order and subsequent speed buffering reading order can It corresponds respectively to read descriptor in preceding speed buffering and subsequent speed buffering reads descriptor.
Descriptor can be generated by the flash translation layer (FTL) (FTL) of all operationss of control storage system 100, and be transferred to Memory Controller 210.Memory Controller 210 can will be stored in command queue 211 from the descriptor that FTL is provided, and Descriptor based on storage, which generates, will be supplied to the order of non-volatile memory device 300.
Non-volatile memory device 300 can be according to the command-execution operation provided from Memory Controller 210, and incites somebody to action Status information including operating result is transferred to Memory Controller 210.Operating result may include the information for indicating to complete operation With the information for indicating that operation passes through or fails.Based on the status information provided from non-volatile memory device 300, memory control Corresponding descriptor can be moved to response queue 213 and the deletion pair from command queue 211 from command queue 211 by device 210 processed The descriptor answered, or descriptor only is deleted from command queue 211, without corresponding descriptor is moved to response queue 213。
For example, Memory Controller 210 can be from command queue when status information, which includes, to be indicated to operate the information passed through Descriptor is deleted in 211, without corresponding descriptor is moved to response queue 213 from command queue 211.When status information packet When including the information for indicating operation failure, corresponding descriptor can be moved to response from command queue 211 by Memory Controller 210 Then corresponding descriptor is deleted in queue 213 from command queue 211.Because being stored in the descriptor table in response queue 213 Show the operation of failure, so processor 240 can will be used for the operation of failure based on the descriptor being stored in response queue 213 Descriptor is re-transmitted to Memory Controller 210, and Memory Controller 210 can will be opposite with the descriptor transmitted again The order answered is re-supplied to non-volatile memory device 300.
For example, corresponding subsequent high speed can be deleted from command queue 211 when the success of single speed buffering programming operation Buffer programming description symbol.Moreover, when the failure of single speed buffering programming operation, corresponding subsequent speed buffering programming description symbol It can be moved in response queue 213, and can be deleted from command queue 211.For example, when single speed buffering read operation at When function, corresponding subsequent speed buffering can be deleted from command queue 211 and reads descriptor.Moreover, when single speed buffering is read When extract operation fails, corresponding subsequent speed buffering reads descriptor and can be moved in response queue 213, and can be from order team It is deleted in column 211.
As described above, the data for being programmed into memory cell array 310 during speed buffering programming operation can indicate logical The data in page buffer 320 are stored in after the speed buffering programming operation previously executed.It is stored when storing data in When programming operation in device cell array 310 fails, status information can be transferred to memory by non-volatile memory device 300 Controller 210, the status information include the place in the order (for example, speed buffering program command) for the programming operation of failure Reason failure, and descriptor can be moved to response queue 213 from command queue 211 by Memory Controller 210, and the descriptor is same It is associated with from the corresponding order of the received status information of non-volatile memory device 300.
Therefore, can by with the page buffer 320 that is used to for following data being stored in non-volatile memory device 300 In the associated descriptor of order be moved to response queue 213: the data expression storage will be programmed into next one The data of device cell array 310, rather than will delay with the page for being used to for following data being stored in non-volatile memory device 300 The associated descriptor of the order rushed in device 320 is moved to response queue 213: data expression fails to be stored in memory list Data in element array 310.
In addition, being transferred to Memory Controller from non-volatile memory device 300 during speed buffering read operation 210 data can indicate to be read and stored in by the speed buffering read operation previously executed from memory cell array 310 Data in page buffer 320.
Memory Controller 210 can be decoded to from the received data of non-volatile memory device 300.Decoding operate It may include the mistake detected include in data and the mistake that correction detects.For the operation, Memory Controller 210 can be wrapped Error-correcting code (ECC) circuit (not shown) is included, for solving to from the received data of non-volatile memory device 300 Code.
When to failing from the decoding of the received data of non-volatile memory device 300, Memory Controller 210 can be incited somebody to action Descriptor is moved to response queue 213 from command queue 211, and the descriptor is the same as order corresponding with speed buffering read operation It is associated, wherein corresponding data (data of decoding failure) are transmitted by speed buffering read operation.
Therefore, can by be used to read the data for indicating will to transmit in next one from memory cell array 310 Data are simultaneously moved to response queue 213 for the associated descriptor of order that data are stored in page buffer 320 is read, and It is non-by be used for from the memory cell array 310 of non-volatile memory device 300 read decoding failure data and will It reads the associated descriptor of order that data are stored in page buffer 320 and is moved to response queue 213.
In the present embodiment, controller 200 can further comprise speed buffering queue 212, by with the order that handles completely Associated descriptor is moved to speed buffering queue 212 from command queue 211, and selects according to whether order can not be handled The descriptor being stored in speed buffering queue 212 is moved to selecting property response queue 213.
Therefore, when speed buffering programming operation or speed buffering read operation occurring failing, can will be used to program The data of failure are stored in order in page buffer 320 or for reading failure from memory cell array 310 Data are simultaneously correctly stored in response queue for the associated descriptor of order that data are stored in page buffer 320 is read In 213, rather than by with the order that is used to for the data being stored in page buffer 320 being programmed into memory cell array 310 Or the associated descriptor of order for the data being stored in page buffer 320 to be transferred to controller 200 is stored in In response queue 213.The operation will be described in detail referring to the Fig. 3 to Fig. 6 that will be described below.
RAM 220 may include dynamic ram (DRAM) or static state RAM (SRAM).RAM220 can be stored to be driven by processor 240 Dynamic firmware FW.In addition, RAM 220 can data needed for storage driving firmware FW, such as metadata.That is, RAM 220 The working storage that can be used as processor 240 is operated.
RAM 220, which can be stored temporarily, provides from host apparatus and will be provided to the number of non-volatile memory device 300 According to, and the data of host apparatus are received and will be transferred to from non-volatile memory device 300.That is, RAM 220 It can be used as buffer storage.
Host interface 230 can connect host apparatus with 100 interface of storage system.For example, host interface 230 can be used One of standard transmission protocol such as below a variety of is communicated with host apparatus: (general serial is total by secure digital, USB Line), MMC (multimedia card), eMMC (embedded MMC), PCMCIA (Personal Computer Memory Card International Association), PATA it is (parallel Advanced Technology Attachment), SATA (Serial Advanced Technology Attachment), SCSI (small computer system interface), SAS (tandem SCSI), PCI (peripheral component interconnection), PCI-E (high-speed PCI) and UFS (general flash storage).
Processor 240 may include micro-control unit (MCU) and central processing unit (CPU).Processor 240 can be handled from master The received request of machine device.In order to handle the request, processor 240 can drive load to RAM 220 the instruction based on code Or algorithm, i.e. firmware FW, and control internal functional blocks and non-volatile memory device 300.
Fig. 3 is shown the first information after completing the first speed buffering programming operation (hereinafter referred to as " first Speed buffering programming description symbol ") INF_CP1 is moved to the process of speed buffering queue 212.Hereinafter, reference Fig. 2 and Fig. 3, It will be described in executing the first speed buffering programming operation to the first data (hereinafter referred to as " the first programming data ") DT1 Process and the first speed buffering programming description of the first speed buffering programming operation will be corresponded to accord with INF_CP1 from order team Column 211 are moved to the process of speed buffering queue 212.
In step S31, the first speed buffering programming description generated by FTL can be accorded with INF_CP1 and be transferred to storage Device controller 210.For the first speed buffering programming operation the first speed buffering programming description symbol INF_CP1 may include about The address for storing the first programming data DT1 is believed in the information and non-volatile memory device 300 of first programming data DT1 Breath.
In step s 32, the first speed buffering programming description can be accorded with INF_CP1 and be stored in life by Memory Controller 210 It enables in queue 211.
In step S33, Memory Controller 210 can be compiled based on the first speed buffering being stored in command queue 211 Journey descriptor INF_CP1 generates the first speed buffering program command CMD_CP1, and by the first speed buffering program command of generation CMD_CP1 is transferred to non-volatile memory device 300.
In step S34, the first programming data DT1 in the RAM 220 for being stored in controller 200 can be transferred to non-easy The property lost memory device 300, and non-volatile memory device 300 can be based on the first speed buffering program command CMD_CP1 The the first programming data DT1 received is stored in page buffer 320.
When the first programming data DT1 is stored in page buffer 320, achievable first speed buffering programming behaviour Make.
In step s 35, non-volatile memory device 300 can be by the result including the first speed buffering programming operation First state information Response_CP1 is transferred to controller 200.
In step S36, the storage of first state information Response_CP1 is received from non-volatile memory device 300 First speed buffering programming description can be accorded with INF_CP1 and be moved to speed buffering queue from command queue 211 by device controller 210 212.That is, when receiving first state information Response_CP1 from non-volatile memory device 300, memory Controller 210, which can determine, completes the first speed buffering program command, and will correspond to the first speed buffering program command First speed buffering programming description accords with INF_CP1 and is moved to speed buffering queue 212 from command queue 211.In addition, by first Speed buffering programming description symbol INF_CP1 is moved to after speed buffering queue 212, and Memory Controller 210 can be from order team The first speed buffering programming description symbol INF_CP1 is deleted in column 211.
Fig. 4, which is shown, accords with INF_ for the first speed buffering programming description after completing the second speed buffering programming operation CP1 is moved to the process of response queue 213 from speed buffering queue 212.Hereinafter, referring to Figure 2 to Figure 4, it will be described in The process of second speed buffering programming operation is executed to the second programming data DT2 and the first speed buffering programming description is accorded with into INF_ CP1 is moved to the process of response queue 213 from speed buffering queue 212.For ease of description, as shown in Figure 3, it is assumed that the first programming Data DT1 is stored in the first data buffer 321 of page buffer 320, and the first speed buffering programming description accords with INF_CP1 is stored in speed buffering queue 212.
Step S41 to S43 can be executed in a manner of identical with above-mentioned steps S31 to S33 respectively.That is, memory Controller 210 can receive the second information for the second speed buffering programming operation (hereinafter referred to as " the second high speed from FTL Buffer programming description symbol ") INF_CP2, the second speed buffering programming description symbol INF_CP2 is stored in command queue 211, base The second speed buffering program command is generated in the second speed buffering programming description symbol INF_CP2 being stored in command queue 211 CMD_CP2, and the second speed buffering program command CMD_CP2 of generation is transferred to non-volatile memory device 300.Example Such as, the second speed buffering program command CMD_CP2 may include the first programming data for that will be stored in page buffer 320 DT1 is programmed into the order of memory cell array 310 and is used for the second data (hereinafter referred to as " the second programming data ") DT2 is buffered to the order in page buffer 320.
In step S44, the first data buffering of page buffer 320 is stored in by the first speed buffering programming operation The first programming data DT1 in device 321 can be moved to the second data buffer 323 of page buffer 320, and then compile Journey is to memory cell array 310.
In step S45, the second programming data DT2 being stored in the RAM 220 of controller 200 can be transmitted non-easy The property lost memory device 300, and non-volatile memory device 300 can be based on the second speed buffering program command CMD_CP2 Second programming data DT2 is stored in the first data buffer 321 of page buffer 320.
That is, when the first programming data DT1 for being moved to the second data buffer 323 is programmed into memory cell When array 310, the second programming data DT2 can be stored in the first data buffer 321 of page buffer 320.Implementing In example, step S44 and S45 can be performed simultaneously.
When step S44 and S45 are completed, achievable second speed buffering programming operation.
In step S46, non-volatile memory device 300 can be by the result including the second speed buffering programming operation Second status information Response_CP2 is transferred to controller 200.
In step S47, the storage of the second status information Response_CP2 is received from non-volatile memory device 300 Second speed buffering programming description can be accorded with INF_CP2 and be moved to speed buffering queue from command queue 211 by device controller 210 212。
That is, being deposited when receiving the second status information Response_CP2 from non-volatile memory device 300 Memory controller 210, which can determine, completes the second speed buffering program command, and will correspond to the second speed buffering programming life The the second speed buffering programming description symbol INF_CP2 enabled is moved to speed buffering queue 212 from command queue 211.In addition, will Second speed buffering programming description symbol INF_CP2 is moved to after speed buffering queue 212, and Memory Controller 210 can be deleted The the second speed buffering programming description symbol INF_CP2 being stored in command queue 211.
Second status information Response_CP2 may include the letter for indicating the second speed buffering programming operation and passing through or failing Breath.Passing through or failing for second speed buffering programming operation can indicate that the first programming data DT1 is normally to be programmed into storage Device cell array 310 or program fail.
In step S48, it is based on the second status information Response_CP2, Memory Controller 210 optionally will First speed buffering programming description accords with INF_CP1 and is moved to response queue 213 from speed buffering queue 212.
For example, when the second status information Response_CP2 includes the information for indicating the second speed buffering programming operation and passing through When, it can indicate that the first programming data DT1 is normally programmed into memory cell array 110.In this case, because of nothing The program command for being used for the first programming data DT1 need to be re-transmitted to non-volatile memory device 300, so memory control First speed buffering programming description can not be accorded with INF_CP1 and be moved to response queue 213 from speed buffering queue 212 by device 210 processed, But the first speed buffering programming description symbol INF_CP1 is deleted from speed buffering queue 212.
When the second status information Response_CP2, which includes, indicates the information of the second speed buffering programming operation failure, it It can indicate that the first programming data DT1 is not programmed into memory cell array 310.In this case, since it is desired that will be used for The program command of first programming data DT1 is re-transmitted to non-volatile memory device 300, so Memory Controller 210 First speed buffering programming description can be accorded with INF_CP1 and be moved to response queue 213 from speed buffering queue 212, and from height The first speed buffering programming description symbol INF_CP1 is deleted in fast buffering queue 212.Therefore, it can be ensured that with the first programming data DT1 The relevant descriptor (that is, the first speed buffering programming description accords with) about the first speed buffering programming operation.
When the first speed buffering programming description symbol INF_CP1 is deleted from speed buffering queue 212 in step S48, Second speed buffering programming description can be accorded with INF_CP2 and be moved to the first speed buffering programming description symbol by Memory Controller 210 The storage location of INF_CP1.However, the present embodiment is without being limited thereto.
In the present embodiment, controller 200 can program the first speed buffering about the first speed buffering programming operation Descriptor INF_CP1 is stored in speed buffering queue 212, and the second shape based on subsequent second speed buffering programming operation First speed buffering programming description symbol INF_CP1 is optionally stored in response queue 213 by state information Response_CP2. Therefore, controller 200 can correctly determine descriptor relevant to the data not being programmed into memory cell array 310. That is, it can be ensured that descriptor relevant to the data of program fail, and can be executed again based on the descriptor ensured pair The programming operation of the data of program fail, the reliability of storage system 100 can be improved in this.
Fig. 5 is shown third information after completing the first speed buffering read operation (hereinafter referred to as " first Speed buffering reads descriptor ") INF_CR1 is moved to the process of speed buffering queue 212.Hereinafter, reference Fig. 2 and Fig. 5, It will be described in executing the first speed buffering read operation to third data (hereinafter referred to as " first reads data ") DT3 Process and the first speed buffering of the first speed buffering read operation will be corresponded to read descriptor INF_CR1 from order team Column 211 are moved to the process of speed buffering queue 212.
In step s 51, the first speed buffering generated by FTL can be read descriptor INF_CR1 and is transferred to storage Device controller 210.It may include non-easy that the first speed buffering for the first speed buffering read operation, which reads descriptor INF_CR1, The address information of the property lost memory device 300, data DT3 is read in storage first in the address information.
In step S52, the first speed buffering can be read descriptor INF_CR1 and be stored in life by Memory Controller 210 It enables in queue 211.
In step S53, Memory Controller 210 can be read based on the first speed buffering being stored in command queue 211 Descriptor INF_CR1 is taken to generate the first speed buffering reading order CMD_CR1, and by the first speed buffering reading order of generation CMD_CR1 is transferred to non-volatile memory device 300.For example, the first speed buffering reading order CMD_CR1 may include being used for It reads the first reading data DT3 from memory cell array 310 and reading data is stored in the second of page buffer 320 and count According to the order in buffer 323.
In step S54, it is based on the first speed buffering reading order CMD_CR1, non-volatile memory device 300 can be from First is read in memory cell array 310 and reads data DT3, and the first reading data DT3 is stored in page buffer 320 The second data buffer 323 in.
When step S54 is completed, achievable first speed buffering read operation.
In step S55, non-volatile memory device 300 can be by the result including the first speed buffering read operation First state information Response_CR1 is transferred to Memory Controller 210.
In step S56, the storage of first state information Response_CR1 is received from non-volatile memory device 300 First speed buffering can be read descriptor INF_CR1 and be moved to speed buffering queue from command queue 211 by device controller 210 212.That is, when providing first state information Response_CR1 from non-volatile memory device 300, memory control Device 210 processed, which can determine, completes the first speed buffering reading order, and will correspond to the of the first speed buffering reading order One speed buffering reads descriptor INF_CR1 and is moved to speed buffering queue 212 from command queue 211.In addition, high by first Speed buffering reads descriptor INF_CR1 and is moved to after speed buffering queue 212, and Memory Controller 210 can be from command queue The first speed buffering is deleted in 211 reads descriptor INF_CR1.
Fig. 6, which is shown, reads descriptor INF_ for the first speed buffering after completing the second speed buffering read operation CR1 is moved to the process of response queue 213 from speed buffering queue 212.It hereinafter, will be detailed referring to Fig. 2, Fig. 5 and Fig. 6 The process that the second speed buffering read operation is executed to the 4th data (hereinafter referred to as " second reads data ") DT4 is described And the first speed buffering reading descriptor INF_CR1 is moved to the process of response queue 213 from speed buffering queue 212. For ease of description, as shown in fig. 5, it is assumed that the first reading data DT3 is stored in the second data buffer of page buffer 320 In 323, and the first speed buffering reads descriptor INF_CR1 and is stored in speed buffering queue 212.
Step S61 to S63 can be executed in a manner of identical with above-mentioned steps S51 to S53 respectively.That is, memory Controller 210 can receive the 4th information for the second speed buffering read operation (hereinafter referred to as " the second high speed from FTL Buffering reads descriptor ") INF_CR2, the second speed buffering reading descriptor INF_CR2 is stored in command queue 211, base Descriptor INF_CR2, which is read, in the second speed buffering being stored in command queue 211 generates the second speed buffering reading order CMD_CR2, and the second speed buffering reading order CMD_CR2 of generation is transferred to non-volatile memory device 300.Example Such as, the second speed buffering reading order CMD_CR2 may include the first reading data for that will be stored in page buffer 320 DT3 is output to the order of controller 200 and reads data DT4 and by second for reading second from memory cell array 310 It reads data DT4 and is stored in the order in page buffer 320.
In step S64, it is based on the second speed buffering reading order CMD_CR2, non-volatile memory device 300 can incite somebody to action The first reading data DT3 being stored in the second data buffer 323 of page buffer 320 is moved to the first data buffer 321, and the first reading data DT3 is transferred to Memory Controller 210 from the first data buffer 321.When the first reading When data DT3 is transmitted completely, the first reading data DT3 in the first data buffer 321 of page buffer 320 can be deleted It removes.
In step S65, it is based on the second speed buffering reading order CMD_CR2, non-volatile memory device 300 can be from Second is read in memory cell array 310 and reads data DT4, and the second reading data DT4 of reading is stored in the page and is delayed It rushes in the second data buffer 323 of device 320.Step S64 and S65 can be performed simultaneously.
When step S64 and S65 are completed, achievable second speed buffering read operation.
In step S66, non-volatile memory device 300 can be by the result including the second speed buffering read operation Second status information Response_CR2 is transferred to Memory Controller 210.
In step S67, the storage of the second status information Response_CR2 is received from non-volatile memory device 300 Second speed buffering can be read descriptor INF_CR2 and be moved to speed buffering queue from command queue 211 by device controller 210 212.In addition, Memory Controller 210, which can delete the second speed buffering being stored in command queue 211, reads descriptor INF_ CR2。
In step S68, ECC circuit can be used to receive to from non-volatile memory device 300 for Memory Controller 210 First reading data DT3 be decoded.For example, decoding may include ECC decoding.When the decoding for reading data DT3 to first is logical Out-of-date, the first reading data DT3 can be transferred to host apparatus by controller 200, and Memory Controller 210 can be slow from high speed It rushes in queue 212 and deletes the first speed buffering reading descriptor INF_CR1.
When the decoding for reading data DT3 to first fails, the first speed buffering can be read and be retouched by Memory Controller 210 It states symbol INF_CR1 and is moved to response queue 213 from speed buffering queue 212, and delete first from speed buffering queue 212 Speed buffering reads descriptor INF_CR1.Therefore, it can be ensured that the first speed buffering relevant to the first reading data DT3 is read The descriptor (that is, the first speed buffering reads descriptor) of operation.
When the first speed buffering reading descriptor INF_CR1 is deleted from speed buffering queue 212 in step S68, Second speed buffering can be read descriptor INF_CR2 and be moved to the first speed buffering reading descriptor by Memory Controller 210 The storage location of INF_CR1.However, the present embodiment is without being limited thereto.
In the present embodiment, controller 200 can read the first speed buffering about the first speed buffering read operation Descriptor INF_CR1 is stored in speed buffering queue 212, and is based on passing to by subsequent second speed buffering read operation First speed buffering reading descriptor INF_CR1 is optionally stored in sound by the decoding result of the first defeated reading data DT3 It answers in queue 213.Therefore, controller 200 can correctly determine descriptor relevant to the data for reading failure.That is, It can ensure that descriptor relevant to the data for reading failure, and can be executed again based on the descriptor ensured to reading failure The read operation of data, the reliability of storage system 100 can be improved in this.
Fig. 7 to Figure 11 B is the flow chart for describing the operating method of storage system 100 according to the embodiment.
Specifically, Fig. 7 is shown when cache operations corresponding with the descriptor being stored in command queue are completed When descriptor is moved to from command queue speed buffering queue method flow chart.
Fig. 8 to Fig. 9 B is to show to be moved to descriptor from speed buffering queue according to the result of speed buffering programming operation The flow chart of the method for response queue.
Figure 10 to Figure 11 B is to show to be moved descriptor from speed buffering queue according to the result of speed buffering read operation To the flow chart of the method for response queue.
Referring to Fig. 2 and Fig. 7, by description according to the operating method of the storage system 100 of the present embodiment.
In the step s 100, the Memory Controller 210 of controller 200 can by be used for cache operations information ( Hereinafter, referred to " descriptor ") it is stored in command queue 211.Cache operations may include speed buffering programming operation and Speed buffering read operation.Descriptor can be generated by FTL and be transferred to Memory Controller 210.
In step s 200, Memory Controller 210 can generate high speed based on the descriptor being stored in command queue 211 Buffers command, and the speed buffering order of generation is transferred to non-volatile memory device 300.
In step S300, non-volatile memory device 300 can execute high speed based on the speed buffering order received Buffer operation.
In step S400, non-volatile memory device 300 can believe the state of the result including cache operations Breath is transferred to Memory Controller 210.Status information may include indicating the information of cache operations completion and indicating that high speed is slow Punching operation passes through or the information of failure.
In step S500, descriptor can be moved to speed buffering queue from command queue 211 by Memory Controller 210 212.At this point, Memory Controller 210 can delete descriptor from command queue 211.That is, working as from non-volatile memories When device device 300 receives status information, Memory Controller 210 can determine that the high speed for completing and transmitting in step s 200 is slow Punching order, and corresponding descriptor is moved to speed buffering queue 212 so that descriptor is temporarily stored to speed buffering team In column 212.
Referring to Fig. 2 and Fig. 8, by description according to the operating method of the storage system 100 of the present embodiment.
In step S1100, Memory Controller 210 can will be used for the first information of the first speed buffering programming operation (hereinafter referred to as " the first speed buffering programming description symbol ") is stored in command queue 211.For example, the first speed buffering Programming operation may include the behaviour being stored in the first programming data in the page buffer 320 of non-volatile memory device 300 Make.
In step S1200, Memory Controller 210 can be based on the first speed buffering being stored in command queue 211 Programming description symbol generates the first speed buffering program command, and the first speed buffering program command of generation is transferred to non-volatile Property memory device 300.At this point, Memory Controller 210 the first programming data being stored in RAM 220 can be transferred to it is non- Volatile memory devices 300.
In step S1300, based on the first speed buffering program command received, non-volatile memory device 300 The first speed buffering programming operation can be executed to the first programming data.That is, non-volatile memory device 300 can basis First programming data is stored in page buffer 320 by the first speed buffering program command.When the first programming data is complete When storing in page buffer 320, achievable first speed buffering programming operation.
In step S1400, non-volatile memory device 300 can be by the result including the first speed buffering programming operation First state information be transferred to Memory Controller 210.First state information may include indicating the first speed buffering programming behaviour Make the information completed and indicates the information that the first speed buffering programming operation passes through or fails.For ease of description, the present embodiment base In there is no the hypothesis of the speed buffering programming operation operated before the first speed buffering programming operation.Therefore, the first shape State information can only include the information for indicating the first speed buffering programming operation and completing.
In step S1500, Memory Controller 210, which can determine, completes the first speed buffering program command, and by One speed buffering programming description symbol is moved to speed buffering queue 212 from command queue 211.It is retouched by the programming of the first speed buffering It states symbol to be moved to after speed buffering queue 212, it is slow that Memory Controller 210 can delete the first high speed from command queue 211 Rush programming description symbol.
In step S2100, Memory Controller 210 can will be used for the second information of the second speed buffering programming operation (hereinafter referred to as " the second speed buffering programming description symbol ") is stored in command queue 211.For example, the second speed buffering Programming operation may include will be buffered in the page buffer 320 of non-volatile memory device 300 in step S1300 One programming data is programmed into the operation of memory cell array 310, and the second programming data is buffered in non-volatile memories Operation in the page buffer 320 of device device 300, wherein the second programming data is in being buffered in page buffer 320 Memory cell array 310 is programmed into after first programming data.
In step S2200, Memory Controller 210 can be based on the second speed buffering being stored in command queue 211 Programming description symbol generates the second speed buffering program command, and the second speed buffering program command of generation is transferred to non-volatile Property memory device 300.At this point, Memory Controller 210 the second programming data being stored in RAM 220 can be transferred to it is non- Volatile memory devices 300.
In step S2300, non-volatile memory device 300 can be based on the second speed buffering program command received Execute the second speed buffering programming operation.That is, according to the second speed buffering program command, non-volatile memory device 300 can be while the first programming data that will be stored in page buffer 320 be programmed into memory cell array 310, will Second programming data is stored in page buffer 320.When the first programming data is programmed into memory cell array 310 completely And when the second programming data is completely stored in page buffer 320, achievable second speed buffering programming operation.
In step S2400, non-volatile memory device 300 can be by the result including the second speed buffering programming operation The second status information be transferred to Memory Controller 210.Second status information may include indicating the second speed buffering programming behaviour Make the information completed and indicates the information that the second speed buffering programming operation passes through or fails.For example, indicating the second speed buffering The information that programming operation is completed can indicate to complete the operation being stored in the second programming data in page buffer 320.It indicates Second speed buffering programming operation passes through or the information of failure can indicate the first programming data being programmed into memory cell array 310 operation be by or failure.
In step S2500, Memory Controller 210, which can determine, completes the second speed buffering program command, by second Speed buffering programming description symbol is moved to speed buffering queue 212 from command queue 211, then deletes from command queue 211 Second speed buffering programming description symbol.
In step S2600, Memory Controller 210 is based on the second status information may or may not be slow by the first high speed It rushes programming description symbol and is moved to response queue 213 from speed buffering queue 212.
Fig. 9 A is the flow chart for being shown specifically the step S2600 of Fig. 8.
In step S2610, it is based on from received second status information of non-volatile memory device 300, memory control Device 210 processed can determine that the operation that the first data are programmed into memory cell array 310 is failure or passes through.It is compiled when by first When number of passes is according to the operation of memory cell array 310 is programmed by (being "No" in step S2610), process be can continue to Step S2630.On the other hand, when the operation failure (step that the first programming data is programmed into memory cell array 310 It is "Yes" in S2610) when, process can continue to step S2620.
In step S2620, Memory Controller 210 can accord with the first speed buffering programming description from speed buffering queue 212 are moved to response queue 213.
In step S2630, Memory Controller 210 can delete the first speed buffering volume from speed buffering queue 212 Journey descriptor.
That is, when the second status information includes indicating the first programming data being programmed into memory cell array 310 Operation failure information when, Memory Controller 210 can accord with the first speed buffering programming description from speed buffering queue 212 It is moved to response queue 213, the first speed buffering programming description symbol is then deleted from speed buffering queue 212.On the other hand, When the second status information includes the information for indicating for the first programming data to be programmed into the operation of memory cell array 310 and passing through When, the first speed buffering programming description can not be accorded with from speed buffering queue 212 and be moved to response queue by Memory Controller 210 213, but the first speed buffering programming description symbol is deleted from speed buffering queue 212.
Fig. 9 B is the stream for showing the operating method when the first speed buffering programming description symbol is moved to response queue 213 Cheng Tu.
In step S2710, the processor 240 of controller 200 can delete the order team for being stored in Memory Controller 210 Descriptor in column 211, speed buffering queue 212 and response queue 213.
In step S2720, processor 240 can program the first speed buffering for being used for the first speed buffering programming operation Descriptor and for the second speed buffering programming operation the second speed buffering programming description symbol be sequentially re-transmitted to storage Device controller 210.Following operation can be executed with same way described in step S1100 to S2600.
Referring to Fig. 2 and Figure 10, by description according to the operating method of the storage system 100 of the present embodiment.
In step S3100, Memory Controller 210 can will be used for the third information of the first speed buffering read operation (hereinafter referred to as " the first speed buffering reads descriptor ") is stored in command queue 211.For example, the first speed buffering Read operation may include reading the first reading data from memory cell array 310 and the first reading data being stored in the page to delay Rush the operation in device 320.
In step S3200, Memory Controller 210 can be based on the first speed buffering being stored in command queue 211 It reads descriptor and generates the first speed buffering reading order, and the first speed buffering reading order of generation is transferred to non-volatile Property memory device 300.
In step S3300, based on the first speed buffering reading order received, non-volatile memory device 300 Data can be read to first execute the first speed buffering read operation.That is, according to the first speed buffering reading order, it is non- Volatile memory devices 300 can read first from memory cell array 310 and read data, and read number for the first of reading According to being stored in page buffer 320.When the first reading data are completely stored in page buffer 320, achievable the One speed buffering read operation.
In step S3400, non-volatile memory device 300 can be by the result including the first speed buffering read operation Third state information is transferred to Memory Controller 210.Third state information may include indicating the first speed buffering read operation The information of completion.
In step S3500, Memory Controller 210, which can determine, completes the first speed buffering read operation, and by One speed buffering reads descriptor and is moved to speed buffering queue 212 from command queue 211.It is retouched by the reading of the first speed buffering It states symbol to be moved to after speed buffering queue 212, it is slow that Memory Controller 210 can delete the first high speed from command queue 211 Descriptor is read in punching.
In step S4100, Memory Controller 210 can will be used for the 4th information of the second speed buffering read operation (hereinafter referred to as " the second speed buffering reads descriptor ") is stored in command queue 211.For example, the second speed buffering Read operation can include: will be read and stored in page buffer 320 in step S3300 from memory cell array 310 The first reading data be transferred to the operation of Memory Controller 210；And second is read from memory cell array 310 and is read Second reading data are simultaneously stored in the operation in page buffer 320 by data, wherein second reads data in the first reading number According to being transferred to Memory Controller 210 later.
In step S4200, Memory Controller 210 can be based on the second speed buffering being stored in command queue 211 It reads descriptor and generates the second speed buffering reading order, and the second speed buffering reading order of generation is transferred to non-volatile Property memory device 300.
In step S4300, non-volatile memory device 300 can be based on the second speed buffering reading order received Execute the second speed buffering read operation.That is, according to the second speed buffering reading order, non-volatile memory device 300 can be while the first reading data that will be stored in page buffer 320 be transferred to Memory Controller 210, from depositing The second reading data are read in memory cell array 310 and the second reading data of reading are stored in page buffer 320. When by first reading full data transmission to Memory Controller 210 and by second read data be completely stored in page buffer When in device 320, achievable second speed buffering read operation.
In step S4400, non-volatile memory device 300 can be by the result including the second speed buffering read operation The 4th status information be transferred to Memory Controller 210.4th status information may include indicating that the second speed buffering reads behaviour Make the information completed.
In step S4500, Memory Controller 210 can determine the processing for completing the second speed buffering reading order, Second speed buffering is read into descriptor and is moved to speed buffering queue 212 from command queue 211, then from command queue 211 The second speed buffering of middle deletion reads descriptor.
In step S4600, the first speed buffering may or may not be read descriptor from height by Memory Controller 210 Fast buffering queue 212 is moved to response queue 213.
Figure 11 A is the flow chart for being shown specifically the step S4600 of Figure 10.
In step S4610, Memory Controller 210 can be read from non-volatile memory device 300 received first Access evidence is decoded.
In step S4620, Memory Controller 210 can determine whether the decoding to the first reading data fails.Work as solution When code is by (being "No" in step S4620), process can continue to step S4640.When decoding failure is (in step S4620 For "Yes") when, process can continue to step S4630.
In step S4630, the first speed buffering can be read descriptor from speed buffering queue by Memory Controller 210 212 are moved to response queue 213.
In step S4640, Memory Controller 210 can delete the reading of the first speed buffering from speed buffering queue 212 Take descriptor.
That is, being read when to first read by the first speed buffering read operation from memory cell array 310 When the decoding failure for evidence of fetching, the first speed buffering can be read descriptor from speed buffering queue 212 by Memory Controller 210 It is moved to response queue 213, the first speed buffering is then deleted from speed buffering queue 212 and reads descriptor.On the other hand, When the decoding to the first reading data passes through, the first speed buffering can not be read descriptor from height by Memory Controller 210 Fast buffering queue 212 is moved to response queue 213, but deletes the first speed buffering from speed buffering queue 212 and read description Symbol.
Figure 11 B is shown when the first speed buffering reads operating method when descriptor is moved to response queue 213 Flow chart.
In step S4710, the processor 240 of controller 200 can delete the order team for being stored in Memory Controller 210 Descriptor in column 211, speed buffering queue 212 and response queue 213.
In step S4720, processor 240 can drive FLT to generate for third data (that is, first reads data) Normal read operation third descriptor, and by the 5th information of generation (hereinafter referred to as " third descriptor ") pass It is defeated to arrive Memory Controller 210.At this point, normal read operation can be following operation: reading the from memory cell array 310 One reads data, the first reading data of reading is stored in page buffer 320, and will be stored in page buffer The first reading data in 320 are transferred to Memory Controller 210.Memory Controller 210 can be generated based on third descriptor The normal reading order for reading data for first, and the normal reading order of generation is transferred to nonvolatile memory dress Set 300.
In step S4730, non-volatile memory device 300 can execute following normal reading according to normal reading order Extract operation: the first reading data are read from memory cell array 310, the first reading data are stored in page buffer 320 In and by be stored in page buffer 320 first reading data be transferred in Memory Controller 210.
In step S4740, Memory Controller 210 can be read from non-volatile memory device 300 received first Access evidence is decoded.
In step S4750, Memory Controller 210 can determine whether the decoding to the first reading data passes through.Work as solution When code failure (being "No" in step S4750), step S4720 to S4740 can be executed again.When decoding is by (in step S4750 For "Yes") when, process can continue to step S4760.
In step S4760, processor 240 can drive FTL to generate for the 4th data (that is, second reads data) Normal read operation the 6th information (hereinafter referred to as " the 4th descriptor "), and by the 4th descriptor of generation pass It is defeated to arrive Memory Controller 210.Memory Controller 210 can be generated based on the 4th descriptor and read the normal of data for second Reading order, and the normal reading order of generation is transferred to non-volatile memory device 300.
In step S4770, non-volatile memory device 300 can execute following normal reading according to normal reading order Operation: the second reading data are read from memory cell array 310, the second reading data of reading are stored in page buffer Memory Controller 210 is transferred in 320 and by the be stored in page buffer 320 second reading data.
In step S4780, Memory Controller 210 can be read from non-volatile memory device 300 received second Access evidence is decoded.
In step S4790, Memory Controller 210 can determine whether the decoding to the second reading data passes through.Work as solution When code failure (being "No" in step S4790), step S4760 to S4780 can be executed again.When decoding is by (in step S4790 For "Yes") when, the process can be terminated.
According to the present embodiment, storage system and operating method can correctly determine stored in memory for failing The descriptor of data and descriptor for decoding miss data, and behaviour is read in speed buffering programming operation and speed buffering Programming/read operation is executed to corresponding data again during work, the reliability of system can be improved in this way.
Figure 12 is to show the representative example of the data processing system according to the embodiment including solid state drive (SSD) to show Figure.Referring to Fig.1 2, data processing system 1000 may include host apparatus 1100 and SSD 1200.
SSD 1200 may include controller 1210, buffer memory means 1220, non-volatile memory device 1231 to 123n, power supply 1240, signal connector 1250 and power connector 1260.
Controller 1210 can control the general operation of SSD 1200.Controller 1210 may include memory control unit 210, Random access memory 220, host interface unit 230, control unit 240 and error-correcting code (ECC) unit 1214.
Memory control unit 210 will can such as be ordered according to the control of control unit 240 and the control signal of address mentions Non-volatile memory device 1231 is supplied to 123n.In addition, memory control unit 210 can be according to the control of control unit 240 System exchanges data with non-volatile memory device 1231 to 123n.For example, memory control unit 210 can will be stored in buffering Data in memory device 1220 are supplied to non-volatile memory device 1231 to 123n, or will be from non-volatile memories Device device 1231 to the data that 123n is read are supplied to buffer memory means 1220.
Host interface unit 230 can exchange signal SGL with host apparatus 1100 by signal connector 1250.Signal SGL It may include order, address, data etc..Host interface unit 230 can be according to the agreement of host apparatus 1100 come to host apparatus 1100, which carry out interface with SSD 1200, connects.For example, host interface unit 230 can be by standard interface protocol such as below Any one communicated with host apparatus 1100: it is secure digital, universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), Personal Computer Memory Card International Association (PCMCIA), parallel advanced technology annex (PATA), serial advanced skill Art attachment (SATA), small computer system interface (SCSI), tandem SCSI (SAS), peripheral component interconnection (PCI), high-speed PCI (PCI-E) and general flash stores (UFS).
The signal SGL inputted from host apparatus 1100 can be analyzed and be handled to control unit 240.Control unit 240 can basis The operation of internal functional blocks is controlled for driving the firmware or software of SSD 1200.Random access memory 220 can be used as driving Move the working storage of this firmware or software.
Error-correcting code (ECC) unit 1214 produces the number to be transmitted to non-volatile memory device 1231 to 123n According to parity data.The parity data of generation can be collectively stored in data non-volatile memory device 1231 to In 123n.Error-correcting code (ECC) unit 1214 can be detected based on parity data from non-volatile memory device The mistake of 1231 to the 123n data read.If the mistake detected is within the scope of recoverable, error-correcting code (ECC) is single The mistake that first 1214 recoverables detect.
Buffer memory means 1220 can be stored temporarily to be stored in non-volatile memory device 1231 into 123n Data.Further, buffer memory means 1220 can be stored temporarily from non-volatile memory device 1231 to 123n and be read Data.The data being temporarily stored in buffer memory means 1220 can be transferred to master according to the control of controller 1210 Machine device 1100 or non-volatile memory device 1231 are to 123n.
Non-volatile memory device 1231 can be used as the storage medium of SSD 1200 to 123n.Nonvolatile memory dress Setting 1231 to 123n can be coupled by multiple channel C H1 to CHn with controller 1210 respectively.One or more non-volatile memories Device device can be connected to a channel.The non-volatile memory device for being connected to each channel can be connected to identical signal Bus and data/address bus.
The electric power PWR inputted by power connector 1260 can be provided to the inside of SSD 1200 by power supply 1240.Power supply 1240 may include accessory power supply 1241.When occur suddenly power-off when, accessory power supply 1241 can be powered so that SSD 1200 just Often terminate.Accessory power supply 1241 may include large value capacitor.
Signal connector 1250 can be according to the interface connection scheme between host apparatus 1100 and SSD 1200 and by each The connector of seed type configures.
Power connector 1260 can be configured according to the power supply plan of host apparatus 1100 by various types of connectors.
Figure 13 is the diagram for showing the representative example of the data processing system according to the embodiment including storage system.Ginseng According to Figure 13, data processing system 2000 may include host apparatus 2100 and storage system 2200.
Host apparatus 2100 can the plate form of such as printed circuit board configure.Although it is not shown, but host apparatus 2100 may include the internal functional blocks for executing the function of host apparatus.
Host apparatus 2100 may include the connection terminal 2110 of such as socket, slot or connector.Storage system 2200 Connection terminal 2110 can be mounted to.
Storage system 2200 can the plate form of such as printed circuit board configure.Storage system 2200 is represented by Memory module or storage card.Storage system 2200 may include controller 2210, buffer memory means 2220, non-volatile Memory device 2231 and 2232, power management integrated circuit (PMIC) 2240 and connection terminal 2250.
Controller 2210 can control the general operation of storage system 2200.Controller 2210 can be controlled with shown in Figure 12 Device 1210 processed configures in an identical manner.
Buffer memory means 2220 can be stored temporarily in non-volatile memory device 2231 and 2232 to be stored in Data.Further, buffer memory means 2220 can be stored temporarily reads from non-volatile memory device 2231 and 2232 The data taken.The data being temporarily stored in buffer memory means 2220 can be transferred to according to the control of controller 2210 Host apparatus 2100 or non-volatile memory device 2231 and 2232.
Non-volatile memory device 2231 and 2232 can be used as the storage medium of storage system 2200.
PMIC 2240 can provide the electric power inputted by connection terminal 2250 to the inside of storage system 2200. PMIC 2240 can manage the electric power of storage system 2200 according to the control of controller 2210.
Connection terminal 2250 can be connected to the connection terminal 2110 of host apparatus 2100.By connection terminal 2250, such as The signal and electric power of order, address, data etc. can transmit between host apparatus 2100 and storage system 2200.According to host Interface scheme between device 2100 and storage system 2200, connection terminal 2250 can be configured to various types.Connecting pin Son 2250 may be disposed at any side of storage system 2200.
Figure 14 is the diagram for showing the representative example of the data processing system according to the embodiment including storage system.Ginseng According to Figure 14, data processing system 3000 may include host apparatus 3100 and storage system 3200.
Host apparatus 3100 can the plate form of such as printed circuit board configure.Although it is not shown, but host apparatus 3100 may include the internal functional blocks for executing the function of host apparatus.
Storage system 3200 can be configured in the form that surface installing type encapsulates.Storage system 3200 can pass through soldered ball 3250 are installed to host apparatus 3100.Storage system 3200 may include controller 3210, buffer memory means 3220 and non- Volatile memory devices 3230.
Controller 3210 can control the general operation of storage system 3200.Controller 3210 can be controlled with shown in Figure 12 Device 1210 processed configures in an identical manner.
Buffer memory means 3220 can temporarily store the data in non-volatile memory device 3230 to be stored in. Further, buffer memory means 3220 can temporarily store the data read from non-volatile memory device 3230.Faced When the data that are stored in buffer memory means 3220 can be transferred to host apparatus 3100 according to the control of controller 3210 Or non-volatile memory device 3230.
Non-volatile memory device 3230 can be used as the storage medium of storage system 3200.
Figure 15 is the diagram for showing the representative example of the network system according to the embodiment including storage system.Referring to figure 15, network system 4000 may include the server system 4300 coupled by network 4500 and multiple client system 4410 to 4430。
Server system 4300 may be in response to carry out service data from the request of multiple client system 4410 to 4430.Example Such as, server system 4300 can store the data provided from multiple client system 4410 to 4430.In another example server system 4300 can serve data to multiple client system 4410 to 4430.
Server system 4300 may include host apparatus 4100 and storage system 4200.Storage system 4200 can pass through The storage system 100 of Fig. 1, the SSD 1200 of Figure 12, the storage system 2200 of Figure 13 or the storage system 3200 of Figure 14 To configure.
Figure 16 is that show according to the embodiment include that the representative of the non-volatile memory device in storage system is shown The block diagram of example.Referring to Fig.1 6, non-volatile memory device 300 may include memory cell array 310, row decoder 320, page Face buffer 330, column decoder 340, voltage generator 350 and control logic 360.
Memory cell array 310 may include that the region intersected with each other wordline WL1 to WLm and bit line BL1 to BLn is arranged in In memory cell MC.
Page buffer 330 can be coupled by bit line BL1 to BLn with memory cell array 310.Page buffer 330 It may include the read/write circuits RW1 to RWn for corresponding respectively to bit line BL1 to BLn.Page buffer 330 can be patrolled according to control 360 control is collected to operate.Page buffer 330 can be operated according to operation mode as write driver or sense amplifier. For example, page buffer 330 can be used as write driver to operate, which in write operation will be by external device (ED) The data of offer are stored in memory cell array 310.In another example page buffer 330 can be used as sense amplifier to grasp Make, which reads data from memory cell array 310 in read operation.
Row decoder 320 can be coupled by wordline WL1 to WLm with memory cell array 310.Row decoder 320 can It is operated according to the control of control logic 360.Row decoder 320 can be solved to from the address that external device (ED) (not shown) provides Code.Row decoder 320 can be selected based on decoding result and drive wordline WL1 to WLm.For example, row decoder 320 can will be from electricity The word line voltage that pressure generator 350 provides is supplied to wordline WL1 to WLm.
Column decoder 340 can be operated according to the control of control logic 360.Column decoder 340 can be mentioned to from external device (ED) The address of confession is decoded.Column decoder 340 can will correspond respectively to the page buffer of bit line BL1 to BLn based on decoding result The read/write circuits RW1 to RWn of device 330 couples with data input/output line (or data input/output buffer).
Voltage generator 350, which produces, will be used for the voltage of the inside operation of non-volatile memory device 300.Pass through electricity The voltage that pressure generator 350 generates can be applied to the memory cell of memory cell array 310.For example, in programming operation The program voltage of middle generation can be applied to the wordline of the memory cell of pending programming operation.For another example in erasing operation The erasing voltage of middle generation can be applied to the well area of the memory cell of pending erasing operation.For another example being grasped reading The reading voltage generated in work can be applied to the wordline of the memory cell of pending read operation.
Control logic 360 can control non-volatile memory device 300 based on the control signal provided from external device (ED) General operation.For example, control logic 360 can control read operation, write operation and the wiping of non-volatile memory device 300 Except operation.
It can will be applied to method according to an embodiment of the present disclosure to the description of above system.Therefore, it is omitted in method To description identical with the description of above system.
Although each embodiment is described above, it will be appreciated, however, by one skilled in the art that described embodiment It is merely illustrative.Therefore, storage system and its operating method described herein should not based on described embodiment and by Limitation.

Claims (19)

1. a kind of storage system, comprising:
Non-volatile memory device, including memory cell array and the page buffer for being connected to the memory cell array Device；And
Controller is connect with the non-volatile memory device interface,
Wherein the controller will be moved to speed buffering queue from command queue about the descriptor of speed buffering order, and The descriptor that selectively will be moved into the speed buffering queue is moved to response queue, wherein the speed buffering is ordered Order is transferred to the non-volatile memory device.
2. storage system according to claim 1, wherein the controller is based on being stored in the command queue The descriptor generates the speed buffering order, and speed buffering order generated is transferred to described non-volatile deposit Reservoir device.
3. storage system according to claim 2, wherein the non-volatile memory device is slow according to the high speed Punching order executes cache operations to the memory cell array and the page buffer, and will include the high speed The status information of the result of buffer operation is transferred to the controller.
4. storage system according to claim 3, wherein described when being provided from the non-volatile memory device When status information, the descriptor is moved to the speed buffering queue from the command queue by the controller.
5. storage system according to claim 1,
Wherein the speed buffering order includes for the first speed buffering program command of the first data and for the second data The second speed buffering program command, and
Wherein the non-volatile memory device is based on the first speed buffering program command execution for first data The first speed buffering programming operation being stored in the page buffer, and it is based on the second speed buffering program command The first data in the page buffer are programmed into the memory cell array and deposit second data by execution Store up the second speed buffering programming operation in the page buffer.
6. storage system according to claim 5,
Wherein first state information and the second status information are transferred to the controller by the non-volatile memory device, Described in first state information include the first speed buffering programming operation as a result, second status information includes described Second speed buffering programming operation as a result, and
Wherein when receiving the first state information and second status information from the non-volatile memory device, The the first speed buffering programming description for corresponding to the first speed buffering program command is accorded with and is corresponded to institute by the controller The the second speed buffering programming description symbol for stating the second speed buffering program command is moved to the high speed from the command queue and delays Rush queue.
7. storage system according to claim 6, wherein when second status information includes that second high speed is slow When rushing the failure information of programming operation, the controller accords with the first speed buffering programming description from the speed buffering team Column are moved to the response queue.
8. storage system according to claim 7, wherein controller deletion is stored in the command queue, described Descriptor in speed buffering queue and the response queue, and by the first speed buffering program command and described second Speed buffering program command is sequentially re-transmitted to the non-volatile memory device.
9. storage system according to claim 1,
Wherein the speed buffering order includes for the first speed buffering reading order of the first data and for the second data The second speed buffering reading order, and
Wherein the non-volatile memory device is based on the first speed buffering reading order execution from the memory list Element array reads first data and the first speed buffering that first data are stored in the page buffer is read Extract operation, and transmitted first data from the page buffer based on the second speed buffering reading order execution Second data are read to the controller, from the memory cell array and are stored in second data described The second speed buffering read operation in page buffer.
10. storage system according to claim 9,
Wherein first state information and the second status information are transferred to the controller by the non-volatile memory device, Described in first state information include the first speed buffering read operation as a result, second status information includes described Second speed buffering read operation as a result, and
Wherein when receiving the first state information and second status information from the non-volatile memory device, The first speed buffering for corresponding to the first speed buffering reading order is read descriptor and corresponds to institute by the controller The the second speed buffering reading descriptor for stating the second speed buffering reading order is moved to the high speed from the command queue and delays Rush queue.
11. storage system according to claim 10, wherein the controller executes wrong school to first data Code decoding is ECC decoding, and when the ECC decodes failure, will first speed buffering reading descriptor from described Speed buffering queue is moved to the response queue.
12. storage system according to claim 11, wherein controller deletion is stored in the command queue, institute State the descriptor in speed buffering queue and the response queue, and by be used for first data normal reading order and Normal reading order for second data is sequentially transmitted the non-volatile memory device.
13. a kind of method for operating storage system, which comprises
It will be used to be stored in command queue to the descriptor of the cache operations of non-volatile memory device by controller In；
The descriptor is based on by the controller and generates speed buffering order, and the speed buffering order is transferred to institute State non-volatile memory device；
The speed buffering order, which is based on, by the non-volatile memory device executes cache operations；
The status information of the result including the cache operations is transferred to institute by the non-volatile memory device State controller；And
When receiving the status information from the non-volatile memory device, by the controller by the descriptor Speed buffering queue is moved to from the command queue.
14. according to the method for claim 13,
Wherein the speed buffering order includes for the first speed buffering program command of the first data and for the second data The second speed buffering program command, and
Wherein executing the cache operations includes:
It is executed based on the first speed buffering program command and first data is stored in the nonvolatile memory dress The first speed buffering programming operation in the page buffer set；And
It is executed based on the second speed buffering program command and first data in the page buffer is programmed into institute It states the memory cell array of non-volatile memory device and second data is stored in the page buffer Second speed buffering programming operation.
15. according to the method for claim 14,
Wherein transmitting the status information includes: that first state information and the second status information are transferred to the controller, Described in first state information include the first speed buffering programming operation as a result, second status information includes described Second speed buffering programming operation as a result, and
Wherein move the descriptor include: when from the non-volatile memory device receive the first state information and When second status information, will correspond to the first speed buffering program command the first speed buffering programming description symbol and The second speed buffering programming description corresponding to the second speed buffering program command, which is accorded with from the command queue, is moved to institute State speed buffering queue.
16. according to the method for claim 15, further comprising:
When second status information includes the failure information of the second speed buffering programming operation, pass through the controller The first speed buffering programming description is accorded with from the speed buffering queue and is moved to response queue；And
Retouching in the command queue, the speed buffering queue and the response queue is stored in by controller deletion Symbol is stated, and the first speed buffering program command and the second speed buffering program command are sequentially re-transmitted to The non-volatile memory device.
17. according to the method for claim 13,
Wherein the speed buffering order includes for the first speed buffering reading order of the first data and for the second data The second speed buffering reading order, and
Wherein executing the cache operations includes:
The memory cell array from the non-volatile memory device is executed based on the first speed buffering reading order It reads first data and first data is stored in the page buffer of the non-volatile memory device The first speed buffering read operation；And
It is executed based on the second speed buffering reading order by the first data transmission in the page buffer to the control Device processed reads second data from the memory cell array and the second data of reading is stored in the page and delays Rush the second speed buffering read operation in device.
18. according to the method for claim 17,
Wherein transmitting the status information includes: that first state information and the second status information are transferred to the controller, Described in first state information include the first speed buffering read operation as a result, second status information includes described Second speed buffering read operation as a result, and
Wherein move the descriptor include: when from the non-volatile memory device receive the first state information and When second status information, by correspond to the first speed buffering reading order the first speed buffering read descriptor and The second speed buffering corresponding to the second speed buffering reading order reads descriptor and is moved to institute from the command queue State speed buffering queue.
19. according to the method for claim 18, further comprising:
ECC decoding is executed to from received first data of the non-volatile memory device by the controller；
It is determined by the controller to whether the ECC decoding of first data fails；
When the ECC to first data decodes failure, first speed buffering is read by the controller Descriptor is moved to response queue from the speed buffering queue；And
By the normal reading order for being used for first data and the normal readings of second data to be used for by the controller It is transferred to the non-volatile memory device with taking command sequences.
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