CN110022245B - Debugging method, debugging system and storage medium - Google Patents

Debugging method, debugging system and storage medium Download PDF

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Publication number
CN110022245B
CN110022245B CN201910285692.1A CN201910285692A CN110022245B CN 110022245 B CN110022245 B CN 110022245B CN 201910285692 A CN201910285692 A CN 201910285692A CN 110022245 B CN110022245 B CN 110022245B
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chip
network management
management module
change value
packet
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CN110022245A (en
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王志浩
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/06—Management of faults, events, alarms or notifications
    • H04L41/0654—Management of faults, events, alarms or notifications using network fault recovery
    • H04L41/0659—Management of faults, events, alarms or notifications using network fault recovery by isolating or reconfiguring faulty entities
    • H04L41/0661—Management of faults, events, alarms or notifications using network fault recovery by isolating or reconfiguring faulty entities by reconfiguring faulty entities
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L41/00—Arrangements for maintenance, administration or management of data switching networks, e.g. of packet switching networks
    • H04L41/06—Management of faults, events, alarms or notifications
    • H04L41/0677—Localisation of faults
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L43/00—Arrangements for monitoring or testing data switching networks
    • H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
    • H04L43/0805—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability
    • H04L43/0811—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters by checking availability by checking connectivity

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Environmental & Geological Engineering (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The invention discloses a debugging method, which comprises the following steps: the method comprises the steps that a first network management module obtains a change value of a first chip sending package and a change value of a second chip receiving package, wherein the first chip sends the package to the second chip; if the first network management module judges that the change value of the first chip sending package is larger than the change value of the second chip receiving package, judging the link between the first chip and the second chip is blocked; the first network management module, the first chip and the second chip are arranged on a first server; the embodiment of the application also provides a debugging system and a storage medium; the embodiment provided by the invention monitors the conditions of receiving and sending the packets between the chips through the network management module so as to judge the link blocking points between the chips, can quickly position the problem under the condition that the topology complexity of the whole link in the system network is increased, and improves the debuggability of the system.

Description

Debugging method, debugging system and storage medium
Technical Field
The invention relates to the technical field of computers, in particular to a debugging method, a debugging system and a storage medium.
Background
Servers, also known as servers, are devices that provide computing services, and memory is a memory device in a computer system that stores programs and data. With the development of information technology, more and more functions need to be realized through a system network in equipment such as a server mainboard or a memory; the interconnection between the chips and even the sharing of the link to achieve efficient information transfer directly results in high complexity of the system network topology.
In the prior art, when a system network encounters a condition that a link is not through, the high complexity of the overall link topology greatly affects the speed of problem location, and further affects the debuggability of the system network.
Therefore, the above problems in the prior art have yet to be improved.
Disclosure of Invention
Embodiments of the present invention provide a debugging method, a debugging system, and a storage medium, which can quickly locate a link congestion point and improve the adjustability of a system network by obtaining a change in packet receiving and sending conditions between chips in a complex system network.
In view of the above, a first aspect of the present application provides a debugging method, including: the method comprises the steps that a first network management module obtains a change value of a first chip sending package and a change value of a second chip receiving package, wherein the first chip sends the package to the second chip; if the first network management module judges that the change value of the first chip sending package is larger than the change value of the second chip receiving package, judging the link between the first chip and the second chip is blocked; the first network management module, the first chip and the second chip are arranged on a first server.
With reference to the first aspect of the present application, in a first possible implementation manner, the first server further includes a reset module, and after the determining that the link between the first chip and the second chip is blocked, the method further includes: the first network management module acquires a reset signal sent by a reset module, wherein the reset signal is used for restarting the first chip and the second chip; the first network management module sends the reset signal to the first chip and the second chip.
With reference to the first possible implementation manner of the first aspect of the present application, in a second possible implementation manner, the method further includes a second server, where the second server is the same as the first server, and the method further includes: the first network management module acquires a change value of a packet sent by the second chip to a third chip, and the third chip is arranged on the second server; the first network management module sends a change value of a packet sent by the second chip to a third chip to a second network management module through a transceiver module, and the second network management module is arranged on the second server and connected with the third chip; the second network management module acquires a change value of the third chip receiving the second chip sending package; if the second network management module judges that the change value of the packet sent by the second chip to the third chip is larger than the change value of the packet sent by the second chip received by the third chip, the link between the second chip and the third chip is blocked.
With reference to the first aspect, the first possible implementation manner, or the second possible implementation manner of the present application, in a third possible implementation manner, the change value is a magnitude value of packet transceiving or a rate value of packet transceiving.
A second aspect of the present application provides a debugging system having the functionality of a method implementing the first aspect or any one of the possible implementations of the first aspect. The function can be realized by hardware, and can also be realized by executing corresponding software by hardware. The hardware or software includes one or more modules corresponding to the functions described above.
A third aspect of the present application provides a server apparatus comprising: a processor and a memory; the memory is configured to store computer-executable instructions, and when the server device operates, the processor executes the computer-executable instructions stored in the memory, so as to enable the server device to perform the debugging method according to the first aspect or any one of the possible implementations of the first aspect.
A fourth aspect of the present application provides a computer-readable storage medium, having stored therein instructions, which, when run on a computer, enable the computer to perform the debugging method of the first aspect or any one of the possible implementations of the first aspect.
According to the technical scheme, the embodiment of the application has the following advantages:
in an embodiment of the present invention, a debugging method, a debugging system, and a storage medium are provided, including: the method comprises the steps that a first network management module obtains a change value of a first chip sending package and a change value of a second chip receiving package, wherein the first chip sends the package to the second chip; if the first network management module judges that the change value of the first chip sending package is larger than the change value of the second chip receiving package, judging the link between the first chip and the second chip is blocked; the first network management module, the first chip and the second chip are arranged on a first server. The variation value can be the number of packets to be sent and received in real time or the rate of sending and receiving the packets in real time; whether a link between the two chips is blocked is judged by measuring the packet receiving and sending conditions between the two chips, so that the on-off condition and the link blocking point of the whole link are timely confirmed in a system network link with a high complex system network, and the debuggability of the system network is improved.
Drawings
FIG. 1 is a topology diagram of a prior art system network;
FIG. 2 is a topology diagram of one embodiment of a system network in an embodiment of the present application;
FIG. 3 is a schematic diagram of an embodiment of a debugging method in the embodiment of the present application;
FIG. 4 is a schematic diagram of another embodiment of a debugging method in the embodiment of the present application;
FIG. 5 is a schematic diagram of another embodiment of a debugging method in the embodiment of the present application;
FIG. 6 is a schematic diagram of another embodiment of a debugging method in the embodiment of the present application;
FIG. 7 is a schematic diagram of another embodiment of a debugging method in the embodiment of the present application;
fig. 8 is a schematic device diagram of a debugging system in the embodiment of the present application.
Detailed Description
Embodiments of the present invention provide a debugging method, a debugging system, and a storage medium, which can quickly determine whether a link is blocked by acquiring a condition of receiving and sending a packet between chips, so as to find a link blocking point in time.
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the above-described drawings (if any) are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As shown in fig. 1, in a server motherboard or a memory, in order to store data and ensure normal operation of the system, a complex system Network is disposed on the motherboard, and taking fig. 1 as an example, a first server and a second server are two servers connected to each other, where the first server and the second server have the same structure, in the first server, a first Baseboard Management Controller BMC1(Baseboard Management Controller) and a first platform path Controller PCH1(platform Controller Hub) share a link, specifically, the BMC1 and the PCH1 are connected to a first Network interface card NIC1(Network Information Center), and the NIC1 is connected to a first switch chip SW1, a first Physical Port Layer PHY1(Port Physical Layer) and a first terminal device in sequence; in the second server, the second BMC2 and the second platform path controller PCH2 share two links, specifically, the BMC2 and the PCH2 are connected to the second NIC2, and the NIC2 is connected to the second switch chip SW2, the second PHY layer PHY2 and the second terminal device in sequence. The NIC1 is connected to the NIC2, so as to enable the first server to communicate with the second server. Because the system network in the topology of the first server and the second server is complex, when the system network fails, the link blocking point is difficult to find in time, so that the problem positioning speed is reduced, and the debuggability of the system network is influenced.
In view of the above problems, embodiments of the present invention provide a debugging method, which can monitor the packet transceiving conditions between key chips on a network link of a system through a network management module, so as to confirm the on-off conditions and link blocking points of the entire link in time, thereby improving the debuggability of the system network.
Referring to fig. 2, a debugging method provided by the present invention is executed by the debugging system shown in fig. 2, a network management module for obtaining a package condition of each chip is disposed in a server motherboard, and the network management module may be a Complex Programmable Logic Device (CPLD), or a Field Programmable Gate Array (FPGA) or other Programmable Logic chip, which is not limited in the embodiments of the present invention; the network management module is connected with the reset module, so that when the link is detected to be blocked, the blocked link can be restarted through the reset module, the network management module is further connected with a transceiver module, the transceiver module specifically comprises a serial port module and a wireless module, wherein the serial port module is used for exporting data of the network management module, the wireless module is used for carrying out wireless communication, the transceiver module enables the servers which are connected with each other to be mutually packaged and transmitted, and therefore the link blocking condition between the servers is monitored.
It should be noted that, in the network management module provided in the embodiment of the present application, the link connection manner monitored by the network management module is not limited to that shown in fig. 2, and any network management module may obtain the packet transceiving conditions between any two chips, which falls within the scope of the protection claimed in the embodiment of the present application.
For convenience of understanding, a specific flow of the debugging method in the embodiment of the present application is described below, and referring to fig. 3, an embodiment of the debugging method in the embodiment of the present application includes:
301. the first network management module acquires a change value of a first chip sending package and a change value of a second chip receiving package.
In this embodiment, the first chip sends a packet to the second chip, wherein the first chip is a chip for sending a packet, the second chip is a chip for receiving a packet, and any chip in the first server having a signal transceiving relationship can be used as a relationship between the first chip and the second chip; the first network management module may obtain the change value of each chip for receiving or sending packets through an MDC/MDIO management manner.
302. If the first network management module judges that the change value of the first chip sending the package is larger than the change value of the second chip receiving the package, the link between the first chip and the second chip is blocked.
In this embodiment, the first chip sends the packet to the second chip, and therefore, the variation value of the packet sent by the first chip should be equal to the variation value of the packet received by the second chip, specifically, when the link is clear, the variation value of the packet sent by the sending end of the first chip is equal to the variation value of the packet received by the receiving end of the second chip.
In this embodiment, the network management module obtains the variation value of the packet transmission and reception between the chips, and when the variation values of the packet transmission and reception between the two chips are different, it determines that the link between the two chips is blocked, so that the link can be monitored in real time according to the packet transmission and reception conditions, and the link blockage can be found in time.
It should be noted that the above-mentioned variation value of packet transceiving may be a quantity value of packet transceiving or a rate value of packet transceiving, and then, by taking an example of signal interaction between the BMC1 and the NIC1 in fig. 2, two cases of the network management module monitoring the quantity variation of packet transceiving and the network management module monitoring the rate variation of packet transceiving are described.
Firstly, the network management module monitors the quantity change of the packet receiving and sending.
In this embodiment, the first network management module monitors the link operation condition by monitoring the number change of packet generation between the first chip and the second chip, and for convenience of understanding, a specific flow of the debugging method in the embodiment of the present application is described below, please refer to fig. 4, where an embodiment of the debugging method in the embodiment of the present application includes.
401. The first network management module obtains the number of packets sent by the first chip in real time and the number of packets received by the second chip in real time.
In this embodiment, the first chip is responsible for sending, and the second chip is responsible for receiving, for example, the BMC1 sends packets to the NIC1, and at this time, the first network management module obtains the number of packets sent by the BMC1 in real time and the number of packets received by the NIC1 in real time.
402. If the first network management module judges that the number of packets sent by the first chip in real time is larger than the number of packets received by the second chip in real time, the link between the first chip and the second chip is blocked.
In this embodiment, since the first chip sends packets to the second chip, the number of packets sent by the first chip in real time should be the same as the number of packets received by the second chip in real time, and if the number of packets sent by the first chip is different from the number of packets received by the second chip in real time, it indicates that a link between the first chip and the second chip is blocked, and data damage occurs during packet transmission; for example, if the number of packets sent by the BMC1 in real time is 10 and the number of packets received by the NIC1 in real time is 5, it indicates that a link is blocked between the BMC1 and the NIC 1.
It should be noted that, in the above example of the BMC1 and the NIC1 sending and receiving packets, if the PCH1 also sends packets to the NIC1 at the same time, at this time, the PCH1 receives packets sent from the PCH1 and the BMC1 at the same time, the number of real-time received packets of the PCH1 is equal to the sum of real-time sent packets of the PCH1 and the BMC1, and if the number of real-time received packets of the PCH1 is greater than the sum of real-time sent packets of the PCH1 and the BMC1, it cannot be determined whether the link between the NIC1 and the BMC1 is blocked or the link between the NIC1 is blocked.
In view of the above situation, the embodiments of the present invention provide the following solutions.
Secondly, the network management module monitors the rate change of the packet receiving and sending.
In this embodiment, the first chip sends packets to the second chip, and the number of the first chip is two, so that when a link is blocked, it is difficult to determine which packet is a specific one of the two packets based on the number of the packets received and sent, and therefore the problem occurs. The first network management module detects the link condition by detecting the packet sending rate of the first chip and the packet sending rate of the second chip. For convenience of understanding, a specific flow of the debugging method in the embodiment of the present application is described below, and referring to fig. 5, an embodiment of the debugging method in the embodiment of the present application includes.
501. The first network management module obtains the rate of the first chip for sending the packets in real time and the rate of the second chip for receiving the packets in real time.
In this embodiment, the sum of the packet sending rates of the first chip is equal to the sum of the packet receiving rates of the second chip, for example, the packet sending rates of the PCH1 and the BMC1 are all 1 second and 2 packets, respectively, and the packet receiving rate of the NIC1 is 1 second and 3 packets are received.
502. If the first network management module judges that the rate of sending the packets by the first chip is greater than the rate of receiving the packets by the second chip, the link between the first chip and the second chip is blocked.
In this embodiment, for example, the packet sending rate of the PCH1 is 1 second to send 1 packet, and the packet sending rate of the BMC1 is 1 second to send 2 packets, in a normal operating state, the packet receiving rate of the second chip NIC1 is 1 second to receive 3 packets, and if the packet receiving rate of the second chip is less than 3 packets per 1 second, it indicates that a link between the second chip and the first chip is blocked, specifically, a link between the PCH1 and the NIC1 is blocked, and a link between the BMC1 and the NIC1 is blocked.
503. When the number of the first chips is multiple, if the first network management module judges that the reduction value of the packet receiving rate of the second chip is equal to the rate value of the packet sending rate of the target first chip, the link blockage between the second chip and the target first chip is confirmed, and the target first chip is one of the multiple first chips.
In this embodiment, for example, the packet sending rate of the PCH1 is 1 second to send 1 packet, and the packet sending rate of the BMC1 is 1 second to send 2 packets, so that under normal working conditions, the packet receiving rate of the NIC1 is 1 second to receive three packets; when the rate of receiving packets by the NIC1 becomes 1 second to receive 2 packets, the rate of receiving packets by the NIC1 is reduced by the amount equal to the rate of sending packets by the PCH1, so that the first network management module confirms that the link between the NIC1 and the PCH1 is blocked.
In this embodiment, the first network management module realizes the situation of locating the link congestion point when a plurality of first chips are connected to one second chip by changing the packet receiving and sending rates of the first chip and the second chip.
It should be noted that, in the foregoing situation, a method for real-time monitoring and fast positioning of a link congestion point by a first network module is introduced, and after the first network module locates the link congestion point, the first network module needs to reset the link congestion point to solve the problem of link congestion and ensure normal operation of a system network. For the sake of understanding, the following describes a specific flow of the present case, and referring to fig. 6, an embodiment of the debugging method in the embodiment of the present application includes.
Step 601-602 can refer to the above steps 301-302, which are not described herein again.
603. The first network management module box resetting module sends a request signal, and the request signal carries the blocking condition of the link.
In this embodiment, the request signal records the congestion point of a specific link congestion. For example, when the link between the NIC1 and the PCH1 is blocked, the request signal records the blocking condition and requests the reset module to reset the blocking condition.
604. The first network management module acquires a reset signal sent by the reset module.
In this embodiment, the reset signal carries a restart command, which is used for restarting the first chip and the second chip in which the link is blocked.
605. The first network management module sends a reset signal to the first chip and the second chip.
In this embodiment, after receiving the reset signal, the first chip and the second chip perform a restart according to the requirement of the restart command, thereby solving the problem of link congestion. For example, when the NIC1 and the PCH1 receive a reboot command carried in a reset signal, they are rebooted, and after the reboot, the link between the NIC1 and the PCH1 is restored to be clear, so that the system network can operate normally.
In this embodiment, the first network management module sends a restart signal to the chip in the blocked link through the reset module, thereby solving the problem of link blocking and ensuring normal operation of the system network.
It should be noted that, in the above situation, the network link blocking point of the server system can be located only inside one first server, and if there are multiple servers connected through a network card, the first network management module of the first server cannot acquire the situation of receiving and sending packets by the network card in the second server, so that monitoring of link blocking between the servers cannot be achieved.
701. The first network management module acquires a change value of a packet sent by the second chip to the third chip.
In this embodiment, the first server and the second server communicate with each other through the second chip and the third chip, and the second chip and the third chip may be network interface cards NIC.
For example, the second chip is a NIC1 disposed on the first server, the third chip is a NIC2 disposed on the second server, the NCI1 is interconnected with the NIC2 via a SERializer/DESerializer (SERializer/DESerializer), and the NIC1 sends packets to the NIC 2; at this time, the first network management module obtains the change value of the packet sent by the NIC1 to the NIC 2.
702. The first network management module sends the change value of the package sent by the second chip to the third chip to the second network management module through the first transceiver module.
In this embodiment, the first network management module sends the change value of the packet sent by the second chip to the third chip to the second network management module through the transceiver module, so that the second network management module can know the packet sending condition of the second chip; the transceiver module is a first transceiver module disposed on a first server, and specifically includes a first serial module and a first wireless module, where the first serial module has a function of importing/exporting data, and in this embodiment, is used to export data acquired by a first network management module, and the first wireless module has a function of wireless transceiving, and in this embodiment, is used to send data exported by the first serial module.
For example, the first network management module obtains the change value of the packet sent by the NIC1 to the NIC2, and the first serial module derives the change value of the packet sent by the NIC1 to the NIC2 and sends the result to the first wireless module for sending.
703. The second network management module receives the change value of the package sent by the second chip to the third chip through the second transceiver module.
In this embodiment, the second transceiver module includes a second serial module and a second wireless module, where the second wireless module has a function of wireless transceiving, and in this embodiment, the second transceiver module is configured to receive a change value of a packet sent by the second chip to the third chip from the first wireless module, and then send the change value to the second serial module; the second serial port module has a function of importing/exporting data to/from the second network management module, and in this embodiment, the second serial port module imports a change value of a packet sent by the second chip to the third chip into the second network management module.
For example, the second wireless module receives a change value of a packet sent by the NIC1 sent by the first wireless module to the NIC2, and then the second wireless module sends the received change value to the second serial module, and the second serial module imports the change value into the second network management module.
704. The second network management module obtains the change value of the third chip receiving the packet sent by the second chip.
In this embodiment, the second network management module may obtain the change value of the third chip receive packet through an MDC/MDIO management manner.
For example, the second network management module obtains the changed value of the packet received by the NIC 2.
705. And if the second network management module judges that the change value of the packet sent by the second chip to the third chip is greater than the change value of the packet sent by the second chip and received by the third chip, judging the link between the second chip and the third chip is blocked.
In this embodiment, the change value of the packet sent by the second chip to the third chip is sent by the first network management module to the second network management module, and the change value of the packet sent by the third chip to the second chip is obtained by the second network module from the third chip.
For example, the first network management module sends a change value of a packet sent by the NIC1 to the NIC2 to the second transceiver module through the first transceiver module, the second transceiver module sends the change value of the packet sent by the NIC1 to the NIC2 to the second network management module, the second network management module is connected to the NIC2 and obtains the change value of the packet sent by the NIC1 received by the NIC2, and when the second network management module determines that the change value of the packet sent by the NIC1 to the NIC2 is greater than the change value of the packet sent by the NIC2 received by the NIC1, it is determined that a link is blocked between the NIC1 and the NIC 2.
In this embodiment, the first network management module and the second network management module are connected through the wireless transceiver module, so that the scheme for determining link congestion by monitoring packet transceiving changes provided by the embodiment of the present invention can be used in communication between servers.
It should be noted that the packet change value between the servers may be a change in the number of packet transceiving or a change in the packet transceiving rate, and specific embodiments may refer to steps 401 to 402 and steps 501 to 503, respectively, which are not described herein again.
The above-mentioned scheme provided by the embodiment of the present application is introduced mainly from the perspective of interaction between each chip and the network management module. It is understood that the debugging system includes hardware structures and/or software modules for performing the functions in order to realize the functions. Those of skill in the art will readily appreciate that the various illustrative modules and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
Described in terms of hardware structures, the debugging method may be implemented by one entity device, may also be implemented by multiple entity devices together, and may also be a logic function module in one entity device, which is not specifically limited in this embodiment of the present application.
For example, the debugging method described above may be implemented by the communication device in fig. 8. Fig. 8 is a schematic hardware structure diagram of a communication device according to an embodiment of the present application. The communication device includes at least one processor 801, communication lines 802, memory 803, and at least one communication interface 804.
The processor 801 may be a general-purpose Central Processing Unit (CPU), a microprocessor, an application-specific integrated circuit (server IC), or one or more ICs for controlling the execution of programs in accordance with the present invention.
The communication link 802 may include a path for transmitting information between the aforementioned components.
The communication interface 804 may be any device, such as a transceiver, for communicating with other devices or communication networks, such as an ethernet, a Radio Access Network (RAN), a Wireless Local Area Network (WLAN), etc.
The memory 803 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact-disc-only memory (CD-ROM) or other optical disk storage, optical disk storage (including compact disk, laser disk, optical disk, digital versatile disk, blu-ray disk, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory may be separate and coupled to the processor via a communication line 802. The memory may also be integral to the processor.
The memory 803 is used for storing computer-executable instructions for executing the present invention, and is controlled by the processor 801. The processor 801 is configured to execute computer-executable instructions stored in the memory 803, thereby implementing the method for billing management provided by the embodiments described below in the present application.
Optionally, the computer-executable instructions in the embodiments of the present application may also be referred to as application program codes, which are not specifically limited in the embodiments of the present application.
In particular implementations, processor 801 may include one or more CPUs such as CPU0 and CPU1 in fig. 8, for example, as an example.
In particular implementations, the communication device may include multiple processors, such as processor 801 and processor 807 in fig. 8, for example, as an example. Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. A processor herein may refer to one or more devices, circuits, and/or processing cores for processing data (e.g., computer program instructions).
In particular implementations, the communication device may also include an output device 805 and an input device 806, as one embodiment. The output device 805 is in communication with the processor 801 and may display information in a variety of ways. For example, the output device 805 may be a Liquid Crystal Display (LCD), a Light Emitting Diode (LED) display device, a Cathode Ray Tube (CRT) display device, a projector (projector), or the like. The input device 806 is in communication with the processor 801 and may receive user input in a variety of ways. For example, the input device 806 may be a mouse, a keyboard, a touch screen device, or a sensing device, among others.
The communication device may be a general purpose device or a dedicated device. In a specific implementation, the communication device may be a desktop, a laptop, a web server, a Personal Digital Assistant (PDA), a mobile phone, a tablet, a wireless terminal device, an embedded device, or a device with a similar structure as in fig. 8. The embodiment of the application does not limit the type of the communication equipment.
In the embodiment of the present application, the user plane function network element and the user plane function network element may be divided according to the above method example, for example, each function unit may be divided corresponding to each function, or two or more functions may be integrated in one processing unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit. It should be noted that the division of the unit in the embodiment of the present application is schematic, and is only a logic function division, and there may be another division manner in actual implementation.
For example, in a case that each functional unit is divided in an integrated manner, the debugging system provided in the embodiment of the present application includes:
the first server comprises a first network management module, a first chip and a second chip;
wherein the first network management module is configured to:
acquiring a change value of a packet sent by the first chip and a change value of a packet received by the second chip, wherein the first chip sends the packet to the second chip;
if the change value of the first chip sending the package is larger than the change value of the second chip receiving the package, judging the link between the first chip and the second chip is blocked.
Optionally, the first server further includes a reset module, and the first network management module is further configured to:
acquiring a reset signal sent by a reset module, wherein the reset signal is used for restarting the first chip and the second chip;
and sending the reset signal to the first chip and the second chip.
Optionally, the second server includes a second network management module and a third chip connected to each other, and the third chip is connected to the second chip;
the first network management module is further configured to:
acquiring a change value of a packet sent by the second chip to the third chip;
sending the change value of the package sent by the second chip to the third chip to the second network management module through the transceiver module;
correspondingly, the second network management module is configured to:
acquiring a change value of the third chip receiving the second chip sending package;
and if the change value of the packet sent by the second chip to the third chip is larger than the change value of the packet sent by the second chip and received by the third chip, judging the link between the second chip and the third chip is blocked.
Optionally, the variation value is a magnitude of packet transceiving or a rate of packet transceiving.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product.
The computer program product includes one or more computer instructions. The procedures or functions described in accordance with the embodiments of the invention are generated in whole or in part when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that a computer can store or a data storage device, such as a server, a data center, etc., that is integrated with one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
Those skilled in the art will appreciate that all or part of the steps in the methods of the above embodiments may be implemented by associated hardware instructed by a program, which may be stored in a computer-readable storage medium, and the storage medium may include: ROM, RAM, magnetic or optical disks, and the like.
The debugging method, the debugging system and the storage medium provided by the embodiment of the invention are described in detail, a specific example is applied in the text to explain the principle and the implementation of the invention, and the description of the embodiment is only used for helping to understand the method and the core idea of the invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims (8)

1. A debugging method, comprising:
the method comprises the steps that a first network management module obtains a change value of a first chip sending package and a change value of a second chip receiving package, wherein the first chip sends the package to the second chip;
if the first network management module judges that the change value of the packet sent by the first chip is larger than the change value of the packet received by the second chip, judging that a link between the first chip and the second chip is blocked;
when the number of the first chips is multiple, if the first network management module judges that the reduction value of the packet receiving rate of the second chip is equal to the rate value of the packet sending rate of the target first chip, determining that link blockage occurs between the second chip and the target first chip, wherein the target first chip is one of the multiple first chips;
the first network management module, the first chip and the second chip are arranged on a first server; the change value is a quantity value of packet receiving and sending or a rate value of packet receiving and sending.
2. The method of claim 1, wherein the first server further comprises a reset module, and after the determining that the link between the first chip and the second chip is blocked, the method further comprises:
the first network management module acquires a reset signal sent by a reset module, wherein the reset signal is used for restarting the first chip and the second chip;
the first network management module sends the reset signal to the first chip and the second chip.
3. The method of claim 1, further comprising a second server, the second server comprising a second network management module and a third chip connected to each other, the third chip being connected to the second chip; the method further comprises:
the first network management module acquires a change value of a packet sent by the second chip to a third chip;
the first network management module sends a change value of a packet sent by the second chip to the third chip to the second network management module through the transceiver module;
and if the second network management module judges that the change value of the packet sent by the second chip to the third chip is greater than the change value of the packet sent by the second chip received by the third chip, judging that a link between the second chip and the third chip is blocked.
4. A debugging system is characterized by comprising a first server, wherein the first server comprises a first network management module, a first chip and a second chip;
wherein the first network management module is configured to:
acquiring a change value of a packet sent by the first chip and a change value of a packet received by the second chip, wherein the first chip sends the packet to the second chip;
if the change value of the packet sent by the first chip is larger than the change value of the packet received by the second chip, judging the link between the first chip and the second chip is blocked;
when the number of the first chips is multiple, if the first network management module judges that the reduction value of the packet receiving rate of the second chip is equal to the rate value of the packet sending rate of the target first chip, determining that link blockage occurs between the second chip and the target first chip, wherein the target first chip is one of the multiple first chips;
the change value is a quantity value of packet receiving and sending or a rate value of packet receiving and sending.
5. The system of claim 4, wherein the first server further comprises a reset module, and the first network management module is further configured to:
acquiring a reset signal sent by a reset module, wherein the reset signal is used for restarting the first chip and the second chip;
and sending the reset signal to the first chip and the second chip.
6. The system of claim 4, further comprising a second server, the second server comprising a second network management module and a third chip connected to each other, the third chip being connected to the second chip;
the first network management module is further configured to:
acquiring a change value of a packet sent by the second chip to a third chip;
sending a change value of a packet sent by the second chip to the third chip to a second network management module through a transceiver module;
the second network management module is configured to:
acquiring a change value of the third chip receiving the package sent by the second chip;
and if the change value of the packet sent by the second chip to the third chip is larger than the change value of the packet sent by the second chip and received by the third chip, judging the link between the second chip and the third chip is blocked.
7. A server device, characterized in that the server device comprises: an interaction device, an input/output (I/O) interface, a processor, and a memory having program instructions stored therein;
the interaction device is used for acquiring an operation instruction input by a user;
the processor is configured to execute program instructions stored in the memory to perform the method of any of claims 1-3.
8. A computer-readable storage medium comprising instructions that, when executed on a computer device, cause the computer device to perform the method of any of claims 1-3.
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