CN110021704B - Resistive random access memory device - Google Patents

Resistive random access memory device Download PDF

Info

Publication number
CN110021704B
CN110021704B CN201811469807.4A CN201811469807A CN110021704B CN 110021704 B CN110021704 B CN 110021704B CN 201811469807 A CN201811469807 A CN 201811469807A CN 110021704 B CN110021704 B CN 110021704B
Authority
CN
China
Prior art keywords
layer
electrode contact
material layer
electrode
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811469807.4A
Other languages
Chinese (zh)
Other versions
CN110021704A (en
Inventor
莫竣杰
郭仕奇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110021704A publication Critical patent/CN110021704A/en
Application granted granted Critical
Publication of CN110021704B publication Critical patent/CN110021704B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H10B63/845—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays the switching components being connected to a common vertical conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
    • H10N70/245—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies the species being metal cations, e.g. programmable metallization cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8825—Selenides, e.g. GeSe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/023—Formation of the switching material, e.g. layer deposition by chemical vapor deposition, e.g. MOCVD, ALD
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/021—Formation of the switching material, e.g. layer deposition
    • H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering

Abstract

An embodiment of the present invention provides a memory cell, including: a first electrode contact formed in a cylindrical shape extending in a first direction; a resistive material layer including a first portion extending in a first direction and surrounding the first electrode contact; and a second electrode contact connected to the resistive material layer, wherein the second electrode contact surrounds the first electrode contact and the first portion of the resistive material layer.

Description

Resistive random access memory device
Technical Field
Embodiments of the invention relate generally to the field of semiconductors, and more particularly, to resistive random access memory devices.
Background
In recent years, non-conventional non-volatile memory (NVM) devices such as Ferroelectric Random Access Memory (FRAM) devices, phase-change random access memory (PRAM) devices, and Resistive Random Access Memory (RRAM) devices have emerged. In particular, RRAM devices that exhibit switching behavior between a high resistance state and a low resistance state have various advantages over conventional NVM devices. These advantages include, for example, fabrication steps compatible with current Complementary Metal Oxide Semiconductor (CMOS) technology, low cost fabrication, compact structure, flexible scalability, fast switching, high integration density, etc.
As Integrated Circuits (ICs) including such RRAM devices are expected to be more powerful, it is desirable to maximize the number of RRAM devices in the IC accordingly. Generally, RRAM devices include a top electrode (e.g., an anode) and a bottom electrode (e.g., a cathode) with a layer of variable resistance material therebetween. Forming RRAM devices in such a stacked configuration may encounter limitations in maximizing the number of RRAM devices in an IC, since the number can only be increased two-dimensionally. In other words, the number of RRAM devices is greatly limited within a given area on an IC. Thus, the existing RRAM devices and methods of fabricating the same are not entirely satisfactory.
Disclosure of Invention
According to an aspect of the present invention, there is provided a memory cell comprising: a first electrode contact formed in a cylindrical shape extending in a first direction; a resistive material layer including a first portion extending along the first direction and surrounding the first electrode contact; and a second electrode contact, wherein the second electrode contact surrounds the first electrode contact and the first portion of the resistive material layer when viewed from top to bottom.
According to another aspect of the present invention, there is provided a memory cell comprising: a first electrode contact formed in a cylindrical shape extending in a first direction; a resistive material layer surrounding the first electrode contact, wherein the resistive material layer includes a first portion extending in the first direction and a second portion extending in a second direction; and a second electrode contact surrounding the resistive material layer, wherein the second electrode contact is connected to both the first portion of the resistive material layer and the second portion of the resistive material layer.
According to still another aspect of the present invention, there is provided a memory device including: a first memory cell and a second memory cell sharing a common electrode contact, wherein the first memory cell comprises: a first portion of the common electrode contact; a first resistive material layer including a first portion surrounding a first portion of the common electrode contact; and a first electrode contact including at least a portion surrounding a first portion of the common electrode contact and a first portion of the first resistance material layer, and wherein the second memory cell includes: a second portion of the common electrode contact; a second resistive material layer including a first portion surrounding a second portion of the common electrode contact; and a second electrode contact including at least a portion surrounding the second portion of the common electrode contact and the first portion of the second resistance material layer.
Drawings
The various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A-1C illustrate a flow diagram of an exemplary method for forming a semiconductor device, according to some embodiments.
Fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, and 2O illustrate cross-sectional views of an exemplary semiconductor device during various stages of fabrication fabricated by the method of fig. 1, in accordance with some embodiments.
Fig. 3 illustrates an example in which the exemplary semiconductor device of fig. 2A-2O is connected to one or more transistors, according to some embodiments.
Fig. 4 illustrates respective top views of the exemplary semiconductor device of fig. 3, in accordance with some embodiments.
Fig. 5 illustrates an alternative structure of the exemplary semiconductor device of fig. 2A-2O, in accordance with some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Also, spatially relative terms such as "below 8230; below", "8230; below", "lower", "above", "upper", and the like may be used herein for ease of description to describe one element or component's relationship to another (or other) element or component as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
Various embodiments of novel RRAM devices and methods of forming the same are provided. In some embodiments, the disclosed RRAM devices include a plurality of RRAM bit cells that are integrated in three dimensions (i.e., laterally and vertically integrated). For example, a subset of the plurality of RRAM bit cells are vertically integrated, and a plurality of such subsets may be further laterally integrated to form a three-dimensional integrated RRAM device. More specifically, in some embodiments, along one of such integrated columns, the common electrode contact is formed to have a cylindrical shape, and each of the plurality of RRAM bit cells integrated along the integrated column includes a respective layer of variable resistance material surrounding a respective portion of the common electrode contact and a respective horizontal electrode contact. In this way, the first plurality of RRAM bit-cells may be vertically integrated by the common electrode contact, while the second plurality of RRAM bit-cells may be laterally integrated by the horizontal electrode contact.
Fig. 1A, 1B, and 1C illustrate a flow diagram of a method 100 of forming a semiconductor device in accordance with one or more embodiments of the present invention. It should be noted that the method 100 is merely an example and is not intended to limit the present invention. In some embodiments, the semiconductor device is at least part of a RRAM device. As used herein, a RRAM device refers to any device that includes a layer of variable resistance material. It should be understood that the method 100 of fig. 1A, 1B, and 1C does not produce a complete RRAM device. The complete RRAM device can be fabricated using Complementary Metal Oxide Semiconductor (CMOS) technology processing. Accordingly, it should be understood that additional operations may be provided before, during, and/or after the method 100 of fig. 1A, 1B, and 1C, and thus some other operations may only be briefly described herein.
Referring first to fig. 1A, in some embodiments, a method 100 begins with operation 102 in which a substrate having at least conductive components (e.g., a source, drain, and/or gate electrode of a transistor) is provided. The method 100 continues to operation 104, where a first pseudo-cylinder is formed. In some embodiments, the first pseudo-cylinder is aligned with (e.g., connected to) the conductive member. In some embodiments, the first dummy cylinders extend in a vertical direction perpendicular to the main surface of the substrate, so that corners may be formed at intersections of sidewalls of the first dummy cylinders and the main surface of the substrate. Further, when viewed from the top, according to some embodiments, the first pseudo cylinder has a cross-section in one of various shapes, such as a circle, a polygon, and the like.
The method 100 continues with operation 106, where a first electrode layer is formed over the first pseudo-cylinder and the substrate. The method 100 continues with operation 108, where a layer of variable resistance material is formed over the first electrode layer. The method 100 continues with operation 110 in which a second electrode layer is formed over the variable resistance material layer. In some embodiments, the first electrode layer, the variable resistance material layer, and the second electrode layer formed at operations 106, 108, and 110, respectively, are all substantially conformal and thin. As such, each of the first electrode layer, the variable resistance material layer, and the second electrode layer may surround the first pseudo-cylinder, and more particularly, may conform to the contours of the aforementioned corners, which will be discussed in further detail below. The method 100 continues with operation 112, where the first electrode layer, the variable resistance material layer, and the second electrode layer are patterned. In this way, part of the main surface of the substrate is exposed again. The method 100 continues with operation 114 in which an isolation layer is formed over the substrate. In some embodiments, the isolation layer covers a top surface of the second electrode layer including the recess, and further covers the re-exposed major surface of the substrate.
Referring then to fig. 1B, the method 100 continues with operation 116 in which a dielectric layer is formed over the first isolation layer. In some embodiments, an optional anti-reflective coating (ARC) layer may be formed over the dielectric layer. The method 100 continues with operation 118 in which a recessed region is formed within the dielectric layer. In some embodiments, forming such a recessed region may again expose a portion of the second electrode layer including the top surface of the above-described recess. The method 100 continues with operation 120 in which a first electrode contact is formed in the recessed region. In some embodiments, the first electrode contact is formed by refilling the recessed region with a conductive material, such as copper (Cu). Thus, the first electrode contact is connected to the recessed portion of the second electrode layer, and the first electrode contact surrounds the second electrode layer when viewed from the top.
According to some embodiments of the invention, from operations 104 through 120, the first RRAM resistor may be partially formed. In other words, the first partially formed RRAM resistor includes a first electrode layer, a first variable resistance material layer, and a second electrode layer, and a first electrode contact, all of which are formed in a single layer. Thus, in some embodiments, the layer in which the first partially formed RRAM resistor (and subsequent first completed RRAM resistor) is formed is referred to herein as the "first layer".
The method 100 continues with operation 122, where a first layer of spacer layers and dummy layers are formed over the substrate. In some embodiments, a first layer of spacer layer may be first formed over the re-exposed top surface of the first dummy cylinder and the first electrode contact, and then a dummy layer may be formed over the first layer of spacer layer. The method 100 continues to operation 124, where a second pseudo-cylinder is formed. In some embodiments, the second dummy cylinders are formed by patterning the dummy layer and are vertically aligned with the first dummy cylinders. The method 100 continues to operation 126, where operations 106 through 124 are repeated. As such, in some embodiments, one or more partially formed RRAM bit cells may be formed in respective "layers" located above the first layer, wherein each of the one or more partially formed RRAM bit cells includes a respective pseudo-cylinder surrounded by respective first, variable resistance material and second electrode layers and respective first electrode contacts, which will be discussed in further detail below.
Referring then to FIG. 1C, the method 100 continues to operation 128, where the first pseudo-cylinder and subsequently formed pseudo-cylinders are removed. In some embodiments, the pseudo-cylinders formed in the respective layer are removed such that the conductive features in the substrate and the respective inner sidewalls of the first electrode layer across the layer are again exposed. The method 100 continues with operation 130, where a common electrode contact is formed. In some embodiments, a common electrode contact may be used as a respective second electrode contact for each RRAM bitcell spanning the layer.
In some embodiments, the operations of the method 100 may be associated with cross-sectional views of the semiconductor device 200 at various stages of fabrication as shown in fig. 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J, 2K, 2L, 2M, 2N, and 2O, respectively. In some embodiments, the semiconductor device 200 may be a RRAM device. RRAM device 200 may be included in a microprocessor, memory cell, and/or other Integrated Circuit (IC). Also, fig. 2A to 2O are simplified for better understanding of the concept of the present invention. For example, although the RRAM device 200 is shown in the figures, it should be understood that the IC in which the RRAM device 200 is formed may include many other devices, including resistors, capacitors, inductors, fuses, etc., and not shown in fig. 2A-2O for clarity of illustration.
Corresponding to operation 102 of fig. 1A, fig. 2A is a cross-sectional view of RRAM 200 including a substrate 202 having a conductive feature 204 provided at one of various stages of fabrication, in accordance with some embodiments. Although the RRAM device 200 in the illustrated embodiment of fig. 2A includes only one conductive feature 204, it should be understood that the illustrated embodiment of fig. 2A and the following figures are for illustration purposes only. Accordingly, RRAM device 200 may include any desired number of conductive features while remaining within the scope of the present invention.
In some embodiments, substrate 202 comprises a substrate of semiconductor material, such as silicon. Alternatively, the substrate 202 may comprise other elemental semiconductor materials such as, for example, germanium. The substrate 202 may also include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate 202 may include an alloy semiconductor such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, and indium gallium phosphide. In one embodiment, substrate 202 comprises an epitaxial layer. For example, the substrate may have an epitaxial layer located over a bulk semiconductor. Further, the substrate 202 may include a semiconductor-on-insulator (SOI) structure. For example, the substrate may include a Buried Oxide (BOX) layer formed by a process such as separation by implantation of oxygen (SIMOX) or other suitable techniques such as wafer bonding and grinding.
In the above-described embodiments in which the substrate 202 comprises a semiconductor material, the conductive feature 204 may be a source, drain, or gate electrode of a transistor. Alternatively, the conductive feature 204 may be a silicide feature disposed on the source, drain, or gate electrode. The silicide features may be formed by a self-aligned silicidation (commonly referred to as "silicidation") technique.
In some other embodiments, the substrate 202 is a dielectric material substrate formed over various device components (e.g., source, drain, or gate electrodes of transistors). Such a dielectric material substrate 202 may include at least one of silicon oxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low-k material may include Fluorinated Silicate Glass (FSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO) x C y )、Black
Figure BDA0001890654410000071
(applied materials of Santa Clara California), xerogel, aerogel, amorphous fluorocarbon, parylene, BCB (bis-benzocyclobutene),
Figure BDA0001890654410000072
(dow chemical company, milan, michigan), polyimide, and/or other future-developed low-k dielectric materials.
In such embodiments where the substrate 202 includes a dielectric material, the conductive features 204 may be horizontal or vertical conductive structures formed within the substrate 202. In general, the substrate 202 may be referred to as an "initial metallization layer" or "initial layer". For example, the conductive features 204 may be interconnect structures (i.e., horizontal conductive structures), or via structures (i.e., vertical conductive structures). Thus, the conductive features 204 may be electrically connected to device components of the transistor (e.g., source, drain, or gate components of the transistor) disposed below the layer provided with the substrate 202. In some embodiments, the conductive features 204 may be formed of a metallic material (e.g., copper (Cu), aluminum (Al), tungsten (W), etc.).
Fig. 2B is a cross-sectional view of RRAM device 200 including first dummy cylinder 206 formed at one of various stages of fabrication, corresponding to operation 104 of fig. 1A, in accordance with some embodiments. As shown, the first dummy cylinders 206 protrude beyond the main surface 203 of the substrate 202 and extend in a vertical direction perpendicular to the main surface 203 of the substrate 202. Accordingly, in some embodiments, a corner 207 may be formed at the intersection of the sidewall 206S of the first pseudo cylinder 206 and the major surface 203 of the substrate 202. Further, in some embodiments, the first dummy cylinder 206 is laterally aligned with the conductive member 204 such that at least a portion of the first dummy cylinder 206 is formed in direct contact with the conductive member 204.
In some embodiments, first pseudo-cylinder 206 may include a cross-section in any of a variety of shapes, such as a circle, a polygon, and so on. In other words, when viewed from the top, the first pseudo cylinder 206 takes one of the above-described shapes. Thus, in some embodiments, the corner 207 around the first pseudo-cylinder 206 may conform to the shape of the first pseudo-cylinder 206, which will be discussed in further detail below. In some embodiments, first dummy cylinders 206 may have an aspect ratio (width/height) of about 0.01 to about 0.5. In examples where the first dummy cylinders 206 have a circular cross-section, the first dummy cylinders 206 may have a diameter of about 10nm to about 70nm and a height of about 200 nm.
In some embodiments, the first dummy cylinders 206 may be formed of an oxide material (e.g., silicon oxide). In some embodiments, the first dummy cylinders 206 are formed by performing at least some of the following processes: depositing an oxide material over the substrate 202 and the conductive feature 204 using Chemical Vapor Deposition (CVD), high Density Plasma (HDP) CVD, physical Vapor Deposition (PVD), spin coating, and/or other suitable techniques; and performing one or more patterning processes (e.g., photolithography process, dry/wet etching process, cleaning process, soft/hard baking process, etc.) to form the first dummy cylinders 206.
Fig. 2C is a cross-sectional view of RRAM device 200 including first electrode layer 208 formed at one of various stages of fabrication, corresponding to operation 106 of fig. 1A, in accordance with some embodiments. As shown, the first electrode layer 208 is formed to cover the main surface 203 of the substrate 202 and the first dummy cylinders 206. In some embodiments, first electrode layer 208 is substantially conformal and thin (e.g., about 20 to 50nm thick), such that first electrode layer 208 may conform to the contours of corners 207 (i.e., extending vertically along sidewalls 206S of first dummy cylinders 206 and horizontally along major surface 203 of substrate 202). As such, first electrode layer 208 includes at least a horizontal portion 208-1 (along major surface 203) and a vertical portion 208-2 (along sidewall 206S) such that a top surface 208T of first electrode layer 208 exhibits a recess 208TC around corner 207. Further, although the portion of the first electrode layer 208 connected to the conductive feature 204 is shown in the illustrated embodiment of fig. 2C, it should be noted that the first electrode layer 208 may not be connected to the conductive feature 204.
In some embodiments, the first electrode layer 208 may be formed of: such as, for example, gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium Tin Oxide (ITO); or any alloy, oxide, nitride, fluoride, carbide, boride or silicide thereof, such as TaN, tiN, tiAlN, tiW; or a combination thereof. Although the first electrode layer 208 is shown as a single layer in the illustrative embodiment of fig. 2C (and the figures below), it should be noted that the first electrode layer 208 may comprise multiple layers formed as a stack, wherein each of the multiple layers is formed from one of the above-described materials, e.g., taN, tiN, etc. In some embodiments, the first electrode layer 208 is formed by depositing at least one of the above materials over the substrate 202 and the conductive feature 204 using Chemical Vapor Deposition (CVD), plasma Enhanced (PE) CVD, high Density Plasma (HDP) CVD, inductively Coupled Plasma (ICP) CVD, physical Vapor Deposition (PVD), spin coating, and/or other suitable techniques.
Fig. 2D is a cross-sectional view of RRAM device 200 including variable resistance material layer 210 formed at one of various stages of fabrication, in accordance with some embodiments, corresponding to operation 108 of fig. 1A. As shown, a variable resistance material 210 is formed to cover the first electrode layer 208. In some embodiments, the variable resistance material layer 210 is substantially conformal and thin (e.g., approximately 2-10 nm thick), such that the first variable resistance material layer 208 may conform to the contours of the corners 207 (i.e., extending vertically along the sidewalls 206S of the first dummy pillars 206 and extending horizontally along the major surface 203 of the substrate 202). As such, variable resistance material layer 210 includes at least horizontal portions 210-1 (along major surface 203) and vertical portions 210-2 (along sidewalls 206S) such that top surface 210T of variable resistance material layer 210 exhibits recesses 210TC around corners 207.
In some embodiments, the variable resistance material 210 is a layer having a resistance switching characteristic (e.g., variable resistance). In other words, variable resistance material layer 210 includes a material characterized by a reversible resistance change depending on the polarity and/or amplitude of the applied electrical pulse. The variable resistance material layer 210 includes a dielectric layer. Based on the polarity and/or amplitude of the electrical signal, variable resistance material layer 210 may become a conductor or an insulator.
In one embodiment, the variable resistance (material) layer 210 may include a transition metal oxide. The transition metal oxide may be represented as M x O y Wherein M is a transition metal, O is oxygen, x is a transition metal component, and y is an oxygen component. In an embodiment, variable resistance material layer 210 includes ZrO 2 . Examples of other materials suitable for variable resistance material layer 210 include: niO, tiO 2 、HfO、ZrO、ZnO、WO 3 、CoO、Nb 2 O 5 、Fe 2 O 3 、CuO、CrO 2 、SrZrO 3 (Nb-doped) and/or other materials known in the art. In another embodiment, the variable resistance (material) layer 210 may include a material such as, for example, pr 0.7 Ca 0.3 、MnO 3 And the like, giant magnetoresistance (CMR) based materials.
In yet another embodiment, the variable resistance (material) layer 210 may include a polymeric material such as, for example, polyvinylidene fluoride and poly [ (vinylidene fluoride-trifluoroethylene) (P (VDF/TrFE)). In yet another embodiment, variable resistance (material) layer 210 may comprise a Conductive Bridged Random Access Memory (CBRAM) material such as, for example, ag in GeSe (Ag in GeSe). According to some embodiments, the variable resistance material layer 210 may include a plurality of layers having resistance conversion material properties. The set voltage and/or the reset voltage of the variable resistance material layer 210 may be determined by the composition of the variable resistance material layer 210 (including the values of "x" and "y"), the thickness, and/or other factors known in the art.
In some embodiments, the variable resistance material layer 210 may be formed by an Atomic Layer Deposition (ALD) technique using precursors including a metal and oxygen. In some embodiments, other Chemical Vapor Deposition (CVD) techniques may be used. In some embodiments, variable resistance material layer 210 may be formed by a Physical Vapor Deposition (PVD) technique such as a sputtering process with a metal target and with oxygen and optionally nitrogen supplied to a PVD chamber. In some embodiments, the variable resistance material layer 210 may be formed by an electron beam deposition technique.
Fig. 2E is a cross-sectional view of the RRAM device 200 including the second electrode layer 212 provided at one of various stages of fabrication, corresponding to operation 110 of fig. 1A, according to some embodiments. As shown, the second electrode layer 212 is formed to cover the variable resistance material layer 210. In some embodiments, the second electrode layer 212 is substantially conformal and thin (e.g., approximately 20 to 50nm thick), such that the second electrode layer 212 may conform to the contours of the corners 207 (i.e., extending vertically along the sidewalls 206S of the first dummy cylinders 206 and horizontally along the major surface 203 of the substrate 202). As such, the second electrode layer 212 includes at least a horizontal portion 212-1 (along the major surface 203) and a vertical portion 212-2 (along the sidewall 206S) such that a top surface 212T of the second electrode layer 212 presents a recess 212TC around the corner 207.
In some embodiments, the second electrode layer may be formed of a substantially similar material as the first electrode layer 208. Accordingly, the second electrode layer 212 may be formed of: such as, for example, gold (Au), platinum (Pt), ruthenium (Ru), iridium (Ir), titanium (Ti), aluminum (Al), copper (Cu), tantalum (Ta), tungsten (W), iridium-tantalum alloy (Ir-Ta), indium Tin Oxide (ITO); or any alloy, oxide, nitride, fluoride, carbide, boride or silicide thereof, such as TaN, tiN, tiAlN, tiW; or a combination thereof. Although the second electrode layer 212 is shown as a single layer in the illustrative embodiment of fig. 2E (and the figures below), it should be noted that the first electrode layer 208 may comprise multiple layers formed as a stack, wherein each of the multiple layers is formed from one of the above-described materials, e.g., taN, tiN, etc. In some embodiments, second electrode layer 212 is formed by depositing at least one of the above materials over variable resistance material layer 210 using Chemical Vapor Deposition (CVD), plasma Enhanced (PE) CVD, high Density Plasma (HDP) CVD, inductively Coupled Plasma (ICP) CVD, physical Vapor Deposition (PVD), spin coating, and/or other suitable techniques.
Corresponding to operation 112 of fig. 1A, fig. 2F is a cross-sectional view of the RRAM device 200 at one of the various stages of fabrication in which the first electrode layer 208, the variable resistance material layer 210, and the second electrode layer 212 are patterned, according to some embodiments. According to some embodiments, the first electrode layer 208, the variable resistance material layer 210, and the second electrode layer 212 are patterned to leave a portion of the respective vertical portion and the respective horizontal portion intact.
More specifically, in some embodiments, vertical portions 208-2 of first electrode layer 208, vertical portions 210-2 of variable resistance material layer 210, and vertical portions 212-2 of second electrode layer 212, respectively, remain intact. And a portion of the horizontal portion 208-1 of the first electrode layer 208 (e.g., the horizontal portion connected to the vertical portion 208-2 and relatively close to the vertical portion 208-2) remains intact (hereinafter referred to as "remaining horizontal portion 208-1"); a part of the horizontal portion 210-1 of the variable resistance material layer 210 (for example, a horizontal portion connected to the vertical portion 210-2 and relatively close to the vertical portion 210-2) remains intact (hereinafter, referred to as "remaining horizontal portion 210-1"); and a portion of the horizontal portion 212-1 of the second electrode layer 212, for example, a horizontal portion connected to the vertical portion 212-2 and relatively close to the vertical portion 212-2, remains intact (hereinafter, referred to as "remaining horizontal portion 212-1"). In this way, the recess 212TC of the second electrode layer 212 may remain intact and again expose the main surface 203.
In some embodiments, the patterning process of the first electrode layer 208, the variable resistance material layer 210, and the second electrode layer 212 may include: a deposition process to form a patternable layer (e.g., a photoresist layer) over the substrate 202; a photolithography process to define a profile of the patternable layer; a dry/wet etch process to etch respective portions of the first electrode layer 208, the variable resistance material layer 210, and the second electrode layer 212 not covered by the defined profile of the patternable layer; a cleaning process and a soft/hard bake process.
Fig. 2G is a cross-sectional view of RRAM device 200 including isolation layer 214 formed at one of various stages of fabrication, corresponding to operation 114 of fig. 1A, in accordance with some embodiments. As shown, an isolation layer 214 is formed to cover the first electrode layer 208, the variable resistance material layer 210, the second electrode layer 212, and the substrate 202.
In some embodiments, the isolation layer 214 may be silicon carbide, silicon oxynitride, silicon nitride, carbon-doped silicon nitride, or carbon-doped silicon oxide. The isolation layer 214 is selected to have a different etch selectivity than the dielectric layer 216, as will be discussed below. A Chemical Vapor Deposition (CVD) technique, such as a Plasma Enhanced (PE) CVD, high Density Plasma (HDP) CVD, inductively Coupled Plasma (ICP) CVD, or thermal CVD technique, is used to deposit an isolation layer 214 over the first electrode layer 208, the variable resistance material layer 210 and the second electrode layer 212 and the substrate 202.
Fig. 2H is a cross-sectional view of RRAM device 200 including dielectric layer 216 formed at one of various stages of fabrication, in accordance with some embodiments, corresponding to operation 116 of fig. 1B. As shown, a dielectric layer 216 is formed to cover the isolation layer 214. In some embodiments, the thickness of the dielectric layer 216 (e.g., about 300 to 400 nm) is substantially higher than the height of the first electrode layer 208, the variable resistance layer 210, the second electrode layer 212, and the isolation layer 214. In some embodiments, an anti-reflective coating (ARC) layer 217 may optionally be formed over the dielectric layer 216.
In some embodiments, the dielectric layer 216 may include at least one of silicon oxide, a low dielectric constant (low-k) material, other suitable dielectric materials, or a combination thereof. The low-k material may include Fluorinated Silicate Glass (FSG)) Phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), carbon-doped silicon oxide (SiO) x C y )、Black
Figure BDA0001890654410000121
(applied materials of Santa Clara California), xerogel, aerogel, amorphous fluorocarbon, parylene, BCB (bis-benzocyclobutene),
Figure BDA0001890654410000122
(dow chemical company, milan, michigan), polyimide, and/or other future-developed low-k dielectric materials. In some embodiments, a dielectric layer 216 is deposited over the isolation layer 214 using a Chemical Vapor Deposition (CVD) technique, such as a Plasma Enhanced (PE) CVD, high Density Plasma (HDP) CVD, inductively Coupled Plasma (ICP) CVD, or thermal CVD technique.
Fig. 2I is a cross-sectional view of RRAM device 200 including recessed region 218 formed at one of various stages of fabrication, corresponding to operation 118 of fig. 1B, in accordance with some embodiments. As shown, the recessed region 218 is formed to re-expose the recess 212TC of the top surface of the second electrode layer 212 (i.e., re-expose the respective top and vertical portions 212-2 of the remaining horizontal portion 212-1) and to expose the recessed top surface 216R of the dielectric layer 216. When viewed from the top, in some embodiments, recessed region 218 may surround first dummy cylinder 206, vertical portion 208-2 of first electrode layer 208, vertical portion 210-2 of variable resistance material layer 210, and vertical portion 212-2 of second electrode layer 212.
In some embodiments, the recessed region 218 is formed by performing at least some of the following processes: performing a polishing process (e.g., a Chemical Mechanical Polishing (CMP) process) on the dielectric layer 216, the isolation layer 214, the second electrode layer 212, the variable resistance material layer 210, and the respective portions of the first electrode layer 208 until the top surfaces 206T of the first dummy cylinders 206 are exposed again; forming a patternable layer 220 (e.g., a photoresist layer) having a plurality of openings 221, as shown in fig. 2I; while using the patternable layer 220 as a mask, performing one or more dry etch processes to remove portions of the isolation layer 214 that cover the recesses 212TC and portions of the dielectric layer 216 that are not covered by the patternable layer 220; and removing the patternable layer 220.
Corresponding to operation 120 of fig. 1B, fig. 2J is a cross-sectional view of RRAM device 200 including first electrode contact 222 formed at one of various stages of fabrication, according to some embodiments. In some embodiments, the first electrode contact 222 may be formed by refilling the recessed region 218 (fig. 2I) with a metallic material, e.g., copper (Cu). As such, according to some embodiments, the first electrode contact 222 may surround the first dummy cylinder 206, the vertical portion 208-2 of the first electrode layer 208, the vertical portion 210-2 of the variable resistance material layer 210, and the vertical portion 212-2 of the second electrode layer 212 when viewed from the top. In addition, the first electrode contact 222 directly contacts the second electrode layer 212 (i.e., directly contacts the remaining horizontal portion 212-1 and vertical portion 212-2 of the second electrode layer 212) via the recess 212TC.
In some embodiments, after forming the first electrode contact 222, the first layer may be formed accordingly. Such a first layer includes a first partially formed RRAM resistor formed by the first electrode layer 208, the variable resistance material layer 210, and the second electrode layer 212, and the first electrode contact 222. In embodiments where the conductive features 204 are formed in the dielectric material substrate 202, a first layer is disposed over the initial layer described above. As will be discussed in further detail below, the first electrode contact 222 may serve as one of the two electrode contacts of the first partially formed RRAM resistor and replace the first dummy cylinder 206 with a metallic material to serve as the other of the two electrode contacts to form the complete first RRAM resistor.
Fig. 2K is a cross-sectional view of RRAM device 200 formed at one of various stages of fabrication, in accordance with some embodiments, corresponding to operation 122 of fig. 1B, where RRAM device 200 includes first interlayer isolation layer 224 and dummy layer 226. As shown, a first layer of spacer layer 224 is formed to cover the first dummy cylinder 206, the first electrode layer 208, the variable resistance material layer 210, the second electrode layer 212, the first electrode contact 222, and the dielectric layer 216 (i.e., to cover the entire first layer); and then a dummy layer 226 is formed to cover the first interlayer insulating layer 224.
In some embodiments, first layer spacer layer 224 is formed of a material substantially similar to the material of spacer layer 214; and the dummy layer 226 is formed of a material substantially similar to that of the first dummy cylinder 206. Accordingly, the materials of the first interlayer spacing layer 224 and the dummy layer 226 will not be discussed again. In some embodiments, the first interlayer isolation layer 224 and the dummy layer 226 are formed using a Chemical Vapor Deposition (CVD) technique, such as a Plasma Enhanced (PE) CVD, a High Density Plasma (HDP) CVD, an Inductively Coupled Plasma (ICP) CVD, or a thermal CVD technique, respectively.
Corresponding to operation 124 of fig. 1B, fig. 2L is a cross-sectional view of RRAM device 200 including second dummy cylinder 228 formed at one of the various stages of fabrication, according to some embodiments. As shown, the second pseudo-cylinders 228 protrude beyond the major surface 225 of the first layer spacer layer 224 and extend in a perpendicular direction perpendicular to the major surface 225 of the first layer spacer layer 224. Similarly, in some embodiments, a corner 229 may be formed at the intersection of the sidewall 228S of the second pseudo-cylinder 228 and the major surface 225 of the first layer spacer layer 224. Furthermore, in some embodiments, second pseudo cylinder 228 is laterally aligned with first pseudo cylinder 206.
In some embodiments, similar to first pseudo-cylinder 206, second pseudo-cylinder 228 may include a cross-section in any of a variety of shapes, such as a circle, a polygon, and so on. In other words, when viewed from the top, the second pseudo-cylinder 228 takes one of the above-described shapes. Accordingly, in some embodiments, the corner 229 around the second pseudo-cylinder 228 may conform to the shape of the second pseudo-cylinder 228. In some embodiments, the second dummy cylinders 228 may have an aspect ratio (width/height) of about 0.01 to about 0.5. In an example where the second dummy cylinders 228 have a circular cross-section, the second dummy cylinders 228 may have a diameter of about 10nm to about 70nm and a height of about 200 nm.
Corresponding to operation 126 of fig. 1B, in which the above-described operations 106 through 124 are repeated, fig. 2M is a cross-sectional view of the RRAM device 200 at one of various stages of fabrication, in which the RRAM device 200 includes a second layer over the first layer and a third layer over the second layer, according to some embodiments. In some embodiments, additional layers are formed when one iteration of operations 106-124 is performed after forming the corresponding pseudo-cylinders (e.g., 206, 228, etc.). Since each additional layer above the first layer (e.g., second layer, third layer, etc.) is substantially similar to the first layer, a brief discussion of the second and third layers follows.
In the illustrated embodiment of fig. 2M, the second layer comprises a second pseudo-cylinder 228 surrounded by respective first 230, variable resistance material 232 and second 234 electrode layers. The second layer also includes a respective isolation layer 236, a dielectric layer 238 and a first electrode contact 240. In this way, a second partially formed RRAM resistor may be disposed at the second layer, wherein the second partially formed RRAM resistor is formed of the first electrode layer 230, the variable resistance material layer 232, the second electrode layer 234, and the first electrode contact 240 at the second layer. Over the second layer, a second interlayer insulating layer 244 is formed, and over the second interlayer insulating layer 244, a third layer is formed. The third layer includes a third pseudo cylinder 246 surrounded by respective first electrode layers 248, variable resistance material layers 250, and second electrode layers 252. The third layer also includes a respective isolation layer 254, dielectric layer 256, and first electrode contact 258. As such, the third partially formed RRAM resistor may be disposed at the third layer, wherein the RRAM resistor is formed of the first electrode layer 248, the variable resistance material layer 250, the second electrode layer 252, and the first electrode contact 258 at the third layer.
Corresponding to operation 128 of fig. 1C, fig. 2N is a cross-sectional view of RRAM device 200 at one of the various stages of fabrication according to some embodiments, with first dummy cylinder 206, second dummy cylinder 228, and third dummy cylinder 246 removed. As shown, the vertical trench 260 is formed after removing the first dummy cylinder 206, the second dummy cylinder 228, and the third dummy cylinder 246 and the corresponding portions (shown in dotted lines) of the interlayer insulating layers 224 and 244.
In some embodiments, the third dummy cylinders 246 are removed using a first wet etching process, the portions of the interlayer isolation layer 244 disposed under the third dummy cylinders 246 are removed using a first dry etching process, the second dummy cylinders 228 are removed using a second wet etching process, the portions of the interlayer isolation layer 224 disposed under the second dummy cylinders 228 are removed using a second dry etching process, and the first dummy cylinders 206 are removed using a third wet etching process. In this way, the top surface of the conductive member 204 is again exposed.
Corresponding to operation 130 of fig. 1C, fig. 2O is a cross-sectional view of RRAM device 200 including common electrode contact 262 formed at one of various stages of fabrication, according to some embodiments. As shown, the common electrode contact 262 is formed by refilling the vertical trench 260 (fig. 2N) with a metal material, e.g., copper (Cu), such that the common electrode contact 262 is electrically connected to the conductive member 204.
When viewed from the top, the common electrode contact 262 may be surrounded by a respective first electrode layer/variable resistance material layer/second electrode layer/first electrode contact at each layer, according to some embodiments. For example, at a first layer, the common electrode contact 262 is surrounded by the first electrode layer 208, the variable resistance material layer 210, the second electrode layer 212, and the first electrode contact 222; at the second layer, the common electrode contact 262 is surrounded by the first electrode layer 230, the variable resistance material layer 232, the second electrode layer 234, and the first electrode contact 240; and at the third layer, the common electrode contact 262 is surrounded by the first electrode layer 248, the variable resistance material layer 250, the second electrode layer 252, and the first electrode contact 258.
Furthermore, according to some embodiments, the common electrode contact 262 directly contacts, at each layer, a respective inner side wall of the first electrode layer, or more particularly, an inner side wall of a respective vertical portion of the first electrode layer. For example, at a first layer, the common electrode contact 262 directly contacts the inner sidewall 208-2S of the vertical portion 208-2 of the second electrode layer 208; at the second layer, the common electrode contact 262 directly contacts the inner sidewall 230-2S of the vertical portion 230-2 of the second electrode layer 230; and at the third layer, the common electrode contact 262 directly contacts the inner sidewall 248-2S of the vertical portion 248-2 of the second electrode layer 248.
As such, a first completed RRAM resistor is disposed at the first layer, wherein the first completed RRAM resistor is formed by respective portions of the common electrode contact 262, the first electrode layer 208, the variable resistance material layer 210, the second electrode layer 212, and the first electrode contact 222; providing a second completed RRAM resistor at the second layer, wherein the second completed RRAM resistor is formed of respective portions of the common electrode contact 262, the first electrode layer 230, the variable resistance material layer 232, the second electrode layer 234, and the first electrode contact 240; and disposing a third completed RRAM resistor at the third layer, wherein the third completed RRAM resistor is formed by respective portions of the common electrode contact 262, the first electrode layer 248, the variable resistance material layer 250, the second electrode layer 252, and the first electrode contact 258.
In some embodiments, at the circuit design level, the common electrode contact 262 may be connected to a Bit Line (BL), and the first electrode contacts 222/240/258 belonging to respective different RRAM resistors at the respective layers are each connected to a respective transistor, also referred to as a select transistor. Thus, as shown in fig. 3, a plurality of 1-transistor 1 resistor (1T 1R) RRAM bit cells may be formed.
In particular, fig. 3 reproduces the RRAM device 200 of fig. 2O, except that the first electrode contact 222 at the first layer further extends vertically through the second and third layers to connect the respective select transistors 302; the first electrode contact 240 at the second level further extends vertically through the third level to connect a respective select transistor 304; and the first electrode contact 258 at the third layer extends further to connect the corresponding select transistor 306. In some embodiments, the first RRAM resistor is connected to BL 308 through the common electrode contact 262 and to the drain or source feature of the select transistor 302 through the first electrode contact 222, forming a first 1t1r RRAM bit cell. Similarly, the second RRAM resistor is connected to BL 308 through common electrode contact 262 and to the drain or source feature of select transistor 304 through first electrode contact 240, forming a second 1t1r RRAM bit cell; the third RRAM resistor is connected to BL 308 through the common electrode contact 262 and to the drain or source feature of the select transistor 306 through the first electrode contact 258, forming a third 1t1r RRAM bit cell.
Although in fig. 3, the select transistors 302, 304, and 306 are shown disposed above these three layers, it is for illustration purposes only. In some embodiments, such select transistors 302, 304, and 306 may be formed below the layer in which the first, second, and third RRAM resistors are formed. Accordingly, the respective first electrode contacts 222/240/258 may be formed to extend further downward.
As described above, in existing RRAM devices and methods of forming the same, the maximum number of RRAM bitcells that can be integrated within a given area is limited because RRAM bitcells can only be integrated two-dimensionally. In sharp contrast, multiple RRAM bit cells can be integrated into the disclosed RRAM device (e.g., 200) in additional (e.g., vertical) directions through a common electrode contact (e.g., 262), thereby making it possible to greatly increase the maximum number of RRAM bit cells integrated into a given area. Furthermore, a plurality of such vertically integrated RRAM bitcells may be further laterally integrated by respective first electrode contacts (e.g., 222, 240, 258, etc.). As such, the total number of RRAM bitcells that may be integrated into the disclosed RRAM device may be further increased.
Fig. 4 illustrates a corresponding top view of RRAM device 200 illustrated in fig. 3 in accordance with some embodiments. Note that the top view of fig. 4 has been simplified for purposes of illustration, such that only the top view of the RRAM resistor of a RRAM bitcell at the third tier and the corresponding first electrode contact of the RRAM resistor of a RRAM bitcell at a lower tier are shown. In the embodiment shown in fig. 4, the third RRAM resistor (the common electrode contact 262, the first electrode layer 248, the variable resistance material layer 250, the second electrode layer 252, and the first electrode contact 258), the first electrode contact 240 of the second RRAM resistor, and the first electrode contact 222 of the first RRAM resistor are arranged along the first row. It should be understood that such rows may be repeated throughout RRAM device 200 to form an RRAM array. For example, a second row may be formed as shown in fig. 4, wherein the second row includes the common electrode contact 462, the first electrode layer 448, the variable resistance material layer 450, the second electrode layer 452 and the first electrode contact 458, and the first electrode contact 440 and the first electrode contact 422.
Fig. 5 illustrates an alternative structure of the RRAM device 200 shown in fig. 2O. For simplicity, an alternative structure for RRAM device 200 is referred to herein as "RRAM device 500". As shown, RRAM device 500 is substantially similar to RRAM device 200, except that the second electrode layer 212/234/252 at each layer has only a respective vertical portion 212-2/234-2/252-2.
In an embodiment, a memory cell includes: a first electrode contact formed in a cylindrical shape extending in a first direction; a resistive material layer including a first portion extending in a first direction and surrounding the first electrode contact; and a second electrode contact connected to the resistive material layer, wherein the second electrode contact surrounds the first electrode contact and the first portion of the resistive material layer.
In some embodiments, the layer of resistive material exhibits a variable resistance value.
In some embodiments, the electrical resistance material layer further includes a second portion extending in a second direction perpendicular to the first direction.
In some embodiments, the second portion of the electrical resistance material layer surrounds the first electrode contact.
In some embodiments, the second electrode contact extends along the second direction and is connected to both the first portion of the layer of resistive material and the second portion of the layer of resistive material.
In some embodiments, the memory cell further comprises: a first electrode layer comprising at least a portion connected between the first electrode contact and a first portion of the electrical resistance material layer; and a second electrode layer including at least a portion connected between the first portion of the resistance material layer and the second electrode contact.
In some embodiments, the at least part of the first electrode layer and the at least part of the second electrode layer both extend along the first direction.
In some embodiments, the memory cell further comprises: a transistor, wherein the second electrode contact is connected to a drain feature or a source feature of the transistor. In another embodiment, a memory cell includes: a first electrode contact formed in a cylindrical shape extending in a first direction; a resistive material layer surrounding the first electrode contact, wherein the resistive material layer includes a first portion extending in a first direction and a second portion extending in a second direction; and a second electrode contact surrounding the resistive material layer, wherein the second electrode contact is connected to the first portion and the second portion of the resistive material layer.
In some embodiments, the second direction is perpendicular to the first direction.
In some embodiments, the electrical resistance material layer exhibits a variable resistance value.
In some embodiments, the second electrode contact extends along the second direction.
In some embodiments, the memory cell further comprises: a transistor, wherein the second electrode contact is connected to a drain component or a source component of the transistor.
In some embodiments, the memory cell further comprises: a first electrode layer including a vertical portion connected between the first electrode contact and the first portion of the resistance material layer, and a second portion connected between the second portion of the resistance material layer and the substrate; and a second electrode layer including a vertical portion connected between the first portion of the resistance material layer and the second electrode contact, and a horizontal portion connected between the second portion of the resistance material layer and the second electrode contact.
In yet another embodiment, a memory device includes: the first memory cell and the second memory cell share a common electrode contact, wherein the first memory cell comprises: a first portion of a common electrode contact; a first resistive material layer including a first portion surrounding a first portion of the common electrode contact; and a first electrode contact including at least a portion surrounding a first portion of the common electrode contact and a first portion of the first resistive material layer, and wherein the second memory cell includes: a second portion of the common electrode contact; a second resistance material layer including a first portion surrounding a second portion of the common electrode contact; and a second electrode contact including at least a portion surrounding the second portion of the common electrode contact and the first portion of the second resistance material layer.
In some embodiments, the first memory cell is disposed at a first level and the second memory cell is disposed at a second level above the first level.
In some embodiments, the memory device further comprises: an isolation layer disposed between the first layer and the second layer.
In some embodiments, the first and second layers of resistive material each exhibit a variable resistance value.
In some embodiments, the common electrode contact and the respective first portions of the first and second layers of resistive material each extend along a first direction.
In some embodiments, the first and second layers of electrical resistance material each include a second portion extending along a second direction substantially perpendicular to the first direction.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (20)

1. A memory cell, comprising:
a first electrode contact formed in a cylindrical shape extending in a first direction;
a resistive material layer including a first portion extending along the first direction and surrounding the first electrode contact;
a second electrode contact, wherein the second electrode contact surrounds the first electrode contact and a first portion of the resistive material layer when viewed from top to bottom,
a first electrode layer comprising at least a portion connected between the first electrode contact and a first portion of the electrical resistance material layer;
a second electrode layer comprising at least a portion connected between a first portion of the electrical resistance material layer and the second electrode contact; and
a transistor, each of the first and second electrode contacts connected to a drain portion or a source portion of the transistor.
2. The memory cell of claim 1, wherein the layer of resistive material exhibits a variable resistance value.
3. The memory cell of claim 1, wherein the resistive material layer further comprises a second portion extending in a second direction perpendicular to the first direction.
4. The memory cell of claim 3, wherein the second portion of the resistive material layer surrounds the first electrode contact.
5. The memory cell of claim 4, wherein the second electrode contact extends along the second direction and is connected to both the first portion of the resistive material layer and the second portion of the resistive material layer.
6. The memory cell of claim 1, wherein the first electrode layer has a thickness of 20 to 50nm.
7. The memory cell of claim 6, wherein the at least a portion of the first electrode layer and the at least a portion of the second electrode layer each extend along the first direction.
8. The memory cell of claim 1, the layer of resistive material having a thickness of 2-10 nm.
9. A memory cell, comprising:
a first electrode contact formed in a cylindrical shape extending in a first direction;
a resistive material layer surrounding the first electrode contact, wherein the resistive material layer includes a first portion extending in the first direction and a second portion extending in a second direction; and
a second electrode contact surrounding the resistive material layer, wherein the second electrode contact is connected to both the first portion of the resistive material layer and the second portion of the resistive material layer,
a first electrode layer including a vertical portion connected between the first electrode contact and the first portion of the resistance material layer, and a horizontal portion connected between the second portion of the resistance material layer and the substrate;
a second electrode layer including a vertical portion connected between the first portion of the resistance material layer and the second electrode contact, and a horizontal portion connected between the second portion of the resistance material layer and the second electrode contact; and
a transistor, wherein the second electrode contact is connected to a drain component or a source component of the transistor.
10. The memory cell of claim 9, wherein the second direction is perpendicular to the first direction.
11. The memory cell of claim 9, wherein the resistive material layer exhibits a variable resistance value.
12. The memory cell of claim 9, wherein the second electrode contact extends along the second direction.
13. The memory cell of claim 9, wherein the resistive material layer comprises a transition metal oxide.
14. The memory cell of claim 9, wherein the resistive material layer comprises ZrO 2 。
15. A memory device, comprising:
a first memory cell and a second memory cell, sharing a common electrode contact,
wherein the first memory cell comprises:
a first portion of the common electrode contact;
a first resistive material layer including a first portion surrounding a first portion of the common electrode contact;
a first electrode contact including at least a portion surrounding a first portion of the common electrode contact and a first portion of the first resistance material layer,
a first electrode layer including at least a portion connected between a first portion of the common electrode contact and a first portion of the first resistance material layer, and
a second electrode layer comprising at least a portion connected between a first portion of the first resistance material layer and a first electrode contact,
and wherein the second memory cell comprises:
a second portion of the common electrode contact;
a second resistive material layer including a first portion surrounding a second portion of the common electrode contact; and
a second electrode contact including at least a portion surrounding a second portion of the common electrode contact and a first portion of the second resistance material layer,
a transistor, each of the first and second electrode contacts connected to a drain portion or a source portion of the transistor.
16. The memory device of claim 15, wherein the first memory cell is disposed at a first level and the second memory cell is disposed at a second level above the first level.
17. The memory device of claim 16, further comprising:
an isolation layer disposed between the first layer and the second layer.
18. The memory device of claim 15, wherein the first resistive material layer and the second resistive material layer each exhibit a variable resistance value.
19. The memory device of claim 15, wherein the common electrode contact and the respective first portions of the first and second resistive material layers each extend along a first direction.
20. The memory device of claim 19, wherein the first resistive material layer and the second resistive material layer each include a second portion extending along a second direction perpendicular to the first direction.
CN201811469807.4A 2017-11-29 2018-11-28 Resistive random access memory device Active CN110021704B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201762592318P 2017-11-29 2017-11-29
US62/592,318 2017-11-29
US16/123,519 2018-09-06
US16/123,519 US10686129B2 (en) 2017-11-29 2018-09-06 Resistive random access memory device

Publications (2)

Publication Number Publication Date
CN110021704A CN110021704A (en) 2019-07-16
CN110021704B true CN110021704B (en) 2022-10-28

Family

ID=66442380

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811469807.4A Active CN110021704B (en) 2017-11-29 2018-11-28 Resistive random access memory device

Country Status (5)

Country Link
US (2) US10686129B2 (en)
KR (1) KR102206938B1 (en)
CN (1) CN110021704B (en)
DE (1) DE102018124810B4 (en)
TW (1) TWI745628B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11088203B2 (en) * 2019-07-29 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3D RRAM cell structure for reducing forming and set voltages
US11121315B2 (en) * 2020-01-03 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Structure improving reliability of top electrode contact for resistance switching RAM having cells of varying height
CN111640863B (en) * 2020-05-19 2023-12-19 厦门半导体工业技术研发有限公司 Semiconductor integrated circuit device and method for manufacturing the same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004103696A (en) * 2002-09-06 2004-04-02 Hitachi Ltd Semiconductor device
CN103022037A (en) * 2011-09-26 2013-04-03 瑞萨电子株式会社 Semiconductor memory device, semiconductor device and method of manufacturing semiconductor memory device
CN106935642A (en) * 2015-12-31 2017-07-07 北京大学 HEMT and memory chip
KR20170085411A (en) * 2016-01-14 2017-07-24 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Rram device with data storage layer having increased height
CN107230742A (en) * 2016-03-24 2017-10-03 台湾积体电路制造股份有限公司 MRAM device and forming method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100990143B1 (en) * 2008-07-03 2010-10-29 주식회사 하이닉스반도체 Magnetic tunnel junction device, memory cell having the same and method for manufacturing the same
US8013389B2 (en) * 2008-11-06 2011-09-06 Samsung Electronics Co., Ltd. Three-dimensional nonvolatile memory devices having sub-divided active bars and methods of manufacturing such devices
US9276041B2 (en) * 2012-03-19 2016-03-01 Globalfoundries Singapore Pte Ltd Three dimensional RRAM device, and methods of making same
US9601544B2 (en) * 2013-07-16 2017-03-21 Imec Three-dimensional magnetic memory element
US9768234B2 (en) 2014-05-20 2017-09-19 Crossbar, Inc. Resistive memory architecture and devices
US9305974B1 (en) * 2015-04-16 2016-04-05 Stmicroelectronics, Inc. High density resistive random access memory (RRAM)
US9978810B2 (en) 2015-11-04 2018-05-22 Micron Technology, Inc. Three-dimensional memory apparatuses and methods of use

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004103696A (en) * 2002-09-06 2004-04-02 Hitachi Ltd Semiconductor device
CN103022037A (en) * 2011-09-26 2013-04-03 瑞萨电子株式会社 Semiconductor memory device, semiconductor device and method of manufacturing semiconductor memory device
CN106935642A (en) * 2015-12-31 2017-07-07 北京大学 HEMT and memory chip
KR20170085411A (en) * 2016-01-14 2017-07-24 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Rram device with data storage layer having increased height
CN107230742A (en) * 2016-03-24 2017-10-03 台湾积体电路制造股份有限公司 MRAM device and forming method thereof

Also Published As

Publication number Publication date
US11158790B2 (en) 2021-10-26
TWI745628B (en) 2021-11-11
DE102018124810A1 (en) 2019-05-29
US10686129B2 (en) 2020-06-16
US20190165267A1 (en) 2019-05-30
CN110021704A (en) 2019-07-16
TW201926751A (en) 2019-07-01
KR102206938B1 (en) 2021-01-26
DE102018124810B4 (en) 2023-12-28
US20200313086A1 (en) 2020-10-01
KR20190063398A (en) 2019-06-07

Similar Documents

Publication Publication Date Title
CN109786549B (en) Resistive random access memory device
US20220344585A1 (en) Novel resistive random access memory device
US11611039B2 (en) Resistive random access memory device
US11950433B2 (en) Resistive random access memory device
US11158790B2 (en) Resistive random access memory device
TWI730475B (en) Integrated circuit device and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant