CN110021607A

CN110021607A - Three-dimensional semiconductor device and forming method thereof

Info

Publication number: CN110021607A
Application number: CN201811632198.XA
Authority: CN
Inventors: 安钟善; 千志成; 权永振; 白石千; 李雄燮
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2018-01-10
Filing date: 2018-12-29
Publication date: 2019-07-16

Abstract

Provide a kind of three-dimensional semiconductor device and a kind of method for forming three-dimensional semiconductor device.The three-dimensional semiconductor device includes: upper substrate；Gate stack structure on the upper substrate, the gate stack structure includes gate electrode, the gate electrode is stacked in memory cell array region while being separated from each other on the direction on the surface perpendicular to the upper substrate, and it extends in the elongated area adjacent with the memory cell array region, to be arranged in the elongated area with stairstepping；And at least one pass-through zone, at least one described pass-through zone passes through the gate stack structure in the memory cell array region or the elongated area, at least one described pass-through zone includes lower area and the upper area than the lower region field width.

Description

Three-dimensional semiconductor device and forming method thereof

Cross reference to related applications

On January 10th, 2018 is " Three-Dimensional in the theme that Korean Intellectual Property Office submits The South Korea patent application No.10-2018-0003256 of Semiconductor Device " (three-dimensional semiconductor device), 2018 years 9 Months 5 days U.S. Patent application No.16/121,911 submitted in U.S.Patent & Trademark Office and know in South Korea on December 18th, 2018 Know the South Korea patent application No.10-2018-0164356 that property right office submits to be incorporated fully by reference by reference.

Technical field

This disclosure relates to semiconductor devices, more particularly, to including three of pass-through zone across gate stack structure Tie up semiconductor devices.

Background technique

The semiconductor device with the gate electrode stacked on the direction perpendicular to the surface of semiconductor substrate is developed Part.It is highly integrated in order to realize in the semiconductor device, increase the quantity of stacked gate electrode.However, with institute The quantity of the gate electrode of stacking gradually increases, and the difficulty level that such gate electrode is electrically connected to peripheral circuit is also increased therewith Greatly, so as to cause defect.

Summary of the invention

One aspect according to the embodiment, a kind of three-dimensional semiconductor device may include: upper substrate；Positioned at the upper substrate On gate stack structure, the gate stack structure includes gate electrode, and the gate electrode is in the table perpendicular to the upper substrate It is stacked in memory cell array region while being separated from each other on the direction in face, and extend to and the memory cell array In the adjacent elongated area in region, to be arranged in the elongated area with stairstepping；And at least one runs through Region, at least one described pass-through zone pass through the grid pile in the memory cell array region or the elongated area Stack structure, at least one described pass-through zone include lower area and the upper area than the lower region field width.

One aspect according to the embodiment, a kind of three-dimensional semiconductor device may include: lower substrate；Substructure, it is described Substructure is arranged on the lower substrate and including peripheral circuit；Upper substrate in the substructure is set；Gap Filled layer, the gap filling layer are arranged in the substrate aperture in the upper substrate；Gate stack structure, the grid pile Stack structure is arranged on the upper substrate and including gate electrode；And the pass-through zone across the gate stack structure, wherein The side of the pass-through zone includes step part.

One aspect according to the embodiment, a kind of three-dimensional semiconductor device may include: memory cell array region；Extend The two sides in the memory cell array region are arranged in region；Main isolation structure, the main isolation structure are single across the storage Element array region and the elongated area；Gate stack structure, the gate stack structure are arranged in the memory cell array In region and extend in the elongated area；Vertical channel structure, the vertical channel structure are arranged in the main isolation Between structure, and the gate stack structure is passed through in the memory cell array region；And at least one pass-through zone, At least one described pass-through zone is arranged in the memory cell array region or the elongated area and passes through the grid Pole stacked structure, the side of at least one pass-through zone include at least one step part.

Detailed description of the invention

Exemplary embodiment is described in detail by reference to attached drawing, feature will become aobvious and easy for those skilled in the art See, in which:

Fig. 1 shows the schematic block diagram of semiconductor devices according to example embodiment；

Fig. 2 shows the exemplary schematic electricity in the memory cell array region of semiconductor devices according to example embodiment Lu Tu；

Fig. 3 A shows the exemplary schematic plan of three-dimensional semiconductor device according to example embodiment；

Fig. 3 B shows the exemplary perspective schematic view of the three-dimensional semiconductor device of Fig. 3 A；

Fig. 4 and Fig. 5 shows the exemplary schematic cross-sectional view of the three-dimensional semiconductor device of Fig. 3 A；

Fig. 6 A shows the schematic plan of the modified example of the three-dimensional semiconductor device of Fig. 3 A；

Fig. 6 B shows the perspective schematic view of the modified example of the three-dimensional semiconductor device of Fig. 3 B；

Fig. 7 A shows the schematic cross-sectional view of a part of three-dimensional semiconductor device according to example embodiment；

Fig. 7 B shows the schematic cross of the modified example of a part of three-dimensional semiconductor device according to example embodiment Section view；

Fig. 8 A and 8B show the partial enlarged view of the region A1 and A2 of Fig. 4；

Fig. 9 shows the schematic plan of the modified example of semiconductor devices according to example embodiment；

Figure 10 A shows the schematic cross-sectional view of the modified example of semiconductor devices according to example embodiment；

Figure 10 B shows the schematic cross-sectional view of the modified example of semiconductor devices according to example embodiment；

Figure 10 C shows the schematic cross-sectional view of the modified example of semiconductor devices according to example embodiment；

Figure 11 A shows the perspective schematic view of the modified example of three-dimensional semiconductor device according to example embodiment；

Figure 11 B shows the schematic cross-section view of the modified example of three-dimensional semiconductor device according to example embodiment Figure；

Figure 12 shows the viewgraph of cross-section of the modified example of three-dimensional semiconductor device according to example embodiment；

Figure 13 A and Figure 13 B show the schematic cross-section of the modified example of semiconductor devices according to example embodiment View；

Figure 14 shows the top view of the modified example of three-dimensional semiconductor device according to example embodiment；

Figure 15 shows the top view of the modified example of three-dimensional semiconductor device according to example embodiment；

Figure 16 shows the top view of the modified example of three-dimensional semiconductor device according to example embodiment；

Figure 17 shows the top views of the modified example of three-dimensional semiconductor device according to example embodiment；

Figure 18 A and 18B show the process flow chart of the method for formation three-dimensional semiconductor device according to example embodiment；

Figure 19, Figure 20, Figure 21, Figure 22, Figure 23 and Figure 24 show formation 3 D semiconductor device according to example embodiment The perspective schematic view of the method for part；And

Figure 25 A, Figure 25 B, Figure 26 A, Figure 26 B, Figure 27 A, Figure 27 B, Figure 28 A, Figure 28 B, Figure 29 A, Figure 29 B, Figure 30 A, figure 30B, Figure 31 A and Figure 31 B show the schematic cross-section of the method for formation three-dimensional semiconductor device according to example embodiment View.

Specific embodiment

By the example of the three-dimensional semiconductor device of reference Fig. 1 description according to example embodiment.

Fig. 1 is the schematic block diagram of semiconductor devices according to example embodiment.

With reference to Fig. 1, semiconductor devices 10 according to example embodiment may include memory cell array region 20 and control Logic region 30.Memory cell array region 20 may include multiple memory block BLK, and each memory block BLK may include Multiple storage units.Control logic region 30 may include line decoder 32, page buffer 34 and control circuit 36.

The storage unit of each memory block BLK can be via string selection line SSL, a plurality of wordline WL and ground connection selection line GSL It is connected to line decoder 32, and page buffer 34 can be connected to via multiple bit lines BL.In the exemplary embodiment, it is arranged in It may be coupled to common word line WL with multiple storage units in a line, and being arranged in multiple storage units in same row can To be connected to identical common bit lines BL.

Line decoder 32 can decode input address to generate and transmit the driving signal for being used for wordline WL.Response In the control of control circuit 36, line decoder 32 can be mentioned the word line voltage generated by the voltage generation circuit of control circuit 36 Supply the selected word line WL and unselected bitline WL in wordline WL.

Page buffer 34 can be connected to memory cell array region 20 via bit line BL, be stored in storage unit to read In information.Page buffer 34 can temporarily store the data to be stored in a storage unit, or can be according to operation mode Sense the data being stored in a storage unit.

Page buffer 34 may include column decoder and sense amplifier.Activate to the column decoder property of can choose storage single The bit line BL in element array region 20, sense amplifier can be sensed during read operation by the bit line BL's of column decoder selection Voltage, to read the data being stored in selected storage unit.

Control circuit 36 can control the operation of line decoder 32 and page buffer 34.Control circuit 36 can receive outside It controls signal and external voltage, and can be operated in response to the control signal that receives.

Control circuit 36 may include voltage generation circuit, and electricity needed for external voltage generates internal operation can be used Pressure (such as program voltage, reading voltage, erasing voltage etc.).Control circuit 36 can read in response to control signal control, write Enter and/or erasing operation.

In addition, control circuit 36 may include input/output (I/O) circuit.The I/O circuit can connect in programming operation It receives data DATA and sends page buffer 34 for DATA, and can export and be connect from page buffer 34 outward in read operation The DATA of receipts.

It include in the three-dimensional semiconductor device 10 according to the example embodiment described above with reference to Fig. 1 by reference Fig. 2 description The example of the circuit of each memory block BLK in the memory cell array region 20 (Fig. 1) in (Fig. 1).Fig. 2 is memory cell array The example of circuit diagram in the memory block BLK in region 20.

With reference to Fig. 2, each memory block BLK of memory cell array region 20 (Fig. 1) may include being serially connected Storage unit MC, and be connected in series to the both ends of storage unit MC first choice transistor ST1 and second selection crystal Pipe ST2.The selection crystal of first choice transistor ST1 and the second selection transistor ST2 and first choice transistor ST1 and second Storage unit MC between pipe ST2 may be constructed storage string S.

The storage unit MC being serially connected can be connected respectively to the wordline WL for select storage unit MC.First The gate terminal of selection transistor ST1 may be coupled to first choice line SL1, and the source terminal of first choice transistor ST1 can To be connected to common source polar curve CSL.The gate terminal of second selection transistor ST2 may be coupled to the second selection line SL2, and second The source terminal of selection transistor ST2 may be coupled to the drain terminal of storage unit MC.In this example, first choice transistor ST1 can be ground connection selection transistor, and the second selection transistor ST2 can be string select transistor.In this example, first choice Ground connection the selection line GSL, the second selection line SL2 that line SL1 can be Fig. 1 can be the string selection line SSL of Fig. 1.

Fig. 2 shows wherein single first choice transistor ST1 and single second selection transistor ST2 to be connected to and go here and there each other Join the structure of the storage unit MC of connection.In different modes, multiple selections of first choice transistor ST1 or multiple second are brilliant Body pipe ST2 also may be coupled to storage unit MC.

In this example, nethermost wordline WL and first choice line in wordline WL can be set in the first dummy line DL1 Between SL1, the second dummy line DL2 be can be set between the uppermost wordline WL and the second selection line SL2 in wordline WL.The One dummy line DL1 can be set to single or multiple first dummy line DL1, and the second dummy line DL2 may be provided as individually Or multiple second dummy line DL2.

The drain terminal of second selection transistor ST2 may be coupled to bit line BL.When by the second selection line SL2 by signal When being applied to the gate terminal of the second selection transistor ST2, the signal applied by bit line BL, which can be sent to, to be one another in series The storage unit MC of connection, therefore reading data or write operation can be executed.Furthermore, it is possible to will have particular value by substrate Data erasing voltage be applied to storage unit MC execute erasing be stored in storage unit MC data data erasing behaviour Make.

Semiconductor devices 10 according to example embodiment may include at least one illusory string DS.At least one illusory string DS may include with the string with the bit line BL illusory channel being electrically isolated.

Fig. 3 A is the exemplary top view for schematically showing three-dimensional semiconductor device 10 according to example embodiment.Fig. 3 B It is the exemplary perspective view for schematically showing three-dimensional semiconductor device 10a according to example embodiment.Fig. 4 is the line along Fig. 3 A The viewgraph of cross-section of I-I ' interception, Fig. 5 are the viewgraph of cross-section of the line II-II ' interception along Fig. 3 A.

With reference to Fig. 3 A, Fig. 3 B, Fig. 4 and Fig. 5, three-dimensional semiconductor device 10 may include lower substrate 105, be arranged in lower substrate Substructure 110, the upper substrate 150 being arranged in substructure 110 on 105 and the grid being arranged on upper substrate 150 Stacked structure 270.Lower substrate 105 can be the semiconductor substrate formed by semiconductor material (for example, monocrystalline silicon etc.), upper substrate 150 can be the semiconductor substrate formed by semiconductor material (for example, polysilicon etc.).

Substructure 110 may include the peripheral circuit PCIR being arranged in the active region 120 limited by isolated area 115 With the lower insulating layer 140 of covering peripheral circuit PCIR.Peripheral circuit PCIR may include periphery transistor PTR and be electrically connected to outer Enclose the periphery wiring 130 of transistor PTR.Lower insulating layer 140 can be formed by silica.

Three-dimensional semiconductor device 10 may include be provided through in the first substrate hole 155a of upper substrate 150 first between Gap filled layer 160a and the intermediate insulating layer 162 being arranged on the side surface of upper substrate 150.First gap filling layer 160a is in Between insulating layer 162 can be formed by identical insulating materials (such as silica).

Gate stack structure 270 may include on the direction on the surface perpendicular to upper substrate 150 (for example, along the side Z To) stack while the gate electrode that is separated from each other.The gate electrode of gate stack structure 270 can be formed from conductive materials, this is led Electric material includes doped silicon, metal nitride (for example, TiN), metal silicide (for example, WSi, TiSi, TaSi etc.) or metal At least one of (for example, W).Doped silicon can be including p-type impurity (for example, P, As etc.) or n-type impurity (for example, B etc.) Polysilicon.

Three-dimensional semiconductor device 10 may include the nethermost gate electrode and upper substrate that gate stack structure 270 is arranged in Lower interlayer insulating film 210L between 150, the upper layer insulation being arranged on the uppermost gate electrode of gate stack structure 270 The layer 210U and intermediate interlayer insulating film 210M being arranged between the gate electrode of gate stack structure 270.Gate stack structure 270 gate electrode can be stacked in the memory cell array region 20 on upper substrate 150, be separated from each other simultaneously, and can With in the elongated area 22 that extends on upper substrate 150 to have welding disking area P in elongated area 22.

In the gate electrode of gate stack structure 270, each gate electrode below uppermost gate electrode be can wrap Include overlapping region (that is, gate electrode and its right above gate electrode crossover region) and non-overlapping region (that is, gate electrode not with its The region of the gate electrode crossover of surface).Non-overlapping region can be welding disking area P, for example, being located under uppermost gate electrode Each gate electrode of side has exposed surface in non-overlapping region.

As above with reference to described in Fig. 1 and 2, memory cell array region 20, which can be, can wherein be formed including Fig. 2 Storage unit MC memory block BLK region, elongated area 22 can be the region that welding disking area P can be set, wherein welding Disk area P is formed by the extension of the gate electrode for the gate stack structure 270 being formed in memory cell array region 20 's.Here, what welding disking area P can be gate electrode can be with the gate contact plug 280g for the line decoder 32 for being electrically connected to Fig. 1 The region of contact, for example, gate contact plug 280g can be from welding disking area P towards the top vertical of gate stack structure 270 Ground extends.

It in the exemplary embodiment, in a top view, can be with to the direction of elongated area 22 from memory cell array region 20 Referred to as first direction X is properly termed as second direction Y perpendicular to the direction of first direction X, and in a cross section view, vertically Third direction Z is properly termed as in the direction on the surface of upper substrate 150.

In the exemplary embodiment, the gate electrode of gate stack structure 270 may include lower gate electrode GE _ L, setting (for example, Stacking) intermediate gate electrode GE _ M on lower gate electrode GE _ L and setting (for example, stacking) be on intermediate gate electrode GE _ M Upper gate electrode GE _ U.In the exemplary embodiment, the gate electrode of gate stack structure 270 may include lower gate electrode GE _ L and in Between dummy gate electrode GE_D1 between gate electrode GE _ M, and it is slow between intermediate gate electrode GE _ M and upper gate electrode GE _ U Rush gate electrode GE _ D2.Here, buffering gate electrode GE _ D2 is referred to as dummy gate electrode.

In the exemplary embodiment, lower gate electrode GE _ L can be the first choice line SL1 of above-mentioned Fig. 2 and/or above-mentioned The ground connection selection line GSL of Fig. 1.Dummy gate electrode GE_D1 can be the first dummy line DL1 in above-mentioned Fig. 2, intermediate gate electrode GE_M can be the wordline WL of above-mentioned Fig. 1 and Fig. 2, and buffering gate electrode GE _ D2 can be the second dummy line of above-mentioned Fig. 2 DL2, upper gate electrode GE _ U can be the string selection line SSL of the second selection line SL2 and above-mentioned Fig. 1 of above-mentioned Fig. 2.

Elongated area 22 may include first step region 22a, second step region 22c and in first step region Buffer area 22b between 22a and second step region 22c.First step region 22a can be gate electrode GE _ U on wherein The region that welding disking area P can be arranged with stairstepping, second step region 22c can be the pad area of intermediate gate electrode GE _ M What the welding disking area P of domain P, the welding disking area P of dummy gate electrode GE_D1 and lower gate electrode GE _ L can be arranged with stairstepping Region.

Three-dimensional semiconductor device 10 may include the first pad pass-through zone TH1 across gate stack structure 270.First Pad pass-through zone TH1 can be overlapping with the first gap filling layer 160a, for example, the bottom of the first pad pass-through zone TH1 can With placed in the middle on the top of the first gap filling layer 160a.In the exemplary embodiment, the first pad pass-through zone TH1 can be passed through Grid in the buffer area 22b between first step region 22a and second step region 22c of gate stack structure 270 Electrode, and can be across the intermediate interlayer insulating film 210M the gate electrode, for example, the first pad pass-through zone TH1 It is the white portion for penetrating the gate stack structure 270 in Fig. 4.In addition, the first pad pass-through zone TH1 can pass through lower interlayer Insulating layer 210L.

In the exemplary embodiment, the first welding disking area TH1 may include lower pass-through zone TH1_L and be located at lower pass-through zone Upper pass-through zone TH1_U on TH1_L.The width in X direction of upper pass-through zone TH1_U can be than lower pass-through zone TH1_L Width in X direction it is wide.For example, the side surface of upper pass-through zone TH1_U can not be with the side surface of lower pass-through zone TH1_L It is vertically aligned, for example, lower pass-through zone TH1_L can be placed in the middle relative to upper pass-through zone TH1_U.In the exemplary embodiment, Length of the upper pass-through zone TH1_U on its vertical direction (for example, along the Z direction) can be greater than lower pass-through zone TH1_L and exist Length on its vertical direction (for example, along the Z direction).

In the exemplary embodiment, the side of the first pad pass-through zone TH1 may include step part S1.Compared to grid The upper surface of stacked structure 270, step part S1 can be (for example, along the Z direction) closer to the following table of gate stack structure 270 Face.Step part S1 is more fully described below with reference to Fig. 8 A.

Three-dimensional semiconductor device 10 may include the upper insulating layer 230 for covering a part of gate stack structure 270.It is upper exhausted Edge layer 230 can cover being located at below uppermost gate electrode GE _ U and extending for the gate electrode of gate stack structure 270 Part in region 22.Therefore, upper insulating layer 230 can be set in elongated area 22.

In the exemplary embodiment, upper insulating layer 230 can cover the top of the first pad pass-through zone TH1, and can be with It is integrally formed with the first pad pass-through zone TH1.First pad pass-through zone TH1 and upper insulating layer 230 can be by such as oxygen SiClx is formed.

Three-dimensional semiconductor device 10 may include vertical channel structure VS, and vertical channel structure VS passes through upper interlayer insulating film 210U, centre interlayer insulating film 210M and lower interlayer insulating film 210L, also cross gate stack structure 270.Vertical-channel knot Structure VS may be coupled to upper substrate 150.Vertical channel structure VS can be set in memory cell array region 20.

As shown in Figure 3B, in gate stack structure 270, welding disking area P in the 22c of second step region is arranged in can be with It is arranged with stairstepping.Here, will with reference to Fig. 3 B description by a pair of first main isolation structure MS1 (adjacent to each other along Y-direction) and The rank for the second step region 22c that the main isolation structure MS2 of second be arranged between the first main isolation structure MS1 of this pair is limited Trapezoidal shape.This stairstepping can be the stairstepping of a pair of of memory block BLK adjacent to each other.

With reference to Fig. 3 B, " step part " will be hereinafter referred to as with the welding disking area P of the gate electrode of stairstepping setting. Welding disking area P may include the first step group SG1 adjacent with the first main isolation structure MS1, setting first step group SG1 it Between center at second step group SG2 and the third platform that is arranged between first step group SG1 and second step group SG1 Rank group SG3.For example, as shown in Figure 3B, first step group SG1 can be tight with each first main isolation structure MS1 along the Y direction Neighbour (for example, show two first step groups corresponding with each of two the first main isolation structure MS1 in figure 3b SG1).For example, second step group SG2 can be between two the first main isolation structure MS1, example as further shown in Fig. 3 B At center such as between this two the first main isolation structure MS1, and third step group SG3 can be in second step group SG2 Between a first main isolation structure MS1 corresponding in two the first main isolation structure MS1.Third step group SG3 can be with First step group SG1 is adjacent.Second step group SG2 can be separated by the second main isolation structure MS2.

In the exemplary embodiment, nominal region DA can be set between second step group SG2 and third step group SG3. Nominal region DA can be the region of not formed step part.

Each step part of first step group SG1 can ramp up the in the side far from the first main isolation structure MS1 One height.Here, the first height can be two in side's gate electrode spaced upwardly on the surface perpendicular to upper substrate 150 Difference in height between a adjacent gate electrode.

The step part of first step group SG1 can reduce on the direction far from memory cell array region 20 is higher than the Second height of one height.For example, the second height can be the first gate electrode being sequentially arranged along the vertical direction, the second gate electrode Difference in height between the first gate electrode in third gate electrode and third gate electrode.

Compared with the step part of first step group SG1, at least part step part of second step group SG2 can be with Upper substrate 150 is adjacent, for example, the vertical distance between second step group SG2 and upper substrate 150 can be less than first step group Vertical distance between SG1 and upper substrate 150.Compared with the step part of second step group SG2, third step group SG3 is extremely Few a part of step part can be adjacent with upper substrate 150, for example, between second step group SG2 and upper substrate 150 it is vertical away from From the vertical range that can be greater than between third step group SG3 and upper substrate 150.With the stage portion split-phase of first step group SG1 Than the step part of third step group SG3 can be adjacent with upper substrate 150.

In modified example, as described above, the illusory district between second step group SG2 and third step group SG3 is arranged in Domain DA can be replaced with the second pad pass-through zone TH2 of Fig. 6 A and Fig. 6 B.It will show with reference to the such modification of Fig. 6 A and 6B description Example.

Fig. 6 A is the top view for schematically showing the modified example of three-dimensional semiconductor device 10 according to example embodiment. Fig. 6 B is the perspective view for schematically showing the modified example of three-dimensional semiconductor device 10 according to example embodiment.

With reference to Fig. 6 A and Fig. 6 B, in three-dimensional semiconductor device 10a, the nominal region DA of Fig. 3 A and Fig. 3 B can use second Pad pass-through zone TH2 is replaced.Therefore, upper substrate 150 may include the second gap filling layer 160b, the second gap filling layer 160b is arranged in the region that upper substrate 150 and the second pad pass-through zone TH2 are overlapped.

Reference Fig. 7 A is described to the example of above-mentioned vertical channel structure VS.Fig. 7 A is to schematically show vertical-channel knot The viewgraph of cross-section of structure VS and grid, to show the vertical channel structure in three-dimensional semiconductor device according to example embodiment The example of VS and grid.

With reference to Fig. 7 A, vertical channel structure VS, which can be set, is passing through gate stack structure 270, lower interlayer insulating film In the channel hole 234 of 210L, centre interlayer insulating film 210M and upper interlayer insulating film 210U.In the exemplary embodiment, vertical furrow Road structure VS may include upwardly extending in the side on the surface perpendicular to upper substrate 150 and passing through gate stack structure 270 Insulative core layer 248, cover insulative core layer 248 side surface and bottom surface channel semiconductor 246, surround channel semiconductor The first grid dielectric 240 of 246 outer surface and setting on insulative core layer 248 and are electrically connected to channel semiconductor The pad layer 250 of layer 246.

Channel semiconductor 246 may be electrically connected to upper substrate 150.Channel semiconductor 246 can be by semiconductor material (such as silicon etc.) is formed.

Pad layer 250 can be formed by the polysilicon for example with n-type conductivity.Insulative core layer 248 can be by insulation material Expect that (such as silica etc.) is formed.

Three-dimensional semiconductor device 10 may include between gate stack structure 270 gate electrode and vertical channel structure VS it Between and extend to the second grid dielectric 268 in the upper and lower surfaces of gate electrode.First grid dielectric 240 and At least one of two gate-dielectrics 268 may include the layer for storing information.For example, first grid dielectric 240 can To include the layer for storing information.However, example embodiment is without being limited thereto, for example, second grid dielectric 268 can also wrap Include the layer for storing information.

The example of the first grid dielectric 240 including the layer for storing information is described below.First grid electricity is situated between Matter 240 may include tunnel dielectric 242, information storage layer 243 and barrier dielectric 244.

Information storage layer 243 can be set between tunnel dielectric 242 and barrier dielectric 244.Tunnel dielectric layer 242 can be adjacent with channel semiconductor 246, and barrier dielectric 244 can be adjacent with gate stack structure 270.Tunnel electricity is situated between Matter 242 may include the silica of such as silica and/or impurity.Barrier dielectric 244 may include silica and/or High-k dielectric.

Information storage layer 243 can be between channel semiconductor 246 and centre gate electrode GE _ M, and can be use In the layer of storage information.For example, information storage layer 243 can be formed by the material of such as silicon nitride, which can be captured simultaneously Retain through tunnel dielectric 242 from 246 injected electrons of channel semiconductor, or can be according to non-volatile memory device The operating condition of (for example, flash memory device etc.) removes the electronics captured in information storage layer 243.Second grid dielectric 268 may include high-k dielectric, such as AlO etc..

Information storage layer 243 can store letter in the region in face of intermediate gate electrode GE _ M of gate stack structure 270 Breath, intermediate gate electrode GE _ M can correspond to the wordline WL of Fig. 1 and Fig. 2 for describing in fig. 1 and 2 above.Wherein vertical furrow The region that the information storage layer 243 of road structure VS can store information can be along the direction cloth on the surface perpendicular to upper substrate 150 It sets, and may be constructed the storage unit MC described in Fig. 2 above.Channel semiconductor 246 can be directly connected to base Plate 150, but example embodiment is without being limited thereto.

Reference Fig. 7 B is described to the modified example of vertical channel structure VS.Fig. 7 B is to schematically show to be implemented according to example The viewgraph of cross-section of the modified example of vertical channel structure VS in the three-dimensional semiconductor device of example.

With reference to Fig. 7 B, in the gate electrode of gate stack structure 270, near upper substrate 150 lower gate electrode GE _ L with Interval between dummy gate electrode GE_D1 on lower gate electrode GE _ L can be greater than the interval between other gate electrodes.As above Described in fig. 7, vertical channel structure VS ' can be set in channel hole 234.

In the exemplary embodiment, vertical channel structure VS ' may include that below channel hole 234 and downwards grid are arranged The lower channel semiconductor layer 235 of electrode GE_L, the insulative core layer 248 being arranged on lower channel semiconductor layer 235, covering insulating core The upper channel semiconductor 246 ' of the side surface of layer 248 and bottom surface, around the of the outer surface of upper channel semiconductor 246 ' One gate-dielectric 240 and the pad layer for being arranged on insulative core layer 248 and being electrically connected to channel semiconductor 246 250.Lower channel semiconductor layer 235 can be directly connected to upper substrate 150, and can be formed as epitaxial semiconductor layer.Upper ditch Road semiconductor layer 246 ' can be formed by semiconductor material (such as silicon etc.).

First grid dielectric 240 can be identical as what is described in fig. 7 above.It can be between vertical furthermore, it is possible to be arranged Between channel structure VS ' and gate stack structure 270 and extend to gate stack structure 270 gate electrode upper surface With the second grid dielectric 268 on lower surface, as described in above in fig. 7.

Referring again to Fig. 3 A to Fig. 5, three-dimensional semiconductor device 10 may include upper interlayer insulating film 210U and be arranged on upper layer Between the first covering insulating layer 255 on insulating layer 210U.First covering insulating layer 255 can be formed by such as silica.

Three-dimensional semiconductor device 10 may include the main isolation junction across memory cell array region 20 and elongated area 22 Structure MS.As described in Figure 1 above, each memory block BLK in the memory cell array region 20 of Fig. 1 can be located at Between the main isolation structure MS of a pair adjacent to each other.

Three-dimensional semiconductor device 10 may include the auxiliary isolation structure SS being arranged between main isolation structure MS.In example In embodiment, auxiliary isolation structure SS may include across memory cell array region 20 and extending to extension along the X direction The auxiliary isolation structure of wire shaped in a part in region 22, and the auxiliary isolation structure being arranged in elongated area 22. In the exemplary embodiment, the length of auxiliary isolation structure SS is shorter than the length of main isolation structure MS accordingly.

Therefore, auxiliary isolation structure SS can have wire shaped, and can along wire shaped length direction in extension area It is spaced apart in a part in domain 22.Therefore, between the main isolation structure MS of a pair adjacent to each other and it is arranged same At least one intermediate gate electrode GE _ M in plane can not be completely separable by auxiliary isolation structure SS, to be used as single word Line.Between the main isolation structure MS of a pair adjacent to each other, upper gate electrode GE _ U can be divided into more by auxiliary isolation structure SS A upper gate electrode GE _ U (Fig. 3 B).

In the exemplary embodiment, insulated wire 232 can be set between the main isolation structure MS of a pair adjacent to each other, and It can be set between auxiliary isolation structure SS dividing upper gate electrode GE _ U for multiple upper gate electrode GE _ U (Fig. 5).Insulated wire 232 can be set at the height higher than the height of intermediate gate electrode GE _ M.

Main isolation structure MS and auxiliary isolation structure SS can be set on upper substrate 150, and can pass through grid pile Stack structure 270.Main isolation structure MS and auxiliary isolation structure SS can pass through gate stack structure 270, lower interlayer insulating film 210L, intermediate interlayer insulating film 210M, upper interlayer insulating film 210U and upper insulating layer 230.Main isolation structure MS and auxiliary isolation Each of structure SS may include the spacer 274 of the side surface of conductive pattern 276 and covering conductive pattern 276.

Spacer 274 can be formed by insulating materials (such as silica, silicon nitride etc.).Spacer 274 can will be conductive Pattern 276 is spaced apart with gate stack structure 270.

Conductive pattern 276 can be formed from conductive materials, which includes DOPOS doped polycrystalline silicon, metal nitride (example At least one of such as, titanium nitride etc.) or metal (for example, tungsten etc.).In the exemplary embodiment, conductive pattern 276 can also claim For source contact plug.

Main isolation structure MS may include the first main isolation structure MS1 and between the first main isolation structure MS1 Second main isolation structure MS2.In the exemplary embodiment, the second main isolation structure MS2 can be with single line shape across storage unit Array region 20 extends in elongated area 22, and the part MS2 ' of two lines can be divided into including wherein single line, from And surround the first pad pass-through zone TH1 (Fig. 3 A-3B).As described above, the partitioning portion MS2 ' of the second main isolation structure MS2 Two lines can be combined into single line across the remainder of elongated area 22.In the exemplary embodiment, the second main isolation junction The partitioning portion MS2 ' of structure MS2 may include protrusion, and the protrusion is along from around the first pad pass-through zone TH1's The direction of a part of partitioning portion MS2 ' to auxiliary isolation structure SS extend.In the exemplary embodiment, the second main isolation structure The partitioning portion MS2 ' of MS2 can be set between at least some auxiliary isolation structure SS.

Three-dimensional semiconductor device 10 may include being located at upper base below main isolation structure MS and auxiliary isolation structure SS Extrinsic region 272 in plate 150.Extrinsic region 272 can have n-type conductivity, and upper substrate 150 and extrinsic region 272 adjacent parts can have p-type conductivity.Extrinsic region 272 can be the common source polar curve of above-mentioned Fig. 1 and Fig. 2 CSL。

Three-dimensional semiconductor device 10 may include the second covering insulating layer 278 being arranged on the first covering insulating layer 255, To cover main isolation structure MS and auxiliary isolation structure SS.Second covering insulating layer 278 can be formed by such as silica.

Three-dimensional semiconductor device 10 may include bit line contact plug 280b and gate contact plug 280g, and bit line contact is inserted Plug 280b passes through the first covering insulating layer 255 and the second covering insulating layer 278 and the position for being electrically connected to vertical channel structure VS Line contact plunger 280b, gate contact plug 280g are extended on the welding disking area P of the gate electrode of gate stack structure 270, together When pass through first covering insulating layer 255 and second covering insulating layer 278, to be electrically connected to the welding disking area P of gate electrode.

Three-dimensional semiconductor device 10a may include peripheral contacts plug, wherein it is exhausted that peripheral contacts plug passes through the first covering Edge layer 255 and the second covering insulating layer 278, pass through the first pad pass-through zone TH1, and extend downwardly to be electrically connected under The periphery wiring 130 of peripheral circuit PCIR in portion's structure 110.Peripheral contacts plug may include grid peripheral contacts plug 284g.Grid peripheral contacts plug 284g can pass through upper substrate 150.For example, grid peripheral contacts plug 284g can sequence Ground passes through gate stack structure 270 and the first gap filling layer 160a, and extends in substructure 110 with electrical connection To periphery wiring 130.

Three-dimensional semiconductor device 10 may include the upper wiring being arranged on the second covering insulating layer 278.Upper wiring can be with Bit line 290b including being electrically connected to bit line contact plug 280b connects cloth with the grid for being electrically connected to gate contact plug 280g Line 290g.In the exemplary embodiment, at least part of grid connecting wiring 290g may be electrically connected to grid peripheral contacts and insert Fill in 284g.Therefore, at least part gate electrode of gate stack structure 270 can be electrically connected by the first pad pass-through zone TH1 It is connected to the peripheral circuit PCIR of 150 lower section of upper substrate.

Optionally, at least part gate electrode of gate stack structure 270 can be by the first pad pass-through zone TH1 simultaneously And the second pad pass-through zone TH2 by describing in figures 6 a and 6b above is electrically connected to the periphery electricity of 150 lower section of upper substrate Road PCIR.

As described above, reference Fig. 8 A and 8B to be described to side and the grid of the first pad pass-through zone TH1 as described above The welding disking area P of the gate electrode of stacked structure 270.Fig. 8 A and 8B are the partial enlarged views of region " A1 " and " A2 " of Fig. 4.This In, region " A1 " can indicate that the step part S1 of every side of the first above-mentioned welding disking area TH1, region " A2 " can be indicated The welding disking area P of gate stack structure 270.

Referring initially to Fig. 4 and Fig. 8 A, the step part S1 of the side of the first pad pass-through zone TH1 is in step part S1 Width in the horizontal direction of (in the region A1 of Fig. 8 A) can than gate stack structure 270 welding disking area P in pad area Width in the horizontal direction of domain P (in the region A2 of Fig. 8 A) is narrow.In this example, the gate electrode of gate stack structure 270 Part in the step part S1 of the side of the first pad pass-through zone TH1 is (for example, the region A1 in Fig. 8 A of gate electrode It is middle limit step part part) and gate stack structure 270 gate electrode the welding disking area positioned at gate stack structure 270 Part in P (for example, the part for limiting welding disking area P in the region A2 in Fig. 8 A of gate electrode) is run through close to the first pad There can be increased thickness at the region of region TH1.

For example, the gate electrode of gate stack structure 270 can extend with first thickness, and can be in the first pad Have in the step part S1 of the side of pass-through zone TH1 and in the welding disking area P of gate stack structure 270 and is greater than the first thickness The second thickness of degree.However, example embodiment is without being limited thereto.For example, as shown in Figure 8 B, the gate electrode of gate stack structure 270 Side positioned at the first pad pass-through zone TH1 step part S1 in part thickness and gate stack structure 270 The thickness of the part in the welding disking area P of gate stack structure 270 of gate electrode can be with the other parts of gate electrode Thickness is identical.

Above, it essentially describes and is arranged between the first main isolation structure MS1 of a pair by reference to Fig. 3 A to Fig. 5 The main isolation structure MS2 of first pad pass-through zone TH1 and second, but example embodiment is without being limited thereto.For example, the first pad passes through Multiple first pad pass-through zone TH1 and multiple second masters can be respectively formed as by wearing the main isolation structure MS2 of region TH1 and second Isolation structure MS2.

As described above, reference Fig. 9 description is run through including that can be formed as the first pad of the first pad pass-through zone TH1 Region TH1 shows with the three-dimensional semiconductor device 10 for the second main isolation structure MS2 that can be formed as the second main isolation structure MS2 Example.Here, three-dimensional semiconductor device 10 may include all constituent element described above with reference to Fig. 3 A to Fig. 5.Before The constituent element above with reference to described in Fig. 3 A to Fig. 5 is described, therefore its detailed description will be omitted.

Fig. 9 is the top view for schematically showing the modified example of semiconductor devices according to example embodiment.

With reference to Fig. 3 A to Fig. 5 and Fig. 9, the first pad pass-through zone TH1 described in Fig. 3 A to Fig. 5 and second is main above Isolation structure MS2 can repeat to arrange in one direction.Therefore, multiple first pad pass-through zone TH1 can be set.

First pad pass-through zone TH1 can along with the first direction from memory cell array region 20 to elongated area 22 X vertical second direction Y is repeatedly disposed in plane shown in Fig. 9.For example, as shown in Figure 9, the first pad runs through area Domain TH1 can be separated from each other with Y in a second direction, for example, each first pad pass-through zone TH1 can have in a second direction The longitudinal direction of Y, and can extend only along two memory block BLK.

As described in Fig. 3 A to Fig. 5, each first pad pass-through zone TH1 can be for example continuously by above The partitioning portion MS2 ' of two main isolation structure MS2 is surrounded.Therefore, the multiple second main isolation structure MS2 can be with the first pad area The quantity of domain TH1 is proportionally arranged.

Main isolation structure MS may include the first main main isolation structure MS2 of isolation structure MS1 and second.Each second it is main every It can be set between the main isolation structure MS1 of a pair first adjacent to each other in the first main isolation structure MS1 from structure MS2. Therefore, the first main main isolation structure MS2 of isolation structure MS1 and second can repeat to arrange with Y in a second direction.For example, as in Fig. 9 Shown, the first main isolation structure MS1 can have between two adjacent first pad pass-through zone TH1 along first direction X The wire shaped of extension, the second main isolation structure MS2 can extend along first direction X and run through area around corresponding first pad Domain TH1, for example, the first main main isolation structure MS2 of isolation structure MS1 and second can replace on second direction Y.

As described in Fig. 3 A to 5, each first pad pass-through zone TH1 can be by gate stack structure above 270 gate electrode is electrically connected to the peripheral circuit PCIR of 150 lower section of upper substrate.According to example embodiment, it is similar to the first pad Pass-through zone TH1, storage pass-through zone TH3 (Fig. 9 and Figure 10 A) can be used for the bit line described in Fig. 3 A to Fig. 5 above 290b is electrically connected to the peripheral circuit PCIR being arranged in below upper substrate 150.

To include with reference to Fig. 3 A to Fig. 5 and Fig. 9 and Figure 10 A description storage pass-through zone TH3 as described above (Fig. 9 and Figure 10 A) semiconductor devices example.Figure 10 A is the schematic cross-sectional view of the line III-III ' along Fig. 9.Here, before The constituent element above with reference to Fig. 3 A to Fig. 5 and Fig. 9 description has been described, therefore its detailed description will be omitted.

With reference to Fig. 3 A to Fig. 5, Fig. 9 and Figure 10 A, three-dimensional semiconductor device according to the embodiment may include that setting is in place The first main isolation structure MS1 adjacent to each other and second in the main isolation structure MS in memory cell array region 20 it is main every From the storage pass-through zone TH3 between structure MS2.Therefore, as described above, memory block BLK can repeat cloth with Y in a second direction It sets, at least one memory block BLK for repeating arrangement in this way can be replaced by storage pass-through zone TH3.Therefore, it overlooks In figure, at least one storage pass-through zone TH3 be can be set between a pair of of memory block BLK, for example, at least one storage runs through Region TH3 can have the longitudinal direction along first direction X.As shown in Figure 10 A, storage pass-through zone TH3 can pass through grid Stacked structure 270, and can be exhausted across lower interlayer insulating film 210L, centre interlayer insulating film 210M and upper interlayer along Z-direction Edge layer 210U.

Above with reference to as described in Fig. 3 A to Fig. 5, the first pad pass-through zone TH1 be can be set in elongated area 22.This Outside, the first pad pass-through zone TH1 can buffer area 22b between first step region 22a and second step region 22c It is interior electric across lower gate electrode GE _ L of gate stack structure 270, dummy gate electrode GE_D1, centre gate electrode GE _ M and buffering grid Pole GE_D2.Storage pass-through zone TH3 can be set in memory cell array region 20, and can pass through gate stack knot Lower gate electrode GE _ L, dummy gate electrode GE_D1, centre gate electrode GE _ M, buffering gate electrode GE _ D2 and the upper gate electrode of structure 270 GE_U.Therefore, the first pad pass-through zone TH1 can be spaced apart with X along a first direction with upper gate electrode GE _ U, and stored and passed through Upper gate electrode GE _ U can further be passed through than the first pad pass-through zone TH1 by wearing region TH3.

Storing pass-through zone TH3 can be by material identical with the material of the first pad pass-through zone TH1 (for example, oxidation Silicon) it is formed.Storage pass-through zone TH3 may include lower pass-through zone TH3_L and on lower pass-through zone TH3_L on run through Region TH3_U.In storage pass-through zone TH3, the width of upper pass-through zone TH3_U can be wider than lower pass-through zone TH3_L Degree is wide.As in the first pad pass-through zone TH1, the side of storage pass-through zone TH3 may include step part S1.It deposits Storage pass-through zone TH3 can have the gap filling layer 161 of setting thereunder, with overlapping with storage pass-through zone TH3.

Gap filling layer 161 can be formed by the insulating materials for filling the substrate aperture 155b across upper substrate 150.Gap is filled out Filling layer 161 can be formed by insulating materials (for example, silica) identical with the insulating materials of the first gap filling layer 160a.

Bit line peripheral contacts plug 284b can pass through storage pass-through zone TH3, can pass through the first covering insulating layer 255 Insulating layer 278 and the second gap filling layer 160b are covered with second, and is extended in substructure 110 with electrical connection To the periphery wiring 130 of peripheral circuit PCIR.Every bit line 290b may be electrically connected to bit line peripheral contacts plug 284b.Cause This, bit line 290b can be electrically connected to peripheral circuit by passing through the bit line peripheral contacts plug 284b of storage pass-through zone TH3 PCIR。

In the exemplary embodiment, the shape for storing pass-through zone TH3 can be similar to the shape of the first pad pass-through zone TH1 Shape, and store pass-through zone TH3 and can also be modified to various shape.For example, storage pass-through zone TH3 can be than the One pad pass-through zone TH1 further passes through gate electrode GE _ U, to be modified to have and the first pad pass-through zone TH1 Variform shape.

For example, multiple upper gate electrode GE _ U can be stacked on the direction on the surface perpendicular to upper substrate 150, and upper grid Electrode GE_U can have the welding disking area P being arranged in elongated area 22 with stairstepping.It is used to form gate electrode The Patternized technique of the welding disking area P of the stairstepping of GE_U can be formed storage pass-through zone TH3 position in pattern Gate electrode GE _ U in change buffers gate electrode GE _ D2 with exposure.In this state, storage pass-through zone TH3 can by with shape It is formed at the identical technique of technique of the first pad pass-through zone TH1.According to by the position that form storage pass-through zone TH3 Buffering gate electrode GE _ D2 exposure the shape setting gate electrode GE _ U on patterning and being formed, can be to storage pass-through zone TH3 Shape carry out various modifications.

Figure 10 B and Figure 10 C are the viewgraph of cross-section for showing the modified example of storage pass-through zone TH3 of Figure 10 A.

Referring initially to Figure 10 B, storing pass-through zone TH3 ' can include step part S2 at an upper portion thereof.For example, storing In the upper pass-through zone TH3_U of pass-through zone TH3, the upper pass-through zone TH3_ that is limited by the uppermost gate electrode in gate electrode The width of U can be greater than the width by intermediate gate electrode GE _ M upper pass-through zone TH3_U limited.For example, as shown in Figure 10 B, Storage pass-through zone TH3 can have increased three vertical components of width on top of each other, wherein first step portion S1 and second step part S2 is divided to separate these vertical components.

With reference to Figure 10 C, the side for storing pass-through zone TH3 " may include multiple step part S1 '.As described above, wherein The stairstepping and the first pad pass-through zone TH1 that can arrange the welding disking area P of the gate electrode of gate stack structure 270 can be with It is modified to various forms, and is not limited to foregoing illustrative embodiments.

The modification for being described with reference to figure 11a and 11b stairstepping as described above and the first pad pass-through zone TH1 is shown Example.

Figure 11 A is the perspective view for schematically showing the modified example of three-dimensional semiconductor device according to example embodiment, Figure 11 B is one schematically shown along Figure 11 A intercepted from memory cell array region 20 to the direction of elongated area 22 Partial viewgraph of cross-section.Here, by the modified example of main description stairstepping and the first pad pass-through zone TH1, and The description of remaining constituent element can be understood as with content replacement those of is described above.Therefore, its detailed description will be omitted.

With reference to Figure 11 A and Figure 11 B, lower substrate 105, substructure 110 and upper substrate 150 as described above can be set. The gate stack structure 370 being arranged on upper substrate 150 may include being separated from each other and for example along perpendicular to upper substrate 150 Surface third direction Z stack gate electrode.

As described above, the gate electrode of gate stack structure 370 can be separated from each other and in memory cell array region It stacks, and is extended in elongated area 22 to have welding disking area P in elongated area 22 in 20.Gate stack structure 370 gate electrode may include lower gate electrode GE _ L, the dummy gate electrode GE_D1 on lower gate electrode GE _ L, positioned at illusory Intermediate gate electrode GE _ M on gate electrode GE _ D1, buffering gate electrode GE _ D2 on intermediate gate electrode GE _ M and it is located at slow Rush upper gate electrode GE _ U on gate electrode GE _ D2.

As described above, elongated area 22 may include first step region 22a, second step region 22c and be located at the Buffer area 22b between one stepped area 22a and second step region 22c.First step region 22a can be such area Domain, that is, in the region, step part can by the upper gate electrode GE _ U sequentially reduced welding disking area p-shaped at.Second step area Domain 22c can be the region that can dispose welding disking area P, and welding disking area P may be arranged to have edge from memory cell array area The first direction of domain 20 to elongated area 22 reduces the step shape of the first height or has along perpendicular to first direction Second direction the stairstepping than the first small the second height of height has been raised and lowered.

First pad pass-through zone TH1 ' can pass through the gate stack structure 370 of buffer area 22b.First gap filling Layer 160a can be overlapping with the first pad pass-through zone TH1 ', and can pass through upper substrate 150.

The side of first pad pass-through zone TH1 ' may include step part S1.Therefore, the first pad pass-through zone The side of TH1 ' can be formed by multiple step parts.Pad pass-through zone TH1 ' can have width can be towards part thereon The increased shape of section.Reduced difference in height between the step part of first welding disking area TH1 ' can be with second step region The welding disking area P of 22c is basic in the difference in height reduced along the first direction from memory cell array region 20 to elongated area 22 It is identical.

Reference Figure 12 is described to the modified example of stairstepping and the first pad pass-through zone TH1.

Figure 12 is the viewgraph of cross-section for showing the modified example of three-dimensional semiconductor device according to example embodiment.Here, Will main description stairstepping and the first pad pass-through zone TH1 modified example, and remaining constitute the description of element can be with It is interpreted as with content replacement those of is described above.Therefore, its detailed description will be omitted.

With reference to Figure 12, the welding disking area P of the gate electrode of gate stack structure 470 can be arranged to have along far from storage The direction of cell array region 20 reduces the step shape of the first height.It is arranged as the pad area with such stairstepping Domain P can be the step part of gate electrode.

Can have width across the first pad pass-through zone TH1 " of gate stack structure 470 can increase towards upper part The shape added.For example, the side of the first pad pass-through zone TH1 " may include the rank with the gate electrode of gate stack structure 470 The corresponding step part S1 of trapezoidal shape.For example, when the step part of the gate electrode of gate stack structure 470 has gradually decreased the When one height, the step part S1 of the side of the first pad pass-through zone TH1 " can also be gradually decreased.

3A and Figure 13 B referring to Fig.1 is described to the modified example of upper substrate 150 as described above and/or main isolation structure MS. Figure 13 A and Figure 13 B show the schematic cross-sectional view of the modified example of semiconductor devices according to example embodiment.Figure 13A is the viewgraph of cross-section of the line I-I ' interception along Fig. 3 A, and Figure 13 B is the viewgraph of cross-section of the line II-II ' interception along Fig. 3 A. Here, will main description upper substrate 150 and/or main isolation structure MS modified example, can be with to the description of remaining constituent element It is interpreted as with content replacement those of is described above.Therefore, its detailed description will be omitted.

3A and Figure 13 B referring to Fig.1, upper substrate 150 ' may include first part 150a and second part 150b.Second 150b is divided to can be set on first part 150a.

The material of first part 150a can be different from the material of second part.First part 150a can be by conductive material It is formed.For example, the conductive material of first part 150a may include metal nitride (for example, TiN, WN etc.), metal silicide (for example, Wsi, TiSi, TaSi etc.) or metal (for example, W etc.).Second part 150b can be formed by polycrystalline silicon material.Example Such as, at least part of second part 150b can be formed by the polysilicon with n-type conductivity.Second part 150b is at least A part can be figure 1 described above and the common source polar curve CSL of Fig. 2.First part 150a can be with vertical channel structure VS is spaced apart.Second part 150b can contact a part of each vertical channel structure VS.

In modified example, main isolation structure MS ' can be formed by insulating materials.For example, the insulation of main isolation structure MS ' Material can be silica, silicon oxynitride or silicon nitride.

As above with reference to being previously mentioned Fig. 3 A to Figure 13 B, in the exemplary embodiment, multiple first pad pass-through zone TH1 It can be set in the elongated area 22 of side for being located at memory cell array region 20.However, example embodiment is without being limited thereto.

Reference Figure 14 is described to the modified example of the arrangement of the first pad pass-through zone TH1.Figure 14 is shown according to example The top view of the modified example of the three-dimensional semiconductor device of embodiment.

With reference to Figure 14, the two sides in memory cell array region 20 are can be set in elongated area 22.Therefore, single storage is single Element array region 20 can be set between a pair of of elongated area 22.

The first above-mentioned pad pass-through zone TH1 can be arranged in this in elongated area 22 in the form of zigzag, wherein Memory cell array region 20 is between the first pad pass-through zone TH1.

As previously described in Fig. 3 A to Figure 14, each first pad pass-through zone TH1 can be by the second main isolation The partitioning portion MS2 ' of structure MS2 is surrounded.However, example embodiment is without being limited thereto.

Such modified example will be described with reference to Figure 15.Figure 15 is the three-dimensional semiconductor device shown according to example embodiment Modified example top view.

With reference to Figure 15, the two sides in memory cell array region 20 are can be set in elongated area 22.As described above, main isolation Structure MS can be across memory cell array region 20 and elongated area 22.Main isolation structure MS can have wherein main isolation junction Structure MS can be parallel to each other and the wire shaped that is separated from each other.

The elongated area 22 in the side for being located at memory cell array region 20 can be set in first pad pass-through zone TH1 It is interior.First pad pass-through zone TH1 can be arranged between main isolation structure MS with line shape in elongated area 22.Such as Upper described, the first pad pass-through zone TH1 being arranged between main isolation structure MS with line shape, which can be set, to be located at In the elongated area 22 of the side in memory cell array region 20.However, example embodiment is without being limited thereto, and can carry out Modification.

Reference Figure 16 is described to the modified example of the arrangement of the first pad pass-through zone TH1 as described above.Figure 16 is to show The top view of the modified example of three-dimensional semiconductor device according to example embodiment out.

With reference to Figure 16, the first pad pass-through zone TH1 be can be set in main isolation structure MS with line shape, and It can be disposed in the form of zigzag in the elongated area 22 of the two sides in memory cell array region 20.Above with reference to Figure 15 Described in 16, the first pad pass-through zone TH1 can be arranged in main isolation structure MS with line shape in elongated area 22 Between.

Reference Figure 17 description is arranged in the example of the elongated area between these main isolation structure MS.Figure 17 is to show root According to the top view of the modified example of the three-dimensional semiconductor device of example embodiment.

With reference to Figure 17, as storage pass-through zone TH3 can be in memory cell array region 20 described in Fig. 9 above It is arranged between main isolation structure MS with line shape.Therefore, with reference to as described in Figure 15 and 16, storage pass-through zone TH3 can To be arranged between main isolation structure MS together with the first pad pass-through zone TH1.

The method that reference Figure 18 A, Figure 18 B and Figure 19 to Figure 24 are described to form the structure of above-mentioned three-dimensional semiconductor device Example.Figure 18 A and Figure 18 B are the process flow charts for showing the method according to the embodiment for forming three-dimensional semiconductor device.Figure 19 and Figure 24 is the saturating of each stage in the method for forming three-dimensional semiconductor device schematically shown according to example embodiment View.

What the type or structure of the material cited below for constituting element can be understood as describing above with reference to Fig. 3 A to Fig. 5 Those contents, and its detailed description will be omitted.Therefore, it will hereinafter omit and partly led above with reference to what Fig. 3 A to Fig. 5 was described The detailed description of the main composition element of body device 10a, and the method for forming this main composition element will be described mainly.

With reference to Figure 18 A, Figure 18 B and Figure 19, the substructure including peripheral circuit PCIR can be formed on lower substrate 105 110(S5).Upper substrate 150 (S10) can be set in substructure 110.

Forming upper substrate 150 may include: to form polycrystalline silicon substrate；Substrate is formed by patterned polysilicon silicon substrate Hole；And intermediate insulating layer 162 is formed on the side surface of patterned polycrystalline silicon substrate, it is formed simultaneously the of filling substrate aperture One gap filling layer 160a and the second gap filling layer 160b.Here, patterned polycrystalline silicon substrate can be upper substrate 150.

Can be formed on upper substrate 150 includes the interlayer insulating film 210 and sacrificial layer 207 alternately and repeatedly stacked Molded structure 205 (S15).Can by the uppermost interlayer insulating film and sacrificial layer 207 in interlayer insulating film 210 most Sacrifice pattern layers above are to form first step 211a.The shape of first step 211a can correspond to above Fig. 3 A extremely The stairstepping of upper gate electrode GE _ U of gate stack structure 270 described in Fig. 5.

It then, can be by the second uppermost interlayer insulating film in interlayer insulating film 210 and second in sacrificial layer 207 Uppermost sacrifice pattern layers are to form the first step 211a and uppermost mould with increased amount of step part Pattern 211b.Uppermost moulded pattern 211b can be formed in the elongated area 22 on upper substrate 150, and can be with that This is spaced apart.

As above described in Fig. 3 A to Fig. 5, in a top view, from memory cell array region 20 to elongated area 22 Direction can be referred to as first direction X, can be referred to as second direction Y perpendicular to the direction of first direction X, and in cross section In view, third direction Z can be referred to as perpendicular to the direction on the surface of upper substrate 150.

The part that can not wherein form first step 211a and uppermost moulded pattern 211b of molded structure 205 Height can be low.In modified example, in order to form first step 211a and uppermost moulded pattern 211b, etching While a part of interlayer insulating film 210 and a part of sacrificial layer 207, it can also etch and be located therein storage to be formed and pass through Wear the mould in the memory cell array region 20 of region (for example, the storage pass-through zone TH3 of Fig. 9 described in Fig. 9 above) Another part of the interlayer insulating film 210 of structure 205 processed and another part of sacrificial layer 207.

With reference to Figure 18 A, Figure 18 B and Figure 20, molded structure 205 can pattern to X is gradually along a first direction to be formed Reduced step part 211c.As described above, step part 211c can be formed as from uppermost moulded pattern 211b with The adjacent part in memory cell array region 20 to the separate memory cell array region 20 of uppermost moulded pattern 211b Another part.Here, the step part 211c that X is gradually decreased along a first direction can be reduced two sacrificial layers 207 and two The thickness of a interlayer insulating film 210.

In the step part 211c that X along a first direction is gradually decreased, it is located at and is handed over uppermost moulded pattern 211b Some step parts in folded region can be relatively high in remaining step part.These step parts can be sacrificial layer 207 step part.

With reference to Figure 18 A, Figure 18 B and Figure 21, being formed on molded structure 205, there is the first penetration opening portion to divide 213a With the first photoetching agent pattern 213 of first step opening portion 213b.First penetration opening portion divides 213a to can be set most upper Between the moulded pattern 211b and first step 211a in face.First penetration opening portion, which divides 213a that can be formed in, will form with reference to figure In the position for the first pad pass-through zone TH1 that 3A to Fig. 5 is described.

In modified example, the first penetration opening portion divides 213a that can be formed as multiple first penetration opening portions and divides 213a, And it can be formed in the position for the storage pass-through zone TH3 that will form Fig. 9 described in above figure 9.

With reference to Figure 18 A, Figure 18 B and Figure 22, the first photoetching agent pattern 213 that Figure 21 can be used loses as etching mask A part of molded structure 205 is carved, runs through sunk area 214a and first step sunk area 214b to form first.It can lead to The a part for the molded structure 205 that the first penetration opening portion that overetch is located at Figure 21 is divided below 213a runs through recessed to form first Region 214a is fallen into, and can be by etching the molded structure 205 below the first step opening portion 213b of Figure 21 A part forms first step sunk area 214b.

With reference to Figure 18 A, Figure 18 B and Figure 23, being formed on molded structure 205, there is the second penetration opening portion to divide 215a With the second photoetching agent pattern 215 of second step opening portion 215b.Second penetration opening portion divides 215a that can be formed as width Run through sunk area 214a wide than first, and at the same time exposure entire first runs through sunk area 214a.Second step opening portion Divide 215b that can be separated from each other on second direction Y.Second step opening portion 215b can be formed such that first step Two side surfaces for being parallel to first direction X of sunk area 214b can be located at the central part of second step opening portion 215b Point.

With reference to Figure 18 A, 18B and Figure 24, the second photoetching agent pattern 215 can be used as etching mask to etch by second Penetration opening portion divides the 215a and second step opening portion 215b molded structure 205 of exposure.Etching molded structure 205 can wrap Etching molded structure 205 is included until that can expose in a part of molded structure 205 between upper substrate 150 and/or exposure first Gap filled layer 160a.The sacrificial layer 207 of the molded structure 205 formed with this technique can be formed to have shape and join above Examine the corresponding step part of stairstepping of the welding disking area P of the gate electrode for the gate stack structure 270 that Fig. 3 A to Fig. 5 is described.

Furthermore, it is possible to divide the molded structure 205 of 215a exposure to form through-hole by the second penetration opening portion by etching 220.Such through-hole 220 can be formed as multiple through-holes 220.Therefore, as described above, molded structure 205 can be patterned To be formed across the through-hole of molded structure 205 and the step part (S20) of molded structure 205.

Referring again to Figure 18 A, Figure 18 B and Fig. 3 A to Fig. 5, filling through-hole can be formed while covering the insulation of step part Layer (S25), when through-hole is formed as multiple through-holes, the insulating layer for filling through-hole can form insulating layer 230, be formed simultaneously the One pad pass-through zone TH1 and/or storage pass-through zone TH3, as above with reference to described in Fig. 3 A to Fig. 5.

Vertical channel structure VS (S30) can be formed by molded structure 205.Vertical channel structure VS can be as above The vertical channel structure VS with reference to described in Fig. 3 A to 5.

Then, it can be formed such as the first covering insulating layer 255 above with reference to described in Fig. 3 A to Fig. 5, and it can be with shape At isolated groove to pass through the first covering insulating layer 255 and molded structure 205 and exposure sacrificial layer 207 (S35).It can remove Sacrificial layer 207 is open (S40) to be formed.

Grid (S45) can be formed in opening.Grid can be such as the grid pile above with reference to described in Fig. 6 A to 13B The gate electrode and second grid dielectric 268 of stack structure 270.

The extrinsic region 272 above with reference to described in Fig. 3 A to Fig. 5 can be formed below isolated groove.It can be isolated Isolation structure (S50) is formed in groove.Isolation structure can be above with reference to Fig. 3 A to Figure 13 A describe main isolation structure MS and Assist isolation structure SS.Then, it can be formed such as the second covering insulating layer 278 above with reference to described in Fig. 3 A to Fig. 5.

Then, peripheral contacts plug can be formed to pass through the insulating layer in through-hole (for example, the first pad pass-through zone TH1 and upper substrate 150) and it is electrically connected to peripheral circuit PCIR (S55).Peripheral contacts plug can be grid peripheral contacts and insert Fill in 284g and/or bit line peripheral contacts plug 284b.

Then, it can be formed such as the upper wiring above with reference to described in Fig. 3 A to Fig. 5.Upper wiring can be grid connection cloth Line 290g and bit line 290b.

Then, by with reference to Figure 25 A to Figure 31 B come describe to be formed step and pass-through zone method example so that as above Face with reference to described in Fig. 3 A to Figure 13 B, the step part of the width in one direction and pass-through zone of step one Width on a direction can be different from each other.

Figure 25 A, Figure 26 A, Figure 27 A, Figure 28 A, Figure 29 A, Figure 30 A and Figure 31 A schematically show stepped area STR The viewgraph of cross-section of a part, to show the example of the method for a part to form step part, Figure 25 B, Figure 26 B, Figure 27 B, Figure 28 B, Figure 29 B, Figure 30 B and Figure 31 B are the viewgraph of cross-section for schematically showing a part of pass-through zone THR, to show Form the example of the method for the side of pass-through zone THR.It is understood that the shape described above with reference to Figure 18 A to Figure 24 At in the method for three-dimensional semiconductor device, can be determined according to the patterned shape of the sacrificial layer 207 of molded structure 205 grid electricity The shape and size of pole and pass-through zone.Therefore, it hereinafter will mainly describe by the patterned method of sacrificial layer 207, still Can recognize from this method as described above across three-dimensional semiconductor device gate electrode pass-through zone shape and The shape of the step part of gate electrode.

With reference to Figure 25 A and Figure 25 B, the upper substrate 150 for being formed with the first gap filling layer 160a thereon can be provided.It can be with The molded structure of the interlayer insulating film 210 and sacrificial layer 207 including alternately and repeatedly stacking is formed on upper substrate 150 205。

The first photoetching agent pattern 415a can be formed on molded structure 205.The first photoetching agent pattern 415a can be used A part of molded structure 205 is etched as etching mask.

Figure 25 A and Figure 25 B show the etching for four sacrificial layers 207 that sequence stacks, but example embodiment is not limited to This.For example, depending on stairstepping to be formed, single sacrificial layer can be etched, or the sacrificial of different number can also be etched Domestic animal layer.

With reference to Figure 26 A and Figure 26 B, the part of molded structure 205 can be etched stage by stage, while reducing the first light stage by stage The size of photoresist pattern 415a is to form the first pad step part 416a and first through step part 417a.First photoresist Pattern 415a, the first photoetching agent pattern 415b, the first photoetching agent pattern 415c and the first photoetching agent pattern 415d can have point The size that stage reduces, and size can be reduced according to the width of step to be formed.Forming the first pad stage portion Divide 416a and first after step part 417a, the first photoetching agent pattern with the size reduced stage by stage can be removed 415a to 415d.

With reference to Figure 27 A to Figure 30 B, stage portion can be run through with formed therein which first pad step part 416a and first Divide on the molded structure 205 of 417a and form the second photoetching agent pattern 420a, and can be used and extremely scheme with above with reference to Figure 25 A The essentially identical method of method of 26B description executes step formation process.

Similar to the first photoetching agent pattern with the size reduced stage by stage described in Figure 25 A to Figure 26 B above 415a to 415d can be sequentially formed the second photoresist figure with the size reduced stage by stage as shown in Figure 27 A to 30B Case 420a, the second photoetching agent pattern 420b, the second photoetching agent pattern 420c and the second photoetching agent pattern 420d.Difference can be executed The second photoetching agent pattern 420a to 420d is used to etch the one of molded structure 205 stage by stage as the etch process of etching mask Part.

The second photoetching agent pattern 420a to 420d with the size reduced stage by stage can be formed as and the first pad platform Exponent part 416a is overlapping, and can be formed as overlapping with first through a part of step part 417a.Therefore, can pass through The second photoetching agent pattern 420a to 420d with the size reduced stage by stage, which is formed, not to be handed over the first pad step part 416a The second folded pad step part 416b has the first pad step part 416a and the second pad step part 416b to be formed Pad step part 425a.In addition, by the second photoetching agent pattern 420a to 420d with the size reduced stage by stage, it can It is formed to have than first with will pass through step part 421b through the horizontal width that step part 417a is narrow.

In addition, with reference to Figure 31 A and Figure 31 B, through the uppermost step of step part 421b and nethermost step it Between horizontal length L2 can than between the uppermost step and nethermost step of pad step part 425a level it is long It is short to spend L1.It is also to be noted that although Figure 31 B represents the first pad for being formed as overlapping with the first gap filling layer 160a Pass-through zone TH1, but any one in pass-through zone TH1 or TH3 can be formed in the same way.

Three-dimensional semiconductor device according to example embodiment may include memory cell array region 20, setting in storage list The elongated area 22 of the one or both sides in element array region 20, across memory cell array region 20 and elongated area 22 and limit The main isolation structure MS of memory block BLK, it is arranged in memory block BLK and extends to the gate stack structure in elongated area 22 270 or 370, it is arranged between main isolation structure MS and in memory cell array region 20 across gate stack structure 270 Vertical channel structure VS and setting in memory cell array region 20 or elongated area 22 and pass through gate stack structure 270 at least one pass-through zone TH1 or TH3.It includes at least one stage portion that at least one pass-through zone TH1 or TH3, which has, The side divided.

Here, at least one step part of the side of at least one pass-through zone TH1 or TH3 is referred to as stepped part Point.At least one pass-through zone TH1 or TH3 can have lower area and the top welding disking area on lower area.This In, the width of the upper area of at least one pass-through zone TH1 or TH3 is wider than the width of lower area.

In the exemplary embodiment, it can be formed at least by the technique of the welding disking area P of formation gate stack structure 270 One pass-through zone TH1 or TH3.Therefore, the additional process for being used to form at least one pass-through zone TH1 or TH3 can be removed To reduce production cost, to improve the productivity of semiconductor devices.Further, since at least one pass-through zone TH1 or TH3 Width can perpendicular to upper substrate 150 and far from upper substrate 150 direction on be segmented increase, so at least one run through area Domain TH1 or TH3 can be formed by the insulating materials of zero defect (for example, gap).

By summarizing and looking back, the one side of embodiment provide a kind of three-dimensional semiconductor device with high integration and Its forming method.That is, according to example embodiment, three-dimensional semiconductor device may include the periphery below gate stack structure Circuit.It is thus possible to increase the integrated level of semiconductor devices.It is furthermore possible to also provide passing through gate stack structure with by grid pile The gate electrode of stack structure is electrically connected to the pass-through zone of peripheral circuit.Therefore, even if the quantity for working as stacked gate electrode increases Added-time can also increase the integrated level of semiconductor devices.In addition, pass-through zone can be formed such that the width in upper part region The width of lower region thereof can be greater than.Accordingly it is possible to prevent or substantially minimize for example can during forming pass-through zone The void defects etc. that can occur.

Example embodiment has been disclosed herein, despite the use of specific term, but they only with generality and are described Property meaning is used and is explained, rather than for purposes of limitation.In some cases, as those skilled in the art exist It submits when the application it is readily apparent that unless expressly stated otherwise, otherwise combining feature, the characteristic of specific embodiment description And/or element can be used alone or be applied in combination with feature, characteristic and/or the element of other embodiments description is combined.Therefore, It will be appreciated by those skilled in the art that not departing from the spirit and scope of the present invention being described in the accompanying claims In the case of, various changes in form and details can be made.

Claims

1. a kind of three-dimensional semiconductor device, the three-dimensional semiconductor device include:

Upper substrate；

Gate stack structure on the upper substrate, the gate stack structure include gate electrode, and the gate electrode is hanging down Directly in being stacked in memory cell array region while being separated from each other on the direction on the surface of the upper substrate, and extend to In the elongated area adjacent with the memory cell array region, to be arranged in the elongated area with stairstepping Shape；And

At least one pass-through zone, at least one described pass-through zone is in the memory cell array region or the elongated area Interior to pass through the gate stack structure, at least one described pass-through zone includes lower area and upper than the lower region field width Portion region.

2. three-dimensional semiconductor device according to claim 1, the three-dimensional semiconductor device further include:

Lower substrate below the upper substrate；

Substructure between the lower substrate and the upper substrate, the substructure includes peripheral circuit；And

The gap filling layer being located across in the substrate aperture of the upper substrate, at least one described pass-through zone are filled out with the gap It is overlapping to fill layer.

3. three-dimensional semiconductor device according to claim 1, wherein the side of at least one pass-through zone includes platform Exponent part.

4. three-dimensional semiconductor device according to claim 3, wherein compared to the upper surface of the gate stack structure, The step part is closer to the lower surface of the gate stack structure.

5. three-dimensional semiconductor device according to claim 1, wherein the side of at least one pass-through zone has rank Trapezoidal shape, and the width of at least one pass-through zone is according to the stairstepping direction described at least one of the side Broaden to the upper segment of a pass-through zone.

6. three-dimensional semiconductor device according to claim 1, in which:

The elongated area includes first step region, second step region and is located at the first step region and described the Buffer area between two stepped areas,

At least one described pass-through zone includes that the first pad of the gate stack structure across the buffer area runs through Region.

7. three-dimensional semiconductor device according to claim 6, in which:

In the first step region, at least part of gate stack structure gate electrode has to be deposited from described The height reduced on storage unit array region to the first direction of the elongated area, and be arranged to perpendicular to described first Direction and be parallel to the upper substrate the surface second direction on height having the same,

In the second step region, at least part of gate stack structure gate electrode has described first The height reduced on direction, and it is arranged to that there is different height in this second direction.

8. three-dimensional semiconductor device according to claim 7, in which:

The part in the first step region of the gate electrode corresponds to upper selection gate electrode, the upper selection gate electrode Including the first welding disking area,

The part in the second step region of the gate electrode corresponds to wordline, and the wordline includes the second pad area Domain,

The first pad pass-through zone is between first welding disking area and second welding disking area.

9. three-dimensional semiconductor device according to claim 8, the three-dimensional semiconductor device further includes second pad The second pad pass-through zone between the wordline in region.

10. three-dimensional semiconductor device according to claim 1, the three-dimensional semiconductor device further include:

Main isolation structure, the main isolation structure limit each across the memory cell array region and the elongated area A memory block；

Vertical channel structure, the vertical channel structure are located at the memory cell array between the main isolation structure In region, and pass through the gate stack structure；

Bit line, the bit line are upwardly extended in the side intersected with the main isolation structure；And

Bit line contact plug, the bit line contact plug, and will be described between the bit line and the vertical channel structure Bit line is electrically connected to the vertical channel structure.

11. three-dimensional semiconductor device according to claim 10, wherein at least one described pass-through zone further includes in institute The storage stated between the main isolation structure of a pair adjacent to each other in the main isolation structure in memory cell array region is passed through Wear region.

12. a kind of three-dimensional semiconductor device, the three-dimensional semiconductor device include:

Lower substrate；

Substructure on the lower substrate, the substructure include peripheral circuit；

Upper substrate in the substructure；

Gap filling layer, the gap filling layer is in the substrate aperture being located in the upper substrate；

Gate stack structure on the upper substrate, the gate stack structure include gate electrode；And

Across the pass-through zone of the gate stack structure, the side of the pass-through zone has step part.

13. three-dimensional semiconductor device according to claim 12, wherein the pass-through zone includes lower area and is located at The width of upper area on the lower area, the upper area is wider than the width of the lower area.

14. three-dimensional semiconductor device according to claim 12, the three-dimensional semiconductor device further include:

Vertical channel structure, the vertical channel structure pass through the gate stack structure；

Peripheral contacts plug, the peripheral contacts plug passes through the pass-through zone and the gap filling layer, and extends to To be electrically connected to the peripheral circuit in the substructure；And

Upper wiring, it is described on be routed on the gate stack structure and in the pass-through zone, at least one upper cloth Line is electrically connected to the peripheral contacts plug.

15. three-dimensional semiconductor device according to claim 14, wherein it is described it is upper wiring include:

Upper grid wiring, the upper grid wiring are electrically connected to the welding disking area of the gate electrode；And

Bit line, the bit line are electrically connected to the vertical channel structure, and at least part upper grid wiring or described Bit line is electrically connected to the peripheral contacts plug.

16. a kind of three-dimensional semiconductor device, the three-dimensional semiconductor device include:

Memory cell array region；

Elongated area, positioned at the two sides in the memory cell array region；

Main isolation structure, the main isolation structure is across the memory cell array region and the elongated area；

Gate stack structure, the gate stack structure is in the memory cell array region and extends to the extension area In domain；

Vertical channel structure, the vertical channel structure is between the main isolation structure, and in the memory cell array area The gate stack structure is passed through in domain；And

At least one pass-through zone, at least one described pass-through zone are located at the memory cell array region or the extension area In domain and the gate stack structure is passed through, the side of at least one pass-through zone has at least one step part.

17. three-dimensional semiconductor device according to claim 16, the three-dimensional semiconductor device further include:

Lower substrate；

Upper substrate in the substructure；And

The gap filling layer being located across in the substrate aperture of the upper substrate, the gap filling layer with it is described at least one run through Region is overlapping,

Wherein, the gate stack structure and the main isolation structure be on the upper substrate,

Wherein, the gate stack structure includes gate electrode, direction of the gate electrode on the surface perpendicular to the upper substrate On be stacked in the memory cell array region while being separated from each other, and extend in the elongated area described There is the welding disking area for being arranged to have stairstepping in elongated area,

Wherein, the width of at least one step part of at least one pass-through zone is than pad area described at least one The width in domain is narrow.

18. three-dimensional semiconductor device according to claim 16, in which:

The main isolation structure includes the main isolation structure of a pair first adjacent to each other and in the pair of first main isolation structure Between a second main isolation structure,

At least one described pass-through zone is arranged at least one described elongated area in the pair of first main isolation Between structure,

The second main isolation structure, across the memory cell array region, and is included in described at least one with single line shape It is divided into a elongated area around the part of at least one pass-through zone.

19. three-dimensional semiconductor device according to claim 18, the three-dimensional semiconductor device further include the master every From the auxiliary isolation structure between structure,

Wherein, the auxiliary isolation structure is in the memory cell array region and the elongated area, and corresponding auxiliary Help the length of isolation structure shorter than the length of the main isolation structure.

20. three-dimensional semiconductor device according to claim 16, in which:

The gate stack structure includes gate electrode, the gate electrode have lower gate electrode, on the lower gate electrode in Between gate electrode, on the intermediate gate electrode buffering gate electrode and positioned at it is described buffering gate electrode at least one on Gate electrode,

The gate electrode at least one has upper welding disking area in the elongated area, and the intermediate gate electrode is in institute Stating has intermediate contact pads region in elongated area,

At least one described pass-through zone passes through described slow between the upper welding disking area and the intermediate contact pads region Rush gate electrode.

21. a kind of method for forming three-dimensional semiconductor device, which comprises

The substructure with peripheral circuit is formed on lower substrate；

Upper substrate is formed in the substructure；

Molded structure is formed on the upper substrate, the molded structure includes the interlayer insulating film alternately and repeatedly stacked And sacrificial layer；

The step of through-hole and the molded structure across the molded structure is formed by patterning the molded structure Part；And

Form the insulating layer for covering the step part and filling the through-hole.

22. according to the method for claim 21, wherein the insulating layer in the through-hole is defined as pass-through zone, The side of the pass-through zone includes at least one step part.

23. the method according to claim 11, the method also includes:

Form the vertical channel structure across the molded structure；

Form the isolated groove across the molded structure and the exposure sacrificial layer；

Opening is formed by removing the sacrificial layer；

Grid is formed in the opening；

Isolation structure is formed in the isolated groove.

24. according to the method for claim 23, wherein at least one described isolation structure, which has, surrounds the pass-through zone Part.

25. according to the method for claim 22, wherein the width of at least one step part of the pass-through zone Width than the step part of the molded structure is narrow.