CN110010696B

CN110010696B - Semiconductor device and method for manufacturing the same

Info

Publication number: CN110010696B
Application number: CN201910007558.5A
Authority: CN
Inventors: 津吹将志
Original assignee: Japan Display Inc
Current assignee: Japan Display Inc
Priority date: 2018-01-05
Filing date: 2019-01-04
Publication date: 2022-06-03
Anticipated expiration: 2039-01-04
Also published as: CN110010696A; JP2019121696A; CN114937702A

Abstract

The invention provides a method for manufacturing a semiconductor device, which comprises the following steps: forming a first gate electrode on a substrate; forming a gate insulating film on the first gate electrode; forming a first oxide semiconductor layer including a region overlapping with the first gate electrode over the gate insulating film; forming a source electrode and a drain electrode on the first oxide semiconductor layer; forming an oxide insulating layer on the source electrode and the drain electrode; forming a second oxide semiconductor layer over the oxide insulating layer by sputtering an oxide semiconductor target in an atmosphere containing oxygen, and adding oxygen to the oxide insulating layer; diffusing oxygen into the first oxide semiconductor layer by performing heat treatment; after the heat treatment is performed, the second oxide semiconductor layer is removed. This can improve the reliability of the transistor of the semiconductor device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

One embodiment of the present invention relates to a semiconductor device including an oxide semiconductor and a method for manufacturing the same.

Background

Conventionally, in a display device such as a liquid crystal display device or an organic EL display device, a transistor using silicon as a semiconductor layer has been used. In recent years, demands for a display device having a large area, high definition, high frame rate, and the like have been increasing, and studies for satisfying these demands have been actively conducted.

Accordingly, development of a transistor formed using an oxide semiconductor instead of silicon has been advanced recently. A transistor using an oxide semiconductor is expected to realize high mobility. In particular, an oxide semiconductor layer formed of IGZO (In-Ga-Zn-O) can be formed at a relatively low temperature over a large area. Therefore, an oxide semiconductor has been attracting attention as a material satisfying the above requirements (see japanese patent application laid-open nos. 2016-146478 and 2016-225651).

However, an insulating film in contact with an oxide semiconductor layer has a problem that deterioration in characteristics of a transistor or the like is likely to occur when the defect level density is high. Further, there is a problem that the characteristics of a transistor using an oxide semiconductor layer greatly fluctuate in the substrate surface.

Disclosure of Invention

In view of the above problems, it is an object of the present invention to provide a semiconductor device in which reliability of a transistor is improved. Alternatively, it is an object of the present invention to provide a semiconductor device in which uniformity of transistor characteristics in a substrate surface is improved.

A method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of: forming a first gate electrode on a substrate; forming a gate insulating film on the first gate electrode; forming a first oxide semiconductor layer including a region overlapping with the first gate electrode over the gate insulating film; forming a source electrode and a drain electrode on the first oxide semiconductor layer; forming an oxide insulating layer on the source electrode and the drain electrode; forming a second oxide semiconductor layer over the oxide insulating layer by sputtering an oxide semiconductor target in an atmosphere containing oxygen, and adding oxygen to the oxide insulating layer; diffusing oxygen into the first oxide semiconductor layer by performing heat treatment; after the heat treatment is performed, the second oxide semiconductor layer is removed. This can improve the reliability of the transistor of the semiconductor device.

A semiconductor device according to an embodiment of the present invention includes: a first gate electrode formed on the substrate; a gate insulating film formed on the first gate electrode; an oxide semiconductor layer overlapping the first gate electrode on the gate insulating film; and an oxide insulating layer formed over the oxide semiconductor layer, wherein indium is included in a first region of the oxide insulating layer, the first region having a thickness of 50nm or less from a surface of the oxide insulating layer.

Thus, a semiconductor device with improved reliability of the transistor can be provided.

Drawings

Fig. 1(a) is a plan view of a semiconductor device according to an embodiment of the present invention, and fig. 1(B) is a cross-sectional view of the semiconductor device according to the embodiment of the present invention.

Fig. 2A is a cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 2B is a cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 2C is a sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 2D is a sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 2E is a cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 2F is a cross-sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 2G is a sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

Fig. 3A is a top view of a semiconductor device according to an embodiment of the present invention.

Fig. 3B is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Fig. 4A is a plan view of a semiconductor device according to an embodiment of the present invention.

Fig. 4B is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Fig. 5A is a plan view of a semiconductor device according to an embodiment of the present invention.

Fig. 5B is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

Fig. 6 is a plan view of a display device according to an embodiment of the present invention.

Fig. 7 is a cross-sectional view of a pixel of a display device according to an embodiment of the present invention.

Fig. 8 is a cross-sectional view of a pixel of a display device according to an embodiment of the present invention.

Fig. 9A is a cross-sectional view of the semiconductor device of the present embodiment.

Fig. 9B is a cross-sectional view of the semiconductor device of the comparative example.

Fig. 10A shows a measurement site of a transistor 510 formed on a substrate 501.

Fig. 10B shows a measurement site of the transistor 610 formed on the substrate 601.

Fig. 11A is a diagram illustrating Id-Vg characteristics of the transistor of the present embodiment.

Fig. 11B is a diagram illustrating Id-Vg characteristics of the transistor of the present embodiment.

Fig. 11C is a diagram illustrating Id-Vg characteristics of the transistor of the present embodiment.

Fig. 11D is a diagram illustrating Id-Vg characteristics of the transistor of this embodiment.

Fig. 12A is a diagram illustrating the Id-Vg characteristics of the transistor of the comparative example.

Fig. 12B is a diagram illustrating the Id-Vg characteristics of the transistor of the comparative example.

Fig. 12C is a diagram illustrating the Id-Vg characteristics of the transistor of the comparative example.

Fig. 12D is a diagram illustrating the Id-Vg characteristics of the transistor of the comparative example.

Fig. 13A is a diagram illustrating Id-Vg characteristics of the transistor of the present embodiment.

Fig. 13B is a graph showing the time dependence of the threshold voltage of the transistor of the present embodiment.

Fig. 14A is a diagram illustrating Id-Vg characteristics of the transistor of the present embodiment.

Fig. 14B is a graph showing the time dependence of the threshold voltage of the transistor of the present embodiment.

Fig. 15A is a diagram illustrating Id-Vg characteristics of the transistor of the present embodiment.

Fig. 15B is a graph showing the time dependence of the threshold voltage of the transistor of the present embodiment.

Fig. 16A is a diagram illustrating the Id-Vg characteristics of the transistor of the comparative example.

Fig. 16B is a graph showing the time dependence of the threshold voltage of the transistor of the comparative example.

Fig. 17A is a diagram illustrating Id-Vg characteristics of the transistor of the comparative example.

Fig. 17B is a graph showing the time dependence of the threshold voltage of the transistor of the comparative example.

Fig. 18A is a diagram illustrating Id-Vg characteristics of a transistor of a comparative example.

Fig. 18B is a graph showing the time dependence of the threshold voltage of the transistor of the comparative example.

Description of reference numerals

100: semiconductor device, 101: substrate, 102: undercoat layer, 110: transistor, 111: gate electrode, 112: gate insulating film, 113: oxide semiconductor layer, 114: drain electrode, 115: drain electrode, 116: oxide insulating layer, 117: oxide semiconductor layer, 118: oxide insulating layer, 121: region, 200: display device, 202: display area, 203: gate drive circuit, 204: data driving circuit, 207: external terminal, 208: pixel, 211: gate line, 212: data line, 213: common line, 214: common wiring, 216: oxide insulating layer, 234: insulating layer, 318: planarizing film, 319: transparent conductive layer, 321: transparent conductive layer, 322: insulating layer, 323: pixel electrode, 324: insulating layer, 325: organic layer, 326: opposing electrode, 330: light-emitting element, 331: inorganic insulating layer, 332: organic insulating layer, 333: inorganic insulating layer, 334: adhesive material, 335: substrate, 339: light-emitting element, 418: planarizing film, 421: pixel electrode, 422: insulating layer, 423: common electrode, 424: liquid crystal layer, 425: planarizing film, 426: color filter, 427: substrate, 430: liquid crystal element, 500: semiconductor device, 501: substrate, 501a to 501 d: regions, 502a to 502 c: measurement points, 510: transistor, 511: gate electrode, 512: gate insulating film, 513: oxide semiconductor layer, 514: source electrode, 515: drain electrode, 516: oxide insulating layer, 600: semiconductor device, 601: substrates, 601a to 601 d: regions, 602a to 602 c: measurement points, 610: a transistor, 611: gate electrode, 612: gate insulating film, 613: oxide semiconductor layer, 614: source electrode, 615: drain electrode, 616: an oxide insulating layer.

Detailed Description

(first embodiment)

In this embodiment, a semiconductor device according to an embodiment of the present invention will be described with reference to fig. 1(a) to 2G. In this embodiment, a structure of a bottom gate transistor will be described.

< Structure of semiconductor device >

Fig. 1(a) is a plan view of the semiconductor device 100 according to the present embodiment, and fig. 1(B) is a cross-sectional view taken along line a 1-a 2 of fig. 1 (a). The semiconductor device 100 includes: a substrate 101, a gate electrode 111 on the substrate 101, a gate insulating film 112 on the gate electrode 111, an oxide semiconductor layer 113 overlapping with the gate electrode 111 on the gate insulating film 112, source and drain

electrodes

114, 115 on the oxide semiconductor layer 113, and an oxide insulating layer 116 on the source and drain

electrodes

114, 115. The transistor 110 is configured by a gate electrode 111, a gate insulating film 112, an oxide semiconductor layer 113, and source and drain

electrodes

114 and 115.

As the substrate 101, a glass substrate, a quartz substrate, or a flexible substrate (polyimide, polyethylene terephthalate, polyethylene naphthalate, cellulose triacetate, a cycloolefin copolymer, a cycloolefin polymer, or another resin substrate having flexibility) can be used. By using a flexible substrate, the semiconductor device 100 can be bent.

As the gate electrode 111, for example,: aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), zinc (Zn), molybdenum (Mo), copper (Cu), indium (In), tin (Sn), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), bismuth (Bi), and the like. In addition, alloys of these metals may also be used. In addition, it is also possible to use: conductive oxides such as ITO (indium tin oxide), IGO (indium gallium oxide), IZO (indium zinc oxide), and GZO (zinc oxide to which gallium is added as a doping element). Further, a structure in which these films are laminated may be employed.

When a flexible substrate is used as the substrate 101, an undercoat layer (not shown) is preferably provided on the substrate 101. The undercoat layer is a film having a function of preventing moisture or hydrogen contained in the substrate 101 from diffusing into the oxide semiconductor layer 113 and the like. As the undercoat layer, there can be used: silicon nitride (SiN)_x) Silicon oxide (SiO)_x) Silicon oxynitride (SiN)_xO_y) Aluminum nitride (AlN)_x) Aluminum oxynitride (AlN)_xO_y) Aluminum oxide (AlO)_x) And the like (x and y are arbitrary integers).

As the gate insulating film 112, there can be used: silicon nitride (SiN)_x) Silicon oxynitride (SiN)_xO_y) Oxygen, oxygenSilicon (SiO)_x) Aluminum nitride (AlN)_x) Aluminum oxynitride (AlN)_xO_y) Aluminum oxide (AlO)_x) Aluminum oxynitride (AlO)_xN_y) And the like (x and y are arbitrary integers). The gate insulating film 112 may be provided in a single-layer structure or a stacked structure using the above-described materials. The insulating layer in contact with the oxide semiconductor layer 113 is preferably an insulating layer containing oxygen such as a silicon oxide film.

The oxide semiconductor layer 113 may contain a group 13 element such as indium or gallium. The compound may contain a plurality of different group 13 elements, and may be a compound of Indium and Gallium (IGO). The oxide semiconductor layer 113 may further contain a group 12 element, and for example, a compound containing indium, gallium, and zinc (IGZO) is given. The oxide semiconductor layer 113 may contain other elements, tin which is a group 14 element, titanium or zirconium which is a group 4 element, or the like.

As the oxide semiconductor layer 113, specifically: InO_x、ZnO_xSnOx, In-Ga-O, In-Zn-O, In-Al-O, In-Sn-O, In-Hf-O, In-Zr-O, In-W-O, In-Y-O, In-Ga-Zn-O, In-Al-Zn-O, In-Sn-Zn-O, In-Hf-Zn-O, In-Ga-Sn-O, In-Al-Sn-O, In-Hf-Sn-O, In-Ga-Al-Zn-O, In-Ga-Hf-Zn-O, In-Sn-Ga-Zn-O and the like. The crystallinity of the oxide semiconductor layer 113 is not limited, and may be single crystal, polycrystalline, microcrystalline, or amorphous. The oxide semiconductor layer 113 preferably has fewer crystal defects such as oxygen vacancies as well. In addition, the oxide semiconductor layer 113 preferably has low hydrogen concentration.

The oxide insulating layer 116 may use silicon oxide (SiO)_x) Silicon oxynitride (SiO)_xN_y) Aluminum oxide (AlO)_x) Aluminum oxynitride (AlO)_xN_y) And the like (x and y are arbitrary integers). The oxide insulating layer 116 is preferably a film capable of releasing oxygen by heat treatment. In addition, the oxide insulating layer 116 preferably has a small defect level density.

The semiconductor device 100 according to one embodiment of the present invention reduces the defect level density of the oxide insulating layer 116. In addition, oxygen vacancies in the oxide semiconductor layer 113 are reduced. Therefore, the characteristic fluctuation of the transistor 110 can be reduced. This can improve the reliability of the semiconductor device including the transistor 110.

< method for manufacturing semiconductor device >

Next, a method for manufacturing the semiconductor device 100 according to one embodiment of the present invention will be described with reference to fig. 2A to 2G.

Fig. 2A is a diagram illustrating a step of forming a gate electrode 111 and a gate insulating film 112 on a substrate 101.

The gate electrode 111 is formed by forming a conductive film on the substrate 101, and then patterning the conductive film into a desired shape. The conductive film is formed in a single-layer structure or a stacked structure by a sputtering method using the above-described materials. The thickness of the gate electrode 111 is preferably 100nm to 500 nm.

Next, a gate insulating film 112 is formed on the gate electrode 111. The gate insulating film 112 is formed to have a single-layer structure or a stacked-layer structure by a sputtering method or a plasma CVD method using the above-described materials. The film thickness of the gate insulating film 112 is preferably 100nm to 500 nm. In addition, as the gate insulating film 112, a material which can release oxygen by heat treatment is preferably used. As the gate insulating film 112, for example, a silicon oxide film is preferably used. After the oxide semiconductor layer 113 is provided in contact with the gate insulating film 112, oxygen is released from the gate insulating film 112 by heat treatment.

Fig. 2B is a diagram illustrating a step of forming the oxide semiconductor layer 113. The oxide semiconductor layer 113 is formed by forming an oxide semiconductor film over the gate insulating film 112, and then patterning the oxide semiconductor film to form a desired shape. The oxide semiconductor film is preferably formed by a sputtering method at 30nm to 100nm, for example.

The power source applied to the oxide semiconductor target may be a Direct Current (DC) or an Alternating Current (AC), and may be determined by the shape, composition, and the like of the oxide semiconductor target. As the oxide semiconductor target, for example, In if InGaZnO is used: ga: zn: o is 1: 1: 1: 4 (In)₂O₃：Ga₂O₃: 1 ZnO: 1: 2) and the like. The composition ratio may be determined by the characteristics of the transistor and the likeThe purpose is determined.

As a sputtering gas for forming the oxide semiconductor film, there can be used: oxygen, a mixed gas of oxygen and a rare gas, or a rare gas. The sputtering gas for forming the oxide semiconductor film is preferably performed in a mixed gas atmosphere of an oxygen gas and a rare gas, and the flow ratio of the oxygen gas to the rare gas is more preferably 5% or more. The oxygen gas flow rate ratio is preferably 5% or more, because oxygen can be easily added to the oxide insulating layer 216.

In addition, the oxide semiconductor layer 113 may be subjected to heat treatment. The heat treatment may be performed before or after the patterning of the oxide semiconductor film. Since the oxide semiconductor layer 113 may have a small volume (shrink) by heat treatment, it is preferable to perform heat treatment before patterning. Further, by performing heat treatment on the oxide semiconductor layer 113, film quality improvement such as reduction in hydrogen concentration and increase in density of the oxide semiconductor layer 113 can be performed.

The heat treatment performed on the oxide semiconductor layer 113 is performed in the presence of nitrogen, dry air, or atmosphere and at atmospheric pressure or low pressure (vacuum). The heating temperature is 250 to 500 ℃, preferably 350 to 450 ℃. The heating time is, for example, 15 minutes to 1 hour. By the heat treatment, oxygen is introduced into oxygen vacancies in the oxide semiconductor layer 113 or oxygen is rearranged, whereby the oxide semiconductor layer 113 having few crystal defects and high crystallinity can be obtained. In addition, the hydrogen concentration in the oxide semiconductor layer 113 can be reduced by heat treatment.

Fig. 2C is a diagram illustrating a step of forming the source and drain

electrodes

114 and 115 over the oxide semiconductor layer 113. The source and drain

electrodes

114 and 115 are formed by forming a conductive film over the oxide semiconductor layer 113 and then patterning the conductive film into a desired shape. The conductive film is formed in a single-layer structure or a stacked structure by a sputtering method using the above-described materials. The film thickness of the source and drain

electrodes

114 and 115 is preferably 100nm to 800 nm.

When the conductive film over the oxide semiconductor layer 113 is processed into a desired shape, damage may occur to the surface of the oxide semiconductor layer 113. The damaged region 121 contains many oxygen vacancies. The region 121 corresponds to a back channel region of the transistor. As shown in fig. 1(a), the oxide semiconductor layer 113 is exposed from the source and drain

electrodes

114 and 115. When the region 121 contains many oxygen vacancies, the characteristics of the transistor may be deteriorated.

Therefore, it is preferable to supply oxygen to the region 121 where the oxide semiconductor layer 113 is damaged to fill the oxygen vacancy. This can reduce oxygen vacancies contained in the oxide semiconductor layer 113.

In this embodiment mode, an oxide insulating layer 116 is formed over the oxide semiconductor layer 113. Fig. 2D illustrates a step of forming the oxide insulating layer 116 over the oxide semiconductor layer 113. The oxide insulating layer 116 is formed by a plasma CVD method using the above-described materials in a single-layer structure or a stacked-layer structure. The thickness of the gate insulating film 112 is preferably 100nm to 500 nm. In addition, as the oxide insulating layer 116, a material which can release oxygen by heat treatment is preferably used. As the oxide insulating layer 116, for example, a silicon oxide film is preferably used. After the oxide insulating layer 116 is provided in contact with the oxide semiconductor layer 113, oxygen is released from the oxide insulating layer 116 by heat treatment. The oxygen thus released can fill the damaged region 121 of the oxide semiconductor layer 113 with oxygen. This can reduce oxygen vacancies contained in the oxide semiconductor layer 113.

However, in the oxide insulating layer which releases oxygen by heat treatment, there is a layer having a high defect level density. In addition, when oxygen is released to the outside of the oxide insulating layer by the heat treatment, the defect level density of the oxide insulating layer may be further increased. In the case where the density of defect levels in the oxide insulating layer is high, the transistor starts operating, and when voltage stress is applied to the gate insulating film and the oxide insulating layer, electrons are trapped by the defect levels. As a result, it is possible to fluctuate the threshold voltage of the transistor by the trapped electrons.

Therefore, not only the oxygen vacancy contained in the oxide semiconductor layer 113 needs to be filled, but also the defect level density of the oxide insulating layer needs to be reduced. Therefore, oxygen is added to the oxide insulating layer 116, and a barrier film that prevents oxygen from being released to the outside of the oxide insulating layer 116 by heat treatment is provided over the oxide insulating layer 116. In this embodiment mode, the oxide semiconductor layer 117 is provided over the oxide insulating layer 116 as a barrier film for preventing oxygen from being released to the outside of the oxide insulating layer 116.

Fig. 2E is a diagram illustrating a step of forming the oxide semiconductor layer 117 over the oxide insulating layer 116. The oxide semiconductor layer 117 is formed under the same conditions as the oxide semiconductor layer 113 described with reference to fig. 2B. The oxide semiconductor layer 117 is preferably formed to have a thickness of 5nm to 60nm by an AC sputtering method or a DC magnetron sputtering method, for example.

As a sputtering gas for forming the oxide semiconductor layer 117, there can be used: oxygen, a mixed gas of oxygen and a rare gas, or a rare gas. The sputtering gas for forming the oxide semiconductor layer 117 is preferably performed in a mixed gas atmosphere of oxygen and a rare gas, and the oxygen flow rate ratio is more preferably 5% or more.

The oxide semiconductor layer 117 is formed by a sputtering method, and oxygen is added to the oxide insulating layer 116. This can increase the oxygen contained in the oxide insulating layer 116. In addition, the defect level density included in the oxide insulating layer 116 can be reduced.

As the oxide semiconductor layer 117, specifically, the following can be used: InO_x、ZnO_x、SnO_xIn-Ga-O, In-Zn-O, In-Al-O, In-Sn-O, In-Hf-O, In-Zr-O, In-W-O, In-Y-O, In-Ga-Zn-O, In-Al-Zn-O, In-Sn-Zn-O, In-Hf-Zn-O, In-Ga-Sn-O, In-Al-Sn-O, In-Hf-Sn-O, In-Ga-Al-Zn-O, In-Ga-Hf-Zn-O, In-Sn-Ga-Zn-O and the like.

The power applied to the target may be either Direct Current (DC) or Alternating Current (AC), depending on the shape and composition of the target, etc. As the target, for example, In case of InGaZnO, In: ga：Zn：O＝1：1：1：4(In₂O₃：Ga₂O₃: 1 ZnO: 1: 2) and the like.

When the material of the oxide semiconductor layer 117 is the same as the material of the oxide semiconductor layer 113, simplification of a manufacturing process can be achieved, which is preferable. For example, In the case where In-Ga-Zn-O is used for the oxide semiconductor layer 113, In-Ga-Zn-O is preferably used for the oxide semiconductor layer 117. In this way, when the material of the oxide semiconductor layer 117 is the same as the material of the oxide semiconductor layer 113, the film formation conditions and the like can be made the same without changing the target, and therefore, the productivity of the semiconductor device is improved. In one embodiment of the present invention, the material of the oxide semiconductor layer 117 may be different from the material of the oxide semiconductor layer 113. In one embodiment of the present invention, for example, In the case where In-Ga-Zn-O is used for the oxide semiconductor layer 113, In-Ga-Zn-O is preferably used for the oxide semiconductor layer 117.

The oxide semiconductor layer 117 preferably has a low hydrogen concentration. When hydrogen is mixed in the oxide semiconductor layer 117, carriers are generated, which causes a shift in threshold voltage, deterioration in characteristics of a transistor, and deterioration in reliability of a semiconductor device using the transistor. Therefore, as the insulating layer in contact with the oxide semiconductor layer 113, a film having a low hydrogen concentration is effectively used. In this embodiment, the hydrogen concentration of the oxide semiconductor layer 117 is set to 1 × 10¹⁹atom/cm³Hereinafter, it is preferably set to 1 × 10¹⁸atom/cm³。

In addition, the oxide semiconductor layer 117 preferably contains a large amount of oxygen. In other words, the element coefficient of the structural formula of the oxide semiconductor layer 117 is preferably a nonstoichiometric coefficient which does not become a simple integer ratio. When oxygen is contained in a large amount in the oxide semiconductor layer 117, the oxygen barrier function of the oxide semiconductor layer 117 is improved.

The carrier concentration of the oxide semiconductor layer 117 is set to 1 × 10¹³cm^-31X 10 above²⁰cm^-3Hereinafter, it is preferably set to 1 × 10¹⁴cm^-31X 1 above0¹⁶cm^-3The following.

The thickness of the oxide semiconductor layer 117 is preferably smaller than the thickness of the oxide semiconductor layer 113. The thickness of the oxide semiconductor layer 117 is preferably larger than the thickness of the region 121 in which oxygen vacancies are more formed in the oxide semiconductor layer 113. For example, if the film thickness of the oxide semiconductor layer 113 is 50nm, the film thickness of the oxide semiconductor layer 117 is preferably 20 nm. Specifically, the film thickness of the oxide semiconductor layer 117 is preferably 5nm to 50 nm. When the thickness is less than 5nm, the thickness may be smaller than the thickness of the region 121 having many oxygen vacancies, so that the oxygen vacancies are sufficiently filled. In addition, if it is 50nm, the oxygen vacancy in the region 121 can be sufficiently filled.

By forming the oxide semiconductor layer 117 over the oxide insulating layer 116 in this manner, oxygen can be added to the oxide insulating layer 116 when the oxide semiconductor layer 117 is formed. Further, after the oxide semiconductor layer 117 is formed, oxygen can be prevented from being released to the outside.

Fig. 2F is a diagram for explaining a step of performing heat treatment on the oxide insulating layer 116 and the oxide semiconductor layer 117. The heat treatment may be performed in the presence of nitrogen, dry air, or the atmosphere, and at atmospheric pressure or low pressure (vacuum). The temperature of the heat treatment is 300 ℃ to 400 ℃. The heating time is, for example, 15 minutes to 1 hour.

By the heat treatment, oxygen is released from the oxide insulating layer 116. By providing the oxide semiconductor layer 117 over the oxide insulating layer 116, oxygen of the oxide insulating layer 116 can be suppressed from being released to the outside. Thereby, oxygen is efficiently supplied to the region 121 where damage is generated in the oxide semiconductor layer 113. Further, oxygen vacancies contained in the region 121 can be reduced because oxygen can be supplemented to the oxygen vacancies.

Finally, by removing the oxide semiconductor layer 117, the semiconductor device 100 shown in fig. 2G can be manufactured.

When the oxide semiconductor layer 117 is formed over the oxide insulating layer 116, oxygen can be added to the oxide insulating layer 116. By oxygen added when the oxide semiconductor layer 117 is formed, the defect level density included in the oxide insulating layer 116 can be reduced.

The oxide semiconductor layer 117 can suppress oxygen release from the oxide insulating layer 116 to the outside by heat treatment. This allows oxygen to be filled into oxygen vacancies formed in the region 121 of the oxide semiconductor layer 113 during formation of the source or drain

electrodes

114 and 115. Therefore, oxygen vacancies in the oxide semiconductor layer 113 can be reduced. This can suppress the fluctuation in the characteristics of the transistor, and therefore, the reliability of the transistor can be improved.

When the oxide semiconductor layer 117 contains indium, the indium contained in the oxide semiconductor layer 117 may diffuse into the oxide insulating layer 116 by heat treatment. In addition, when the oxide semiconductor layer 117 is formed, a mixture with the oxide insulating layer 116 may be generated. Accordingly, indium is contained in a region of the oxide insulating layer 116 having a thickness of 50nm or less from the surface. The concentration of indium contained in this region can be measured by Secondary Ion Mass Spectrometry (SIMS). Indium contained in the region of the oxide insulating layer 116 is, for example, 1 × 10¹⁷atoms/cm³1X 10 above¹⁸atoms/cm³. Even if indium is diffused into the oxide insulating layer 116, the amount of indium is very small and the indium is a region distant from the channel as described above, and therefore characteristics of the transistor are not affected. In addition, since indium is uniformly diffused in the oxide insulating layer 116, indium functions as a conductive shielding material. This prevents the influence of charging (charge up) of the planarization film or the like.

Further, by forming an insulating film such as an aluminum oxide film over the oxide insulating layer 116, release of oxygen from the oxide insulating layer 116 to the outside by heat treatment can also be suppressed. However, the aluminum oxide film is formed by reactive sputtering using an aluminum target and oxygen as a sputtering gas. Since the surface of the aluminum target is oxidized by the oxygen in the sputtering gas, electrons are easily charged on the surface of the target. Thus, a large number of particles are generated on the target surface by the occurrence of abnormal discharge. Further, since oxygen to be injected when forming the aluminum oxide film depends only on the sputtering gas, the amount of oxygen to be injected may vary in a portion near a gas injection port of a sputtering apparatus, and the uniformity of the amount of oxygen to be added to the oxide insulating layer 116 in the substrate surface may be low. Therefore, the amount of oxygen supplied to the oxide semiconductor layer 113 also differs on the substrate surface. Therefore, the characteristic fluctuation of the transistor increases in the substrate plane. In addition, the aluminum oxide film has difficulty in achieving control of the etching rate.

The oxide semiconductor layer 117 described in this embodiment mode can use an oxide semiconductor target. As the oxide semiconductor target, the same one as that used for forming the oxide semiconductor layer 113 is used. Therefore, even if oxygen is used as the sputtering gas, the surface state of the oxide semiconductor target is rarely changed. In addition, since the oxide semiconductor target has conductivity, electrons can be suppressed from being charged on the surface of the oxide semiconductor target. This can suppress abnormal discharge on the surface of the oxide semiconductor target, and thus can suppress generation of particles. In addition, since the IGZO can suppress the conductivity of the target, AC magnetron sputtering or DC magnetron sputtering can be used even in an oxide state, and even a large-area substrate does not have such a problem. When the oxide semiconductor layer 117 is formed, the substrate surface uniformity of oxygen added to the oxide insulating layer 116 is high. Therefore, the uniformity of the amount of oxygen supplied to the oxide semiconductor layer 113 is high in the substrate surface. Therefore, within the substrate 101 plane, the characteristic fluctuation of the transistor can be reduced. In this embodiment, since the oxide semiconductor layer 117 is removed, the control of the etching rate may not be considered in the subsequent steps.

(second embodiment)

In this embodiment, a semiconductor device 100A according to an embodiment of the invention will be described with reference to fig. 3A and 3B. In this embodiment, a structure of a double-gate transistor will be described. Note that the same structure and steps as those of the semiconductor device of the first embodiment will not be described.

< Structure of semiconductor device >

Fig. 3A is a plan view of the semiconductor device 100 according to this embodiment, and fig. 3B is a cross-sectional view taken along line B1-B2 in fig. 3A. The semiconductor device 100A includes: a substrate 101A, a gate electrode 111A on the substrate 101A, a gate insulating film 112A on the gate electrode 111A, an oxide semiconductor layer 113A overlapping with the gate electrode 111 on the gate insulating film 112A, source and

drain electrodes

114A, 115A on the oxide semiconductor layer 113A, and an oxide insulating layer 116A on the source and

drain electrodes

114A, 115A. The transistor 110A is configured by the gate electrode 111A, the gate insulating film 112A, the oxide semiconductor layer 113A, and the source and

drain electrodes

114A and 115A.

The semiconductor device 100A shown in fig. 3B is different from the semiconductor device 100 shown in fig. 1(a) and 1(B) in that the gate electrode 118A overlaps with the oxide semiconductor layer 113A over the oxide insulating layer 116A. The gate electrode 118A functions as a back gate electrode for controlling the threshold voltage of the transistor 110A. By controlling the potential applied to the gate electrode 118A, the threshold voltage of the transistor 110A can be controlled.

< method for manufacturing semiconductor device >

Next, a method for manufacturing the semiconductor device 100A according to this embodiment will be described. In the semiconductor device 100A, the oxide insulating layer 116A and the oxide semiconductor layer 117A are subjected to heat treatment in accordance with the steps of fig. 2A to 2F described in the first embodiment. Thereafter, the oxide semiconductor layer 117A is removed, and a gate electrode 118A which overlaps with the oxide semiconductor layer 113A is formed over the oxide insulating layer 116A. The gate electrode 118A is formed by forming a conductive film over the oxide insulating layer 116A, and then patterning the conductive film to form a desired shape. The conductive film is formed by a sputtering method using the materials described for the gate electrode 111 shown in fig. 1(a) and 1 (B).

In order to supply oxygen to a region where damage is generated in the oxide semiconductor layer 113A, the oxide insulating layer 116A is preferably thick. However, as described in the steps of fig. 2A to 2F, by forming the oxide semiconductor layer 117 over the oxide insulating layer 116 and performing heat treatment, release of oxygen from the oxide insulating layer 116 to the outside can be suppressed. Therefore, oxygen can be efficiently supplied to the oxide semiconductor layer 113A. Therefore, the film thickness of the oxide insulating layer 116A can be reduced as compared with the case where the heat treatment is performed without being covered with the oxide semiconductor layer 117. This makes it easy to provide the gate electrode 118A on the oxide insulating layer 116A and control the voltage. In addition, when the oxide semiconductor layer 117 is removed, the amount of oxygen supplied to the oxide semiconductor layer 113A may decrease due to a reaction with the gate electrode 118A. By removing the heat treatment and the oxide semiconductor layer 117 in advance, these problems can be prevented.

(third embodiment)

In this embodiment, a semiconductor device 100B according to an embodiment of the invention will be described with reference to fig. 4A to 5B. In this embodiment, a structure of a channel protective transistor will be described. Note that the same structure and steps as those of the semiconductor device of the first embodiment will not be described.

< Structure of semiconductor device >

Fig. 4A is a plan view of the semiconductor device 100B according to this embodiment, and fig. 4B is a cross-sectional view taken along the line C1-C2 in fig. 4A. The semiconductor device 100B includes: the semiconductor device includes a substrate 101B, a gate electrode 111B on the substrate 101B, a gate insulating film 112B on the gate electrode 111B, an oxide semiconductor layer 113B overlapping the gate electrode 111B on the gate insulating film 112B, an oxide insulating layer 116B on the oxide semiconductor layer 113B, and source and drain

electrodes

114B and 115B provided on the oxide insulating layer 116B and connected to the oxide semiconductor layer 113B through an opening. The transistor 110B is configured by the gate electrode 111B, the gate insulating film 112B, the oxide semiconductor layer 113B, and the source and drain

electrodes

114B and 115B.

The semiconductor device 100B shown in fig. 4B is different from the semiconductor device 100 shown in fig. 1(a) and 1(B) in that an oxide insulating layer 116B is provided over an oxide semiconductor layer 113B, and source and drain

electrodes

114B and 115B are provided over the oxide insulating layer 116B and connected to the oxide semiconductor layer 113B through openings.

< method for manufacturing semiconductor device >

Next, a method for manufacturing the semiconductor device 100B according to this embodiment will be described with reference to fig. 5A and 5B. In the semiconductor device 100A, the oxide semiconductor layer 113B is formed on the gate insulating film 112B in accordance with the steps of fig. 2A and 2B described in the first embodiment. Fig. 5A is a diagram showing a state after the oxide semiconductor layer 113B is formed on the gate insulating film 112B.

Next, as illustrated in fig. 5B, an oxide insulating layer 116B is formed over the oxide semiconductor layer 113B. The oxide insulating layer 116B is formed in the same manner as the oxide insulating layer 116 described with reference to fig. 2D. Next, an oxide semiconductor layer 117B is formed over the oxide insulating layer 116B. The method for forming the oxide semiconductor layer 117B is the same as the method for forming the oxide semiconductor layer 117B described with reference to fig. 2E. Next, the oxide insulating layer 116B and the oxide semiconductor layer 117B are subjected to heat treatment. The conditions of the heat treatment are the same as those of the heat treatment described with reference to fig. 2F. Next, the oxide semiconductor layer 117B is removed.

Next, an opening portion is formed in the oxide insulating layer 116B. Next, source and drain

electrodes

114B and 115B which are provided over the oxide insulating layer 116B and connected to the oxide semiconductor layer 113B through the openings are formed. The source and drain

electrodes

114B and 115B are formed by forming a conductive film over the oxide insulating layer 116B and then patterning the conductive film into a desired shape. The conductive film is formed by a sputtering method using the materials described for the source and drain

electrodes

114 and 115 shown in fig. 1(a) and 1 (B).

Since damage to the back channel is less during manufacturing compared to a bottom gate transistor, oxygen vacancies can be reduced. Further, by providing the oxide insulating layer 116B so as to be in contact with the oxide semiconductor layer 113B, oxygen can be supplied to the oxide semiconductor layer 113B. This can suppress the fluctuation in the characteristics of the transistor 110B, and therefore can improve the reliability of the semiconductor device 100B.

(fourth embodiment)

In this embodiment, a display device 200 according to an embodiment of the present invention will be described with reference to fig. 6 and 7. The display device 200 is an example of a display device using the semiconductor device 100 of the first embodiment. Note that the semiconductor device 100A and the semiconductor device 100B according to the second embodiment and the third embodiment may be used as transistors used in the display device 200.

< overview of the display device 200 >

Fig. 6 is a plan view schematically showing a display device 200 according to an embodiment of the present invention. Fig. 6 is a simplified circuit diagram of a transistor array substrate in which transistors and wirings are arranged. The transistor array substrate includes a plurality of pixels 208 arranged in a matrix of M rows and N columns (M and N are both natural numbers). Each pixel 208 is connected to a common wiring 214. A region where a plurality of pixels 208 are provided is referred to as a display region 202.

The gate driver circuit 203 is a driver circuit for selecting a row to which a data signal corresponding to the gradation of each pixel 208 is supplied. The gate line 211 extending in the first direction D1 is connected to the gate driver circuit 203. The gate line 211 is a driving circuit for supplying a data signal to each pixel 208. The data driving circuit 204 is connected to a data line 212 extending in the second direction D2. The data line 212 is provided in a manner corresponding to each pixel 208. The common line 214 is a line for supplying a common voltage to the pixels 208. The common wiring 214 is connected in common to the pixels 208 via a common line 213 extending in the first direction D1. The data driving circuit 204 sequentially supplies data signals to the pixels in the row selected by the gate driving circuit 203.

The gate driver circuit 203 and the data driver circuit 204 are connected to the driver IC205 via respective wires. The data driving circuit 204 may be provided inside the driving IC 205. The common wiring 214 is also connected to the driver IC 205. The driver IC205 is connected to the FPC206 via a terminal. An external terminal 207 for connection to an external device is provided on the FPC 206.

< Structure 1 of the pixel 208 >

In this embodiment, a case of a top emission type organic EL display device will be described as a display device. Fig. 7 is a cross-sectional view of the pixel 208. The pixel 208 has at least the transistor 110 and the light-emitting element 330 of the first embodiment over the substrate 101.

In fig. 7, an undercoat layer 102 is provided between a substrate 101 and a gate electrode 111. By providing the undercoat layer 102, diffusion of moisture or hydrogen from the substrate 101 to the oxide semiconductor layer 113 and the like can be suppressed.

An oxide insulating layer 116 is provided over the transistor 110. Further, a planarization film 318 is provided over the oxide insulating layer 116. As the planarization film 318, polyimide, polyamide, acrylate, epoxy resin, or the like can be used. These materials can be formed into a film by a solution coating method, and have advantages such as a high planarization effect. Further, an opening portion is provided in the oxide insulating layer 116 and the planarization film 318.

Transparent

conductive layers

319 and 321 are provided on the planarization film 318. The transparent conductive layer 319 is connected to the source electrode or the drain electrode 115 through the opening. As the transparent

conductive layers

319 and 321, for example, an indium oxide transparent conductive film (e.g., ITO) or a zinc oxide transparent conductive film (e.g., IZO or ZnO) can be used. An insulating layer 322 is provided over the transparent

conductive layers

319 and 321. As the insulating layer 322, a silicon oxide film or a silicon nitride film can be used.

A pixel electrode 323 is provided on the insulating layer 322. In this embodiment, the pixel electrode 323 functions as an anode. For example, in the case of a top emission type, a metal film having a high reflectance may be used as the pixel electrode 323. Alternatively, the pixel electrode 323 can have a stacked structure of a metal film and a transparent conductive layer having a high work function, such as an indium oxide-based transparent conductive layer (e.g., ITO) or a zinc oxide-based transparent conductive layer (e.g., IZO or ZnO). In the case of the bottom emission type, the transparent conductive layer described above can be used as the pixel electrode 323.

An insulating layer 324 is provided on the pixel electrode 323. As the insulating layer 324, there can be used: polyimide-based, polyamide-based, acrylate-based, epoxy-based, or siloxane-based organic resins. The insulating layer 324 has an opening in a part over the pixel electrode 323. The insulating layer 324 is provided so as to cover an end portion of the pixel electrode 323, and functions as a member for separating adjacent pixel electrodes 323. Therefore, the insulating layer 324 is also commonly referred to as a "partition wall" or a "bank". A part of the pixel electrode 323 exposed from the insulating layer 324 becomes a light-emitting region of the light-emitting element 330. The opening of the insulating layer 324 is preferably formed such that the inner wall thereof has a tapered shape. This can reduce coverage failure in the formation of a later-formed organic layer. The insulating layer 234 can cover not only the edge portion of the pixel electrode 323 but also function as a filling material for filling a concave portion due to the opening portion of the planarizing film 318 and the insulating layer 322.

An organic layer 325 is disposed on the pixel electrode 323. The organic layer 325 has at least a light-emitting layer made of an organic material, and functions as a light-emitting portion of the light-emitting element 330. The organic layer 325 includes various charge transport layers such as an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer, in addition to the light emitting layer. The organic layer 325 is provided so as to cover the light-emitting region, that is, the opening portion of the insulating layer 324 of the light-emitting region.

In this embodiment mode, the organic layer 325 includes a light-emitting layer that emits light of a desired color. In addition, an organic layer 325 having a different light emitting layer is provided on each pixel electrode. Thus, the display device can display each color of RGB. That is, in this embodiment mode, the light-emitting layer of the organic layer 325 is discontinuous between the adjacent pixel electrodes 323. In addition, various charge transport layers are continuous between the adjacent pixel electrodes 323. The organic layer 325 may be formed using a known structure and a known material, and is not particularly limited. The organic layer 325 has a light-emitting layer emitting white light, and the display device can display each of RGB colors by a color filter. In this case, the organic layer 325 may also be disposed on the insulating layer 324.

An opposite electrode 326 is provided on the insulating layer 324 and the organic layer 325. In the present embodiment, the counter electrode 326 functions as a cathode. Since the display device 200 of this embodiment mode is of a top emission type, a transparent electrode can be used as the counter electrode 326. As a thin film constituting the transparent electrode, a MgAg thin film or a transparent conductive layer (ITO or IZO) can be used. The opposite electrode 326 is also disposed on the insulating layer 324 across the pixels. The counter electrode 326 is electrically connected to an external terminal through the underlying conductive layer in the peripheral region near the end of the display region.

In this embodiment mode, the light-emitting element 330 is formed of the pixel electrode 323 (anode), the organic layer 325, and the counter electrode 326 (cathode).

An inorganic insulating layer 331, an organic insulating layer 332, and an inorganic insulating layer 333 are provided on the counter electrode 326. The inorganic insulating layer 331, the organic insulating layer 332, and the inorganic insulating layer 333 function as sealing films for preventing moisture or oxygen from entering the light-emitting element 330. By providing a sealing film over the light-emitting element 339, moisture or oxygen can be prevented from entering the light-emitting element 330. This can improve the reliability of the display device.

As the inorganic insulating layer 331 and the inorganic insulating layer 333, for example, there can be used: silicon nitride (Si)_xN_y) Silicon oxynitride (SiO)_xN_y) Alumina (Al)_xO_y) Aluminum nitride (Al)_xN_y) Aluminum oxynitride (Al)_xO_yN_z) Aluminum oxynitride (Al)_xN_yO_z) And the like (x, y, z are arbitrary integers). As the organic insulating layer 332, an organic resin such as polyimide, acrylate, epoxy, silicone, fluorine, or siloxane can be used.

On the inorganic insulating layer 333, a substrate 335 is provided via a bonding material 334. As the adhesive material 334, for example, there can be used: and adhesive materials such as acrylate, rubber, silicone, and urethane. The binder 334 may contain a hygroscopic substance such as calcium or zeolite. Since the binder 334 contains a hygroscopic substance, even when moisture enters the display device 200, the moisture can be delayed from reaching the light-emitting element 330.

As the substrate 335, a glass substrate, a quartz substrate, or a flexible substrate (polyimide, polyethylene terephthalate, polyethylene naphthalate, cellulose triacetate, a cycloolefin copolymer, a cycloolefin polymer, or another resin substrate having flexibility) can be used.

The adhesive 334 may be provided with a spacer to secure a gap between the substrate 101 and the substrate 335. Such a spacer may be mixed in the adhesive material 334, or may be formed on the substrate 101 from a resin or the like.

As the pixel 208 of the display device 200, the transistor 110 according to one embodiment of the present invention can be used. The transistor 110 can suppress fluctuation in characteristics. Accordingly, the reliability of the display device 200 can be improved. In addition, the characteristic fluctuation of the transistor 110 in the substrate plane can be suppressed. This makes it easy to control the gradation of the light-emitting element.

(fifth embodiment)

In this embodiment, a display device according to an embodiment of the present invention will be described with reference to fig. 6 and 8. In this embodiment, a case where a liquid crystal element is used as the pixel 208 shown in fig. 6 will be described. In addition, although the example in which the semiconductor device 100 according to the first embodiment is used is described in the pixel 208, the semiconductor device 100A and the semiconductor device 100B according to the second embodiment and the third embodiment may be used.

< Structure 2 of the pixel 208 >

In this embodiment, a case of a liquid crystal display device will be described as a display device. Fig. 8 is a cross-sectional view of the pixel 208. The pixel 208 has at least the transistor 110 and the liquid crystal element 430 of the first embodiment over the substrate 101.

An oxide insulating layer 116 is provided over the transistor 110. Further, a planarization film 418 is provided on the oxide insulating layer 118. As the planarization film 418, polyimide, polyamide, acrylate, epoxy resin, or the like can be used. These materials can be formed into a film by a solution coating method, and have advantages such as a high planarization effect. Further, an opening portion is provided in the oxide insulating layer 116 and the planarization film 418.

A pixel electrode 421 is provided on the planarization film 418. As the pixel electrode 421, for example, an indium oxide transparent conductive film (e.g., ITO) or a zinc oxide transparent conductive film (e.g., IZO or ZnO) can be used. The pixel electrode 421 is connected to the source electrode or the drain electrode 115 through the opening. In addition, the pixel electrode 421 is separated for each pixel in a planar view and is formed in a comb-tooth shape.

An insulating layer 422 is provided on the pixel electrode 421. As the insulating layer 422, a silicon oxide film or a silicon nitride film can be used. A common electrode 423 is provided on the insulating layer 422. As the common electrode 423, the same material as the pixel electrode 421 can be used. The common electrode 423 is provided so as to straddle each pixel in a plan view, and an opening is provided in a region overlapping with the transistor 110.

A color filter 426 and a planarizing film 425 are provided on the substrate 427. In addition, a liquid crystal layer 424 is provided between the planarization film 425 and the common electrode 423.

As the pixel 208 of the display device 200, the transistor 110 according to one embodiment of the present invention is used. The transistor 110 can suppress characteristic fluctuations. Therefore, the reliability of the display device 200 can be improved. In addition, the characteristic fluctuation of the transistor 110 in the substrate plane can be suppressed.

[ example 1 ]

In this example, a semiconductor device of the present invention was fabricated, and fluctuation in Id-Vg characteristics of transistors in a substrate plane was examined, and the results of the examination were described.

First, a semiconductor device 500 manufactured in this example will be described with reference to fig. 9A.

As shown in fig. 9A, the semiconductor device 500 includes, on a substrate 501: a gate electrode 511, a gate insulating film 512 over the gate electrode 511, an oxide semiconductor layer 513 overlapping the gate electrode 511 over the gate insulating film 512, a source electrode 514 and a drain electrode 515 over the oxide semiconductor layer 513, and an oxide insulating layer 516 over the source electrode 514 and the drain electrode 515. In addition, the transistor 510 is configured by a gate electrode 511, a gate insulating film 512, an oxide semiconductor layer 513, a source electrode 514, and a drain electrode 515.

Next, a method for manufacturing the semiconductor device 500 shown in fig. 9A will be described. First, a gate electrode 511 is formed on a substrate 501. As the gate electrode 511, MoW of 200nm was formed by a DC sputtering method and patterned. Next, a gate insulating film 512 is formed over the gate electrode 511. As the gate insulating film 512, a silicon nitride film of 150nm and a silicon oxide film of 100nm were formed by a plasma CVD method. Next, an oxide semiconductor layer 513 is formed over the gate insulating film 512 so as to overlap with the gate electrode 511. As the oxide semiconductor layer 513, an IGZO film of 75nm was formed on the gate insulating film 512 by an AC sputtering method, and patterning was performed. Next, a source electrode 514 and a drain electrode 515 are formed over the oxide semiconductor layer 513. As the source electrode 514 and the drain electrode 515, 50nm Ti, 200nm Al, and 50nm Ti were stacked and patterned on the oxide semiconductor layer 513 by a sputtering method. Next, an oxide insulating layer 516 is formed over the source electrode 514 and the drain electrode 515. The oxide insulating layer 516 is formed into a 300nm silicon oxide film by a plasma CVD method.

Next, an oxide semiconductor layer is formed over the oxide insulating layer 516. The oxide semiconductor layer was subjected to AC sputtering to form an IGZO film having a thickness of 30 nm. Next, heat treatment is performed on the oxide insulating layer 516 and the oxide semiconductor layer. The conditions of the heat treatment were set to a dry air atmosphere at 350 ℃ for 30 minutes. Finally, the oxide semiconductor layer is removed. Through the above steps, the semiconductor device 500 including the transistor 510 is formed. A plurality of transistors 510 is formed over the substrate 501.

Next, a semiconductor device 600 manufactured as a comparative example will be described with reference to fig. 9B.

As shown in fig. 9B, the semiconductor device 600 includes, on a substrate 601: a gate electrode 611, a gate insulating film 612 over the gate electrode 611, an oxide semiconductor layer 613 overlapping the gate electrode 611 over the gate insulating film 612, a source electrode 614 and a drain electrode 615 over the oxide semiconductor layer 613, and an oxide insulating layer 616 over the source electrode 614 and the drain electrode 615. In addition, the transistor 610 is configured by a gate electrode 611, a gate insulating film 612, an oxide semiconductor layer 613, a source electrode 614, and a drain electrode 615.

Next, a method for manufacturing the semiconductor device 600 shown in fig. 9B will be described. The semiconductor device 600 is formed under the same conditions as the steps of forming the gate electrode 511, the gate insulating film 512, the oxide semiconductor layer 513, the source electrode 514, the drain electrode 515, and the oxide insulating layer 516 on the substrate 501 of the semiconductor device 500 up to the step of forming the gate electrode 611, the gate insulating film 612, the oxide semiconductor layer 613, the source electrode 614, the drain electrode 615, and the oxide insulating layer 616 on the substrate 601. Thereafter, heat treatment is performed without forming an oxide semiconductor layer. The conditions of the heat treatment were set to be a dry air atmosphere at 350 ℃ for 30 minutes. Through the above steps, the semiconductor device 600 including the transistor 610 is formed. A plurality of transistors 610 are formed over a substrate 601.

The Id-Vg characteristic fluctuation of the transistor 510 in the plane of the substrate 501 was investigated. Id-Vg characteristics were measured for 200 transistors 510 out of the plurality of transistors 510 formed on the substrate 501. Fig. 10A shows a portion of the substrate 501 where the Id-Vg characteristic of the transistor 510 is measured. The portion indicated by x shown in fig. 10A is a portion where the Id-Vg characteristic of the transistor 510 is measured.

For the measurement of the Id-Vg characteristic of the transistor 510, a voltage (Vg) applied to the gate electrode 511 of the transistor 510 is applied from-15V to +15V in steps of 0.1V. In addition, the voltage (Vs) applied to the source electrode 514 is set to 0V, and the voltage (Vd) applied to the drain electrode 515 is set to 0.1V and 10V. The Id-Vg characteristic was determined at room temperature.

The Id-Vg characteristic fluctuation of the transistor 610 in the plane of the substrate 601 was examined. Id-Vg characteristics were measured for 200 transistors 610 out of the plurality of transistors 610 formed on the substrate 601. Fig. 10B shows a portion of the substrate 601 where the Id-Vg characteristic of the transistor 610 is measured. The region indicated by x in fig. 10B is a region where the Id-Vg characteristic of the transistor 610 is measured.

The Id-Vg characteristic measurement of the transistor 610 is performed under the same conditions as the Id-Vg characteristic measurement of the transistor 510.

Fig. 11A to 11D are the results of the Id-Vg characteristic of the transistor 510 of the present embodiment. Fig. 11A is the result of the Id-Vg characteristic of the transistor 510 of the region 501A. Fig. 11B is the result of the Id-Vg characteristic of the transistor 510 of the region 501B. Fig. 11C is the result of the Id-Vg characteristic of the transistor 510 of the region 501C. Fig. 11D is the result of the Id-Vg characteristic of the transistor 510 of region 501D. The average value and the standard deviation (3 σ) of the distribution of the threshold voltages of the 200 transistors 510 are Vth ═ 0.42V ± 0.48V (3 σ).

Fig. 12A to 12D are results of Id-Vg characteristics of the transistor 610 of the comparative example. Fig. 12A is the result of the Id-Vg characteristic of the transistor 610 of the region 601 a. Fig. 12B is the result of the Id-Vg characteristic of the transistor 610 of the region 601B. Fig. 12C is the result of the Id-Vg characteristic of the transistor 610 of the region 601C. Fig. 12D is the result of the Id-Vg characteristic of the transistor 610 of the region 601D. The average value and the standard deviation (3 σ) of the threshold voltage distributions of the 200 transistors 610 are 0.35V ± 1.01V (3 σ) Vth.

Table 1 shows threshold voltage Vth and field effect mobility μ for 200

transistors

510 and 610_FESubthreshold S values the results of the mean and standard deviation (σ) were investigated.

[ TABLE 1 ]

As shown in fig. 12A to 12D, in the transistor 610 of the comparative example, it was confirmed that the transistor 610 had large characteristic variations in any of the regions 601a to 601b of the substrate 601. In contrast, as shown in fig. 11A to 11D, in the transistor 510 of the present embodiment, it was confirmed that the fluctuation in the characteristics of the transistor 510 was small in any of the regions 501A to 501b of the substrate 501.

As is clear from the above results, the semiconductor device of the present invention exhibits less variation in transistor characteristics in the substrate plane.

[ example 2 ]

In this example, a semiconductor device of the present invention was manufactured, reliability of a transistor was evaluated, and the evaluation result was explained.

The semiconductor device 500 of this example was manufactured under the same configuration and conditions as those of the semiconductor device 500 shown in example 1. A semiconductor device 600 of a comparative example was fabricated under the same configuration and conditions as those of the semiconductor device 600 shown in example 1.

Next, the manufactured semiconductor device 500 and the semiconductor device 600 were subjected to a bias-thermal stress test (hereinafter, referred to as a GBT test). In the GBT test of this example, the gate voltage (Vg) was set to +30V, the drain voltage (Vd) and the source voltage (Vs) were set to 0V, the stress temperature was set to 60 ℃, and the measurement environment was set to dark. In addition, Id-Vg characteristics of the transistor 510 and the transistor 610 were measured at stress times of 0sec, 100sec, 500sec, 1000sec, 1500sec, 2000sec, and 3600sec, respectively.

Fig. 13A shows the Id-Vg characteristic of the transistor 510 at the central measurement point 502a of the substrate 501. Fig. 13B is a graph showing the time dependence of the threshold voltage Vth of the transistor 510 at the central measurement point 502a of the substrate 501. Fig. 14A shows the result of measuring the Id-Vg characteristic of the transistor 510 at the central measurement point 502b of the region 501a of the substrate 501. Fig. 14B is a graph showing the time dependence of the threshold voltage Vth of the transistor 510 at the central measurement point 502B of the region 501a of the substrate 501. Fig. 15A shows the result of Id-Vg characteristics of the transistor 510 at the end portion measurement point 502c of the region 501a of the substrate 501. Fig. 15B is a graph showing the time dependence of the threshold voltage Vth of the transistor 510 at the end portion measurement point 502c of the region 501a of the substrate 501. In fig. 13A, 14A, and 15A, Id-Vg characteristics of the transistor 510 at 0sec, 1500sec, and 3600sec are shown, respectively.

Fig. 16A shows the Id-Vg characteristic of the transistor 610 at the central measurement point 602a of the substrate 601. Fig. 16B is a graph showing the time dependence of the threshold voltage Vth of the transistor 610 at the central measurement point 602a of the substrate 601. Fig. 17A shows the Id-Vg characteristic of the transistor 610 at the central measurement point 602b of the region 601a of the substrate 601. Fig. 17B is a graph showing the time dependence of the threshold voltage Vth of the transistor 610 at the central measurement point 602B of the region 601a of the substrate 601. Fig. 18A shows the result of Id-Vg characteristics of the transistor 610 at the end measurement point 602c of the region 601a of the substrate 601. Fig. 18B is a graph showing the time dependence of the threshold voltage Vth of the transistor 610 at the end portion measurement point 602c of the region 601a of the substrate 601. Fig. 16A, 17A, and 18A show Id-Vg characteristics of the transistor 610 at 0sec, 1500sec, and 3600sec, respectively.

Table 2 shows the fluctuation value Δ Vth of the threshold voltage at each of the measurement points 502a to 502c and 602a to 602 c.

[ TABLE 2 ]

In the transistor 610 of comparative example 1, the threshold voltage Δ Vth after 3600sec exhibited fluctuations of 2V to 7V at the measurement points 602a to 602 c. In contrast, in the transistor 510 of the embodiment, the threshold voltage Δ Vth after 3600sec fluctuates only about 1V at the measurement points 502a to 502 c. Thus, in the transistor of the present embodiment, it was confirmed that the fluctuation of the threshold voltage of the transistor was smaller than that of the transistor of the comparative example.

From the above results, it is understood that the semiconductor device of the present invention can improve the reliability of the transistor.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

a first gate electrode is formed on a substrate,

forming a gate insulating film on the first gate electrode,

forming a first oxide semiconductor layer including a region overlapping with the first gate electrode over the gate insulating film,

forming a source electrode and a drain electrode on the first oxide semiconductor layer,

an oxide insulating layer is formed on the source and drain electrodes,

forming a second oxide semiconductor layer containing indium over the oxide insulating layer by sputtering an oxide semiconductor target in an atmosphere containing oxygen, and adding oxygen to the oxide insulating layer,

by performing heat treatment, the oxygen is diffused into the first oxide semiconductor layer and contained at a concentration of 1 × 10 in a first region of the oxide insulating layer having a thickness of 50nm or less from the surface¹⁷atoms/cm³1X 10 above¹⁸atoms/cm³The following is an example of indium which,

after the heat treatment is performed, the second oxide semiconductor layer is removed.

2. The method for manufacturing a semiconductor device according to claim 1, wherein:

the film thickness of the second oxide semiconductor layer is smaller than the film thickness of the first oxide semiconductor layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein:

the second oxide semiconductor layer has a carrier concentration of 1 × 10¹³cm^-31X 10 above²⁰cm^-3The following.

4. The method for manufacturing a semiconductor device according to claim 1, wherein:

the temperature of the heat treatment is 300 ℃ to 400 ℃.

5. The method for manufacturing a semiconductor device according to claim 1, wherein:

the oxygen flow rate ratio to the rare gas in the sputtering is 30% or more.

6. The method for manufacturing a semiconductor device according to claim 1, wherein:

the material of the second oxide semiconductor layer is the same as that of the first oxide semiconductor layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein:

the first oxide semiconductor layer and the second oxide semiconductor layer contain at least indium, gallium, and zinc.

8. The method for manufacturing a semiconductor device according to claim 1, wherein:

a material of the second oxide semiconductor layer is different from a material of the first oxide semiconductor layer.

9. The method for manufacturing a semiconductor device according to claim 8, wherein:

the first oxide semiconductor layer and the second oxide semiconductor layer contain at least indium.

10. The method for manufacturing a semiconductor device according to claim 1, wherein:

after the second oxide semiconductor layer is removed, a second gate electrode overlapping with the first oxide semiconductor layer is formed over the oxide insulating layer.

11. A semiconductor device, comprising:

a first gate electrode formed on the substrate;

a gate insulating film formed on the first gate electrode;

an oxide semiconductor layer overlapping with the first gate electrode on the gate insulating film; and

an oxide insulating layer formed on the oxide semiconductor layer,

indium is contained in a first region of the oxide insulating layer having a thickness of 50nm or less from the surface,

the indium contained in the first region has a concentration of 1 × 10¹⁷atoms/cm³1X 10 above¹⁸atoms/cm³The following.

12. The semiconductor device according to claim 11, wherein:

the oxide insulating layer further has a second gate electrode overlapping with the oxide semiconductor layer.