CN110010505A - The production method of semiconductor subassembly - Google Patents
The production method of semiconductor subassembly Download PDFInfo
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- CN110010505A CN110010505A CN201810223925.0A CN201810223925A CN110010505A CN 110010505 A CN110010505 A CN 110010505A CN 201810223925 A CN201810223925 A CN 201810223925A CN 110010505 A CN110010505 A CN 110010505A
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- 238000000034 method Methods 0.000 description 58
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- 239000000463 material Substances 0.000 description 22
- 238000005389 semiconductor device fabrication Methods 0.000 description 19
- 238000010586 diagram Methods 0.000 description 16
- 238000005520 cutting process Methods 0.000 description 10
- 239000003989 dielectric material Substances 0.000 description 6
- 238000009826 distribution Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000012986 modification Methods 0.000 description 5
- 238000013461 design Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
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- 229920001721 polyimide Polymers 0.000 description 2
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- 238000003780 insertion Methods 0.000 description 1
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- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of production methods of semiconductor subassembly, including providing a substrate, a sacrificial layer is formed on substrate, multiple first chips are set on sacrificial layer, then one first dielectric layer is formed, and first dielectric layer surround the multiple first chip, form multiple grooves in first dielectric layer, and form one second dielectric layer in the trench.Wherein the upper surface of the first dielectric layer and the upper surface of the second dielectric layer are generally aligned in the same plane.
Description
Technical field
The present invention relates to a kind of production method of semiconductor subassembly, in particular to the encapsulation production side of a kind of semiconductor subassembly
Method.
Background technique
With development in science and technology, electronic product becomes product indispensable in life, and wherein semiconductor subassembly is electronics production
One of key component of product.In general, semiconductor subassembly needs to apply in various electronic product by encapsulation procedure,
Such as mobile phone, computer, digital camera, wearable device etc..However, the encapsulating structure of conventional semiconductor devices can be because of package material
Material inside stress problem, cause encapsulating structure to be easy to happen warpage, therefore, the packaging method of conditional electronic component still need into
One step improves.
Summary of the invention
The present invention provides a kind of production method of semiconductor subassembly, comprising: provides a substrate, forms one on substrate and sacrifice
Layer；Multiple first chips are set on sacrificial layer；One first dielectric layer is formed, and the first dielectric layer surrounds the multiple first core
Piece；Multiple grooves are formed in first dielectric layer；And one second dielectric layer is formed in the trench.Wherein first dielectric layer
Upper surface and the upper surface of the second dielectric layer are generally aligned in the same plane.
The present invention also provides a kind of production methods of semiconductor subassembly, comprising: provides a substrate；It is sacrificial that one is formed on substrate
Domestic animal layer；A resin layer is formed on sacrificial layer；Multiple first chips are set on sacrificial layer；And it is formed with multiple grooves
One first dielectric layer, and the first dielectric layer surrounds the multiple first chip.
Wherein the upper surface of the first dielectric layer and the upper surface of resin layer are generally aligned in the same plane.
The present invention also provides a kind of production method of semiconductor subassembly again, comprising: provides a substrate；It is formed on the substrate
One sacrificial layer；Multiple first chips are set on sacrificial layer；Form one first dielectric layer with multiple grooves, and the first dielectric
Layer surrounds the multiple first chip；And one second dielectric layer is formed in the trench at least one.Wherein the first dielectric
The upper surface of layer and the upper surface of the second dielectric layer are generally aligned in the same plane.
Detailed description of the invention
Fig. 1 to Fig. 5 is the first embodiment processing procedure schematic diagram of semiconductor device fabrication method of the present invention.
Fig. 6 is the first dielectric layer of alternate embodiment of the present invention and the partial enlargement diagram of the second dielectric layer.
Fig. 7 is the second embodiment processing procedure schematic diagram of semiconductor device fabrication method of the present invention.
Fig. 8 to Fig. 9 is the 3rd embodiment processing procedure schematic diagram of semiconductor device fabrication method of the present invention.
Figure 10 is the first alternate embodiment processing procedure schematic diagram of the 3rd embodiment of semiconductor device fabrication method of the present invention.
Figure 11 to Figure 13 is the fourth embodiment processing procedure schematic diagram of semiconductor device fabrication method of the present invention.
Figure 14 to Figure 17 is the 5th embodiment processing procedure schematic diagram of semiconductor device fabrication method of the present invention.
Figure 18 to Figure 20 is the sixth embodiment processing procedure schematic diagram of semiconductor device fabrication method of the present invention.
Figure 21 is the alternate embodiment schematic top plan view of the sixth embodiment of semiconductor device fabrication method of the present invention.
Figure 22 is the flow chart of first embodiment of semiconductor device fabrication method of the present invention.
Figure 23 is the flow chart of the second embodiment of semiconductor device fabrication method of the present invention.
Figure 24 is the 5th embodiment flow chart of semiconductor device fabrication method of the present invention.
Reference signs list: 100- substrate；102- sacrificial layer；104, the first chip of 104'-；104a,204a,104a',
204a'- joint sheet；104b', 204b'- conducting wire；108- groove；The first dielectric layer of 106-；106a,110a,116a,120a,
The upper surface 120a'-；The lower surface 106b, 110b-；The second dielectric layer of 110-；112,212- reassigns layer；114,214- soldered ball；
116- resin layer；118- mold；118a- protrusion；120,220,120', 220'- encapsulating structure；204, the second core of 204'-
Piece；206- encapsulating material；The lower surface 220a, 220a'-；300- stacked package body；The region A-；DL- cutting line；H1- first is high
Degree；The second height of H2-；SP- separating ball；S10~S20, S40~S48, S60~S68- step.
Specific embodiment
To enable those skilled in the art to be further understood that the present invention, following spy enumerates the embodiment of the present invention, and matches
Close the attached drawing constitution content that the present invention will be described in detail and it is to be reached the effect of.It is noted that attached drawing is simplified signal
Figure, therefore, only shows component related to the present invention and syntagmatic, to basic framework of the invention or implementation method offer
Clearer description, and actual component and layout are likely more complexity.In addition, for convenience of explanation, each attached drawing of the invention
Shown in component equal proportion drafting not done with the number, shape, size of actual implementation, detailed ratio can be according to design
Demand be adjusted.
Furthermore when in the present specification use term " includes " and/or " having " when, which specify the feature, region,
Step, operation and/or the presence of component, but be not precluded other one or more features, region, step, operation, component and/
Or combinations thereof presence or increase.When a component (or its modification, such as layer or region) is referred to as " another component (or its
Modification) on " or when " extending on another component ", it can directly on another component or be extended directly on another component,
Or both between there may also be the components of insertion.On the other hand, when one component of title is " directly in another component (or its modification)
On " or when " extending directly on another component ", plug-in package is not present between the two.Also, when a component is referred to as " coupling
Connect " to when another component (or its modification), it can be directly connected to another component or is connected indirectly by one or more components
(for example, electric connection) is connect to another component.
Notice is known, below for several embodiments can without departing from the spirit of the present invention, by several implementations
Feature in example is replaced, recombinates, mixing to complete other embodiments.
Fig. 1 to Fig. 5 is please referred to, Fig. 1 to Fig. 5 is that the first embodiment processing procedure of semiconductor device fabrication method of the present invention is illustrated
Figure.The production method of semiconductor subassembly of the present invention is described below, as shown in Figure 1, a substrate 100 is provided first, then in substrate
A sacrificial layer 102 is formed on 100 surfaces, wherein substrate 100 be exemplified as transparent rigid substrate (such as, but not limited to glass) or its
He can be used as the substrate (such as, but not limited to soft support plate) of support plate.Then, multiple first chips are set on sacrificial layer 102
104, wherein 104 surface of the first chip may include multiple joint sheet 104a, positioned at the first chip 104 in contrast to sacrificial layer 102
Side.After setting up the first chip 104, one first dielectric layer 106 is formed on sacrificial layer 102, wherein the first dielectric layer 106
The first chip 104 is surrounded, and the first dielectric layer 106 can cover the upper surface of the first chip 104.First dielectric layer 106 can be to appoint
What common encapsulating material, such as (but not limited to) epoxy resin.
Referring to FIG. 2, then removing part of first dielectric layer 106, grinding (grind) system is such as, but not limited to carried out
Journey so that the upper surface 106a of the first dielectric layer 106 it is flat and generally with the upper surface joint sheet 104a of the first chip 104 position
In same plane, and expose the joint sheet 104a of the first chip 104.In the present invention, conplane to mean, the first core
The upper surface 106a of the upper surface of the joint sheet 104a of piece 104 and the first dielectric layer 106 to joined in parallel pad the upper surface 104a it
The distance of one plane of reference is roughly the same.Then, multiple grooves 108 are formed in the first dielectric layer 106, wherein groove 108 is illustrated
But it is not limited to be located between the first adjacent chip 104.Groove 108 in the present embodiment does not extend through the first dielectric layer 106, but
In other embodiments, groove 108 can have different depth according to need, such as can run through the first dielectric layer 106.Groove
108 depth will be described herein-after.The generation type of groove 108 is exemplified as flywheel knife cutting, plasma-based cutting or laser cutting, but
It is not limited.After having made groove 108, the second dielectric layer 110 is formed, such as in groove 108 with dispensing, spraying, wire mark
Etc. modes the second dielectric layer 110 is inserted in groove 108, but the generation type of the second dielectric layer 110 is not limited with above-mentioned.Second
Dielectric layer 110 can be any commonly employed dielectric material or encapsulating material, and the material of the second dielectric layer 110 may be the same or different in
First dielectric layer 106.For example, 110 use of the second dielectric layer of the present embodiment has different heat swollen from the first dielectric layer 106
The material of swollen coefficient (coefficient of temperature expansion, CTE), material are exemplified as polyimide
(polyimide, PI), can also be underfill (underfill), glue class (glue) material or other suitable materials, and
The material of second dielectric layer 110 of the invention is not limited with above-mentioned.
Referring to FIG. 3, the second dielectric layer of part 110 for being higher than 106 upper surface of the first dielectric layer is then removed, so that first
The upper surface 110a of the upper surface 106a of dielectric layer 106 and the second dielectric layer 110 is substantially located at same plane, that is, first is situated between
The upper surface 110a of the upper surface 106a of electric layer 106 and the second dielectric layer 110 is to the upper surface for being parallel to the first dielectric layer 106
The distance of one of 106a plane of reference is roughly the same.The method for removing the second dielectric layer of part 110 is exemplified as carrying out a grinding processing procedure,
But not limited to this.Layer is reassigned referring to FIG. 4, being formed on the first dielectric layer 106 and the second dielectric layer 110
(redistribution layer, RDL) 112, wherein the conducting wire reassigned in layer 112 is electrically connected to the through joint sheet 104a
One chip 104, and production method of the invention also optionally forms multiple soldered balls 114 on reassigning layer 112, wherein respectively
Soldered ball 114 can be electrically connected respectively to one of them first chip 104, such as soldered ball 114 can pass through and reassign layer 112 and via right
The joint sheet 104a for the first chip 104 answered and be electrically connected to the circuit in the first chip 104.However, in certain embodiments,
It may be designed in not each soldered ball 114 to be electrically connected with the first chip 104.
Next referring to Fig. 5, a removing processing procedure is carried out, is detached from the first chip 104 from sacrificial layer 102 and substrate 100.It
Afterwards, cutting processing procedure is carried out, can make each first chip 104 disconnected from each other along cutting line DL, to complete to include the first chip 104
Semiconductor subassembly encapsulating structure 120, the encapsulating structure 120 after cutting can retain or not retain the second dielectric layer 110.Due to
The joint sheet 104a of first chip 104 is located at side of first chip 104 in contrast to sacrificial layer 102, therefore encapsulating structure 120 can
It is considered as the encapsulating structure of joint sheet (face up) formula upward.
As previously mentioned, the groove 108 in first embodiment does not extend through the first dielectric layer 106, therefore insert in groove 108
The second dielectric layer 110 thickness less than the first dielectric layer 106 thickness.However, groove 108 can have in alternate embodiment
There is different depth.Referring to FIG. 6, Fig. 6 is the first dielectric layer 106, the second dielectric layer 110, sacrificial layer 102 and substrate 100
Partial enlargement diagram corresponds to region A shown in Fig. 3, and shows the first dielectric layer 106 in alternate embodiment and the
The relative altitude of two dielectric layers 110.In Fig. 6, the first dielectric layer 106 has the first height H1, upper surface 106a and lower surface
106b, wherein upper surface 106a is opposite with lower surface 106b, and the calculation of the first height H1 is upper surface 106a and following table
The distance between face 106b；Second dielectric layer 110 has the second height H2, upper surface 110a and lower surface 110b, wherein upper table
Face 110a is opposite with lower surface 110b, and the calculation of the second height H2 between upper surface 110a and lower surface 110b away from
From.Such as part (A) of Fig. 6, groove 108 can run through the first dielectric layer 106 and extend downwardly, or even arrive through sacrificial layer 102
Up to the upper surface of substrate 100, therefore the first height H1 possessed by the first dielectric layer 106 is less than the second dielectric layer in groove 108
Second height H2 possessed by 110.In part (B) of Fig. 6, groove 108 is only sacrificial without extending to through the first dielectric layer 106
Domestic animal layer 102, therefore the first height H1 of the first dielectric layer 106 is substantially equal to the second height of the second dielectric layer 110 in groove 108
H2.In part (C) of Fig. 6, groove 108 does not extend through the first dielectric layer 106, such as but not limited to this, the depth of groove 108
For the half of the first height H1, therefore the first height H1 of the first dielectric layer 106 is greater than the second height of the second dielectric layer 110
H2, and the second height H2 is 0.5 to the ratio (H2/H1) of the first height H1.It can be seen from the above, the present invention is forming groove 108
When, can have different designs according to need so that the first dielectric layer 106 and the second dielectric layer 110 have it is different relatively high
Degree.According to the present invention, the second height H2 is 0.5 to 1.5 to the ratio range (H2/H1) of the first height H1.That is, this hair
It is bright to have continuous first dielectric layer 106 or discontinuous first dielectric layer 106.
The present invention is by the formation groove 108 in the first dielectric layer 106, and the second dielectric layer is formed in groove 108
110, to adjust the stress distribution of 120 dielectric material of encapsulating structure, such as by the way that groove 108 and the second dielectric layer 110 is arranged,
The stress in dielectric layer can be made discontinuous, to avoid encapsulating structure 120 occur warpage issues, such as because of high temperature process caused by
Warpage.
Please refer to Figure 22, Figure 22 is the flow chart of first embodiment of semiconductor device fabrication method of the present invention, by it is above-mentioned can
Know, the production method of semiconductor subassembly of the present invention can comprise the following steps that
Step S10: a substrate is provided；
Step S12: a sacrificial layer is formed on substrate；
Step S14: multiple first chips are set on sacrificial layer；
Step S16: the first dielectric layer is formed, and the first dielectric layer surrounds the first chip；
Step S18: multiple grooves are formed in the first dielectric layer；And
Step S20: the second dielectric layer, the upper surface of the upper surface of the first dielectric layer and the second dielectric layer are formed in the trench
It is generally aligned in the same plane.In other words, the upper surface of the upper surface of the first dielectric layer and the second dielectric layer is to being parallel to the first dielectric
The distance of one plane of reference of the upper surface of layer is roughly the same.
The production method of semiconductor subassembly of the present invention may also include to form the reassignment layer for being electrically connected to the first chip, and
It is detached from the first chip from sacrificial layer, wherein first embodiment is to be initially formed reassignment layer to make the first chip de- from sacrificial layer again
From.
The production method of semiconductor subassembly of the invention is not limited with above-described embodiment.It will hereafter continue to disclose the present invention
Other embodiments or variation shape, to simplify the explanation and highlight each embodiment or change shape between difference, hereinafter use
Identical label marks same components, and the repeated section will not be repeated repeats.In addition, each film material in subsequent embodiment of the present invention
It all can refer to first embodiment with the condition of thickness and fabrication steps, therefore repeat no more.
Referring to FIG. 7, Fig. 7 is the processing procedure schematic diagram of the second embodiment of the production method of semiconductor subassembly of the present invention.This
First dielectric layer that is different in of embodiment and first embodiment with groove is formed by mold.According to the present embodiment,
It further include providing a mold 118, and mold 118 includes multiple prominent after being arranged the first chip 104 on sacrificial layer 102
Part 118a is played, corresponding to the predetermined position for forming groove.Then, substrate 100 is placed in mould together with the first chip 104 thereon
Have in 118, then dielectric material is poured into mold 118, makes its solidification, the first dielectric with multiple grooves 108 can be formed
Layer 106.After forming first dielectric layer 106 with multiple grooves 108, mold 118 can be removed, second Jie can be re-formed later
Electric layer 110 reassigns layer 112 and soldered ball 114, such as first embodiment, makes the second dielectric layer 110 and the first dielectric layer 106
Upper surface is substantially located at same plane, wherein it is both above-mentioned be generally aligned in the same plane be meant that the upper of the first dielectric layer 106
Surface substantially phase at a distance from the upper surface of the second dielectric layer 110 to the plane of reference for being parallel to 106 upper surface of the first dielectric layer
Together.It repeats no more.According to the present embodiment, the method that the first dielectric layer 106 with groove 108 is directly formed with mold 118 can
To replace form the first dielectric layer 106, removal part of first dielectric layer 106 and formation groove 108 in first embodiment three
A step (as shown in Figure 1 to Figure 2), and make the upper surface of the first dielectric layer 106 not higher than the first chip using mold 118
104 joint sheet 104a.In addition, can also be initially formed surface general planar first is situated between in the alternate embodiment of the present embodiment
Electric layer 106 recycles the mold 118 with protrusion 118a, carries out imprinting process to the first dielectric layer 106 to form groove
108。
Figure 23 is please referred to, Figure 23 is the flow chart of the second embodiment of the production method of semiconductor subassembly of the present invention, by upper
It states it is found that the production method of semiconductor subassembly of the present invention can comprise the following steps that
Step S40: a substrate is provided；
Step S42: a sacrificial layer is formed on substrate；
Step S44: multiple first chips are set on sacrificial layer；
Step S46: first dielectric layer with multiple grooves is formed, and the first dielectric layer surrounds the first chip；And
Step S48: forming the second dielectric layer in the trench, wherein the upper surface of the first dielectric layer and the second dielectric layer is upper
Surface is generally aligned in the same plane, wherein it is both above-mentioned be generally aligned in the same plane be meant that the first dielectric layer upper surface and the second dielectric
The distance of layer upper surface to the plane of reference for being parallel to the first dielectric layer upper surface is roughly the same.
Fig. 8 to Fig. 9 is please referred to, Fig. 8 to Fig. 9 is that the 3rd embodiment processing procedure of semiconductor device fabrication method of the present invention is illustrated
Figure, wherein 3rd embodiment further illustrates that the present invention applies in stacked package body (package on package, POP)
Processing procedure.Third embodiment of the invention can connect Fig. 5 of first embodiment, another to provide an envelope after having made encapsulating structure 120
Assembling structure 220, wherein encapsulating structure 220 includes the second chip 204 (having joint sheet 204a), encapsulating material 206, reassigns layer
212 and soldered ball 214.The method of the present embodiment includes that encapsulating structure 220 is arranged on encapsulating structure 120, that is, wherein
Second chip 204 is set on one the first chip 104, and is arranged between the first chip 104 and the second chip 204 multiple
Separating ball SP, wherein separating ball SP may include high molecular material, such as can use in general liquid crystal display panel as liquid
The interval insulant of brilliant clearance support.As shown in figure 8, can be prior to multiple partial sizes and coefficient of elasticity be arranged on the first chip 104
Not exactly the same separating ball SP, wherein separating ball SP can be via sprinkling (spray), slot coated (slit) or wire mark
(print) processing procedure and be arranged and be fixed on the first chip 104, that is, be fixed on the upper surface 120a of encapsulating structure 120, but be arranged
The mode of separating ball SP is not limited with above-mentioned.Later, as shown in figure 9, the setting of encapsulating structure 220 is fixed on encapsulating structure again
On 120, such as with soldered ball 214, conductive pad or convex block so that the second chip 204 in encapsulating structure 220 is electrically connected to encapsulation knot
The first chip 104 or certain soldered balls 114 in structure 120, to form stacked package body 300.
Referring to FIG. 10, Figure 10 is the first alternate embodiment of the 3rd embodiment of semiconductor device fabrication method of the present invention
Processing procedure schematic diagram.This alternate embodiment and being different in for 3rd embodiment first will be between different-grain diameter and coefficient of elasticity
The lower surface 220a lower surface of layer 212 (namely reassign) of encapsulating structure 220 is fixed on every ball SP, then by encapsulating structure
220 are fixed on encapsulating structure 120.
The third embodiment of the present invention and its alternate embodiment disclose include semiconductor subassembly stacked package body
Production method, use the separating ball SP with different-grain diameter and coefficient of elasticity as fid between different encapsulating structures,
By the elastic characteristic of separating ball SP and the design of a variety of partial sizes, the buffering of stress and thickness can be provided, warpage is reduced and asks
Topic.The side of one layer of glue material is inserted in a manner of (pasting) by coating (spreading) or paste compared between different encapsulating structures
The design of method, separating ball SP of the present invention separately provides the good advantage of thermal diffusivity.
Figure 11 to Figure 13 is please referred to, Figure 11 to Figure 13 is the fourth embodiment processing procedure of semiconductor device fabrication method of the present invention
Schematic diagram.The main difference of the present embodiment and first embodiment is the set-up mode of the first chip 104.As shown in figure 11, exist
It is to make the first chip 104 with joint sheet 104a court when production sacrificial layer 102 after on substrate 100 is intended to that the first chip 104 is arranged
Under mode be arranged on sacrificial layer 102, even if also joint sheet 104a is directly in contact with 102 surface of sacrificial layer, therefore encapsulate
Structure can be considered joint sheet (face down) downward.Then the first dielectric layer 106 is re-formed, the encirclement of the first dielectric layer 106 is covered
The first chip of lid 104.
Next referring to Figure 12, remove part of first dielectric layer 106, make its upper surface 106a generally with the first chip
104 upper surface flushes, and then similar to first embodiment, multiple grooves 108 is formed in the first dielectric layer 106, then at groove
The second dielectric layer 110 is formed in 108, and makes the upper surface 110a of the second dielectric layer 110 and the upper surface of the first dielectric layer 106
106a is generally aligned in the same plane, wherein both above-mentioned upper surface 106a for being meant that the first dielectric layer 106 being generally aligned in the same plane
At a distance from a plane of reference of the upper surface 110a to the upper surface 106a for being parallel to the first dielectric layer 106 of the second dielectric layer 110
It is roughly the same.It is detached from the first chip 104 from sacrificial layer 102 and substrate 100, exposes the engagement of each first chip 104
Pad 104a.In alternate embodiment, can also second embodiment as the aforementioned, utilize mold 118 to form the first dielectric layer 104 and ditch
Slot 108.
Figure 13 is please referred to, makes the first chip 104 from after sacrificial layer 102 and the disengaging of substrate 100, has in the first chip 104
The side of joint sheet 104a, which is formed, reassigns layer 112, and the conducting wire reassigned in layer 112 can be electrically connected to by joint sheet 104a
Circuit in first chip 104.Then, multiple soldered balls 114 are formed in reassignment 112 surface of layer, and multiple soldered balls 114 are electrically connected
To the first chip 104, then cutting processing procedure can be carried out along cutting line DL, to complete the production of encapsulating structure 120.The present embodiment
The method that the first chip 104 is arranged in different directions is also applicable in the other embodiment of the present invention or alternate embodiment, no
It repeats again.It is noted that be that joint sheet 104a is set in face of sacrificial layer 102 when due to the first chip 104 of setting, because
This present invention is to be detached from the first chip 104 from sacrificial layer 102, will just reassign layer 112 and is produced on exposed joint sheet
The surface 104a.It can be seen from the above, the process of the production method of the present embodiment semiconductor subassembly can refer to Figure 22, repeat no more.
Figure 14 to Figure 17 is please referred to, Figure 14 to Figure 17 is the 5th embodiment processing procedure of semiconductor device fabrication method of the present invention
Schematic diagram.Figure 14 and Figure 15 are please referred to, wherein Figure 14 is schematic top plan view, and the part section that Figure 15 is corresponding diagram 14 is illustrated
Figure.According to the present embodiment, first offer substrate 100, sacrificial layer 102 is then formed on the substrate 100, on sacrificial layer 102
Patterned resin layer 116 is formed, wherein resin layer 116 includes waffle-like pattern, has multiple accommodatings on sacrificial layer 102
Groove (cavity) 122.Then, as shown in figure 16, the first chip 104, such as each first chip are set in containing groove 122
104 are separately positioned in one of them of containing groove 122.The present embodiment is being become so that joint sheet 104a is arranged upward as an example
Change in embodiment, the first chip 104 can also be arranged in such a way that joint sheet 104a is directed downwardly.After setting up the first chip 104, in
Dielectric material (that is, material of the first dielectric layer 106) is inserted in containing groove 122.
Figure 17 is please referred to, the above-mentioned dielectric material outside containing groove 122 is then removed, is formed by the first dielectric layer 106
Upper surface 106a generally flushed with the upper surface 116a of resin layer 116, that is, make the upper surface of the first dielectric layer 106
The upper surface 116a of 106a and resin layer 116 is substantially located at same plane or coplanar, wherein both above-mentioned be located at same put down
The upper surface 116a of the upper surface 106a for being meant that the first dielectric layer 106 in face and resin layer 116 is to being parallel to the first dielectric
The distance of a plane of reference of 106 upper surface 106a of layer is roughly the same.Due to being provided with resin layer 116 in the first dielectric layer 106,
Therefore also can be considered has groove 108 in the first dielectric layer 106.Then, the present embodiment forms on the first dielectric layer 106 and divides again
With layer 112 and soldered ball 114, and it is detached from the first chip 104 from sacrificial layer 102 and substrate 100, wherein soldered ball 114 is through weight
Distribution Layer 112 is electrically connected to corresponding first chip 104, and the reassignment layer 112 of the present embodiment is in the first chip 104 from sacrificial
Domestic animal layer 102 is made before being detached from substrate 100.In alternate embodiment, when the joint sheet 104a of the first chip 104 is sacrificed
When layer 102 covers, the first chip 104 can also first be made to be detached from from sacrificial layer 102 and substrate 100, after exposing joint sheet 104a,
It makes again and reassigns layer 112.After having made reassignment layer 112 and soldered ball 114, cutting system can be carried out along cutting line DL
Journey obtains encapsulating structure 120.
Figure 24 is please referred to, Figure 24 is the flow chart of the 5th embodiment of the production method of semiconductor subassembly of the present invention.By upper
It states it is found that the production method for the semiconductor subassembly that the present invention the 5th is implemented can comprise the following steps that
Step S60: a substrate is provided；
Step S62: a sacrificial layer is formed on substrate；
Step S64: a resin layer is formed on sacrificial layer；
Step S66: multiple first chips are set on sacrificial layer；And
Step S68: forming first dielectric layer with multiple grooves, and the first dielectric layer surrounds the first chip, wherein the
The upper surface of one dielectric layer and the upper surface of resin layer are generally aligned in the same plane, wherein both above-mentioned be generally aligned in the same plane means
Refer to the first dielectric layer upper surface and resin layer upper surface to the upper surface for being parallel to the first dielectric layer a plane of reference away from
From roughly the same.
Figure 18 to Figure 20 is please referred to, Figure 18 to Figure 20 is the sixth embodiment processing procedure of semiconductor device fabrication method of the present invention
Schematic diagram, wherein Figure 18 is the processing procedure for connecting Figure 16 of the 5th embodiment.The present embodiment and the difference of the 5th embodiment are mainly
Resin layer 116 can be removed in processing procedure.Such as Figure 16 and Figure 18, according to the present embodiment, in the containing groove 122 of resin layer 116
After the first dielectric layer 106 of first chip 104 and filling is set, part of first dielectric layer 106 is removed, the first dielectric layer 106 is made
Upper surface and resin layer 116 upper surface it is substantially coplanar (being generally aligned in the same plane), wherein both above-mentioned coplanar or be located at
The upper surface of the conplane upper surface for being meant that the first dielectric layer 106 and resin layer 116 is to being parallel to the first dielectric layer
The distance of one plane of reference of 106 upper surface is roughly the same.Then, at least a part of resin layer 116 is removed, in the first dielectric
Groove 108 is formed in layer 106.This when embodiment be for resin layer 116 to be removed completely, but in other embodiments, can
Only remove part resin layer 116.
Then as shown in figure 19, in the way of Fig. 2 to Fig. 3 in similar first embodiment, second is formed in groove 108
Dielectric layer 110, and it is same to be located at the upper surface 106a of the upper surface 110a of the second dielectric layer 110 and the first dielectric layer 106
Plane, wherein both above-mentioned upper surface 106a and the second dielectric layer for being meant that the first dielectric layer 106 being generally aligned in the same plane
The distance of a plane of reference of 110 upper surface 110a to the upper surface 106a for being parallel to the first dielectric layer 106 is roughly the same.Institute's shape
At the second dielectric layer 110 top view it is as shown in figure 20, there is the waffle-like pattern of the resin layer 116 in similar Figure 14.
Then, production reassigns layer 112 and soldered ball 114, is detached from the first chip 104 from sacrificial layer 102 and substrate 100, then cut
Processing procedure is cut, the encapsulating structure of semiconductor subassembly is fabricated to, repeats no more.The stream of the production method of the semiconductor subassembly of the present embodiment
Journey can refer to Figure 23, repeat no more.
Figure 21 is please referred to, Figure 21 is that the alternate embodiment of the sixth embodiment of semiconductor device fabrication method of the present invention is overlooked
Schematic diagram.Being different in for this alternate embodiment and sixth embodiment, can only remove part resin layer 116 and leave another portion
The resin layer 116 of part inserts the second dielectric layer 110 in the groove 108 for removing resin layer 116 later.In other words, first is situated between
The second dielectric layer 110 is provided in the wherein some of the groove 108 of electric layer 106, and the groove 108 of the first dielectric layer 106
Wherein resin layer 116 is provided in another part.Therefore, in a top view, the first dielectric layer 106, the second dielectric layer 110 and tree
Rouge layer 116 can exist simultaneously.When this three kinds of material layers respectively include different materials, such as it is respectively provided with different heat expansion coefficient
When, the pattern or setting position of the first dielectric layer 106, the second dielectric layer 110 with resin layer 116 can be designed according to product demand
It sets, thus improves the stress distribution of encapsulating structure, and then improve warpage issues.The production side of the semiconductor subassembly of the present embodiment
The process of method can refer to Figure 23, repeat no more.
The production method of semiconductor subassembly of the present invention can be applicable to chip and first make in the processing procedure of (chip-first), in master
Want setting groove and trench fill material (the second dielectric layer or resin above-mentioned in encapsulating material (the first dielectric layer above-mentioned)
Layer).Made semiconductor subassembly according to the present invention, due to may include discontinuous encapsulating material in chip surface, such as together
When include the first dielectric layer, groove, the second dielectric layer and resin layer both wherein, adjustable encapsulating structure dielectric material
Stress distribution, such as keep the stress in dielectric layer discontinuous.Furthermore the present invention passes through the dielectric layer of selection different materials,
The stress distribution of adjustable encapsulating structure.On the other hand, in the application of stacked package body, invention describes with different grains
Diameter, as the support between different chips or encapsulating structure, can provide the preferable advantage that radiates from the separating ball of coefficient of elasticity,
Stress problem can also be improved.Therefore, the production method for the semiconductor subassembly that the present invention is instructed can improve semiconductor subassembly
Warpage issues.
The above description is only an embodiment of the present invention, is not intended to restrict the invention, for those skilled in the art
For member, the invention may be variously modified and varied.All within the spirits and principles of the present invention, it is made it is any modification,
Equivalent replacement, improvement etc., should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of production method of semiconductor subassembly characterized by comprising
One substrate is provided；
A sacrificial layer is formed on the substrate；
Multiple first chips are set on the sacrificial layer；
One first dielectric layer is formed, and first dielectric layer surrounds the multiple first chip；
Multiple grooves are formed in first dielectric layer；And
One second dielectric layer is formed in the multiple groove；
Wherein the upper surface of first dielectric layer and the upper surface of second dielectric layer are generally aligned in the same plane.
2. the production method of semiconductor subassembly according to claim 1, which is characterized in that further include:
It forms a reassignment layer and is electrically connected to the multiple first chip；And
It is detached from the multiple first chip from the sacrificial layer.
3. the production method of the semiconductor subassembly according to claim 2, which is characterized in that form reassignment layer electrical connection
It to the step of the multiple first chip is carried out before the step of being detached from the multiple first chip from the sacrificial layer.
4. the production method of semiconductor subassembly according to claim 2, which is characterized in that form the reassignment layer and be electrically connected to
The step of the multiple first chip, was just carried out after the step of being detached from the multiple first chip from the sacrificial layer.
5. the production method of semiconductor subassembly according to claim 1, which is characterized in that first dielectric layer has one first
Highly, which has one second height, wherein second height to the ratio range of first height be 0.5 to
1.5。
6. the production method of semiconductor subassembly according to claim 1, which is characterized in that the thermal expansion system of first dielectric layer
Number is different from the thermal expansion coefficient of second dielectric layer.
7. the production method of semiconductor subassembly according to claim 1, which is characterized in that further include in the multiple first core
One second chip is set in one of them of piece, and is set between one of them of second chip and the multiple first chip
It is equipped with multiple separating balls.
8. a kind of production method of semiconductor subassembly characterized by comprising
One substrate is provided；
A sacrificial layer is formed on the substrate；
A resin layer is formed on the sacrificial layer；
Multiple first chips are set on the sacrificial layer；And
One first dielectric layer with multiple grooves is formed, and first dielectric layer surrounds the multiple first chip；
Wherein the upper surface of first dielectric layer is generally aligned in the same plane with the upper surface of the resin layer.
9. a kind of production method of semiconductor subassembly characterized by comprising
One substrate is provided；
A sacrificial layer is formed on the substrate；
Multiple first chips are set on the sacrificial layer；
One first dielectric layer with multiple grooves is formed, and first dielectric layer surrounds the multiple first chip；And
One second dielectric layer is formed at least one of the multiple groove；
Wherein the upper surface of first dielectric layer and the upper surface of second dielectric layer are generally aligned in the same plane.
10. the production method of semiconductor subassembly according to claim 9, which is characterized in that being formed has multiple grooves
The step of first dielectric layer, is formed using a mold.
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| US16/211,194 US11127604B2 (en) | 2018-01-05 | 2018-12-05 | Manufacturing method of semiconductor device |
| US17/402,595 US11721560B2 (en) | 2018-01-05 | 2021-08-15 | Manufacturing method of semiconductor device |
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| US201862613777P | 2018-01-05 | 2018-01-05 | |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111081654A (en) * | 2019-11-25 | 2020-04-28 | 上海先方半导体有限公司 | Packaging method of wafer packaging structure and wafer packaging structure |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020096789A1 (en) * | 2001-01-23 | 2002-07-25 | Bolken Todd O. | Semiconductor assembly encapsulation mold |
| US20140217597A1 (en) * | 2013-02-05 | 2014-08-07 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stress Relieving Vias for Improved Fan-Out WLCSP Package |
| US20150014856A1 (en) * | 2013-07-15 | 2015-01-15 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
| CN105355569A (en) * | 2015-11-05 | 2016-02-24 | 南通富士通微电子股份有限公司 | Packaging method |
| CN107301956A (en) * | 2016-08-29 | 2017-10-27 | 上海兆芯集成电路有限公司 | Chip Packaging Process |
| CN107301983A (en) * | 2017-08-02 | 2017-10-27 | 中芯长电半导体（江阴）有限公司 | Fan-out package structure and preparation method thereof |
-
2018
- 2018-03-19 CN CN201810223925.0A patent/CN110010505A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020096789A1 (en) * | 2001-01-23 | 2002-07-25 | Bolken Todd O. | Semiconductor assembly encapsulation mold |
| US20140217597A1 (en) * | 2013-02-05 | 2014-08-07 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Stress Relieving Vias for Improved Fan-Out WLCSP Package |
| US20150014856A1 (en) * | 2013-07-15 | 2015-01-15 | Invensas Corporation | Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation |
| CN105355569A (en) * | 2015-11-05 | 2016-02-24 | 南通富士通微电子股份有限公司 | Packaging method |
| CN107301956A (en) * | 2016-08-29 | 2017-10-27 | 上海兆芯集成电路有限公司 | Chip Packaging Process |
| CN107301983A (en) * | 2017-08-02 | 2017-10-27 | 中芯长电半导体（江阴）有限公司 | Fan-out package structure and preparation method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111081654A (en) * | 2019-11-25 | 2020-04-28 | 上海先方半导体有限公司 | Packaging method of wafer packaging structure and wafer packaging structure |
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