CN110010170B - Operation method of storage device and storage system thereof - Google Patents
Operation method of storage device and storage system thereof Download PDFInfo
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- CN110010170B CN110010170B CN201810010691.1A CN201810010691A CN110010170B CN 110010170 B CN110010170 B CN 110010170B CN 201810010691 A CN201810010691 A CN 201810010691A CN 110010170 B CN110010170 B CN 110010170B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/227—Timing of memory operations based on dummy memory elements or replica circuits
Abstract
The invention discloses an operation method of a storage device, which is executed by a processing circuit and comprises the following steps: executing a non-read instruction; and selecting a target memory cell from a plurality of memory cells of the memory device during execution of the non-read instruction, and executing the specific program on the target memory cell. The specific procedure includes: providing a virtual read instruction to a virtual read queue, wherein the virtual read instruction includes a physical location of a target memory cell; and arranging the virtual read operation on the target storage unit in the execution period according to the virtual read queue.
Description
Technical Field
The invention belongs to the technical field of data storage, and relates to an operation method of a storage device and a storage system thereof.
Background
To meet the demand for high-capacity, low-cost data storage, a storage device having a three-dimensional (3D) stacked structure is proposed. Compared with a memory device with a two-dimensional (2D) structure, the memory device with a 3D stacked structure has a higher probability of read errors and needs to perform a re-read (retry read) because the memory cells (memory cells) are arranged more closely and in a larger number, and the load effect of the word lines is significant. When performing a read again, the column decoder needs to adjust the original read threshold voltage setting to find the proper read threshold voltage setting in a manner similar to trial and error (trial and error). However, this approach often results in a delay in the read time, resulting in an unsmooth data read at the host.
Disclosure of Invention
The invention relates to an operation method of a memory device and a memory system thereof, which can restore the load effect (such as discrete capacitance of a word line) of a relevant word line to a stable state by executing dummy read (dummy read) operation on a memory cell. In this way, the column decoder will not fail to read due to the instability of the word line loading effect when driving the relevant word line in response to the host read command.
According to an embodiment of the present invention, there is provided a method of operating a memory device executed by a processing circuit, including the steps of: executing a non-read instruction; and selecting a target memory cell from a plurality of memory cells of the memory device during execution of the non-read instruction, and executing the specific program on the target memory cell. The specific procedure includes: providing a virtual read instruction to a virtual read queue, wherein the virtual read instruction includes a physical location of a target memory cell; a virtual read operation is scheduled to be performed on a target storage unit during execution according to the virtual read queue.
According to another embodiment of the present invention, there is provided a storage system including a storage device and a controller. The memory device includes a plurality of memory cells. The controller is coupled to the storage device and configured to: executing a non-read instruction; and selecting a target memory cell from the plurality of memory cells and executing a specific program on the target memory cell during execution of the non-read instruction. The specific procedure includes: providing a virtual read instruction to a virtual read queue, wherein the virtual read instruction includes a physical location of a target memory cell; and arranging the virtual read operation on the target storage unit in the execution period according to the virtual read queue.
In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:
drawings
FIG. 1 is a block diagram of a memory system according to an embodiment of the invention.
FIG. 2 is a schematic diagram illustrating a virtual read operation being interspersed with a storage device during execution of a non-read instruction.
FIG. 3 is a sequence diagram illustrating an example of the operation of the memory device.
FIG. 4 is a schematic diagram showing the variation of the potential of the discrete capacitor of the word line in the memory device with time.
FIG. 5 is a block diagram of a memory system according to an embodiment of the invention.
FIG. 6 is a flow chart showing a method of operating a memory device according to an embodiment of the invention.
[ notation ] to show
102. 500: a storage system;
104. 502: a host;
106: a controller;
108. 504, a step of: a storage device;
110: a processing unit;
112: a host interface;
114: a memory;
116: a storage device interface;
118: a conversion unit;
120: a virtual read queue;
CMDnr: a non-read instruction;
202: a non-read instruction queue;
CMDr: reading an instruction;
204: reading an instruction queue;
CMDdr: virtually reading an operation instruction;
120: a virtual read queue;
208: an execution queue;
210: a mapping table;
SI1～SIM: a sub-period;
DI1、DI2: an interval period;
t1, T2: time;
Δ st, Δ th: during the period;
506: a drive module;
508: reading an instruction queue;
510: a non-read instruction queue;
s602, S604, S606: and (5) carrying out the following steps.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to specific embodiments and the accompanying drawings.
The invention provides an operation method of a storage device and a storage system thereof. The method of operation of the memory device of the present invention may be performed by one or more processing circuits. The processing circuit may be implemented by an electronic circuit having an arithmetic processing function, such as a micro control unit (microcontroller), a microprocessor (microprocessor), a digital signal processor (digital signal processor), an Application Specific Integrated Circuit (ASIC), a digital logic circuit, and a Field Programmable Gate Array (FPGA). In one embodiment, the processing circuit is, for example, a controller of a storage device. In another embodiment, for a storage device without a controller, the processing circuit generally refers to a set of software/hardware elements disposed on a host and/or the storage device to perform the operation method of the storage device of the present invention.
FIG. 1 is a block diagram of a memory system 102 according to an embodiment of the invention. The storage system 102 includes a controller 106 and a storage device 108. A host 104, such as a personal computer, may send host instructions to the storage system 102 to access data in the storage devices 108. The controller 106 may schedule operations on the storage device 108 in response to host instructions. The storage 108 may be implemented by, for example, a non-volatile memory (NVM), a hard disk, an optical disk, a magnetic tape, or other storage devices. The memory device 108 includes a plurality of memory cells. Depending on the application, a memory cell may be represented as a block (block), a page (page), a sector (sector), or other unit of access.
The controller 106 is coupled to a storage device 108. According to the embodiment of fig. 1, the controller 106 includes a processing unit 110, a host interface 112, a memory 114, and a storage interface 116 coupled to each other. The processing unit 110 is, for example, a processor. The processing unit 110 may execute one or more programs to perform the methods of operation of the storage device of embodiments of the present invention through cooperation with the memory 114 and the respective interfaces 112, 116.
The host interface 112 may receive host commands (e.g., write commands, read commands, erase commands, etc.) from the host 104 and place them in a corresponding queue.
The processing unit 110 may also determine whether to perform a dummy read operation on the storage device 108 according to a read command in the read command queue of the host interface 112. If so, the processing unit 110 stores the virtual read instruction including the specific physical location in the virtual read queue 120.
According to an embodiment of the present invention, processing unit 110 may interleave the execution of one or more dummy read operations to target storage locations in storage 108 during the execution of the non-read instruction.
The dummy read operation may be implemented by any read operation, such as a read operation for a Single Level Cell (SLC) (e.g., applying a single read threshold voltage to a read target), or a read operation for a multi-level cell (MLC) (e.g., applying a plurality of different read threshold voltages to a read target).
The difference from the normal read operation is that the dummy read operation is only a read-like operation performed on the target memory cell, but the data of the memory cell is not interfaced to the memory of the controller through the memory device. In other words, the dummy read can be completed more quickly than a general read operation.
Through the execution of the dummy read operation, the relevant word line of the read target can be charged to make its loading effect (such as the discrete capacitance of the word line) in a stable state. Once the loading effect of the word line is stable, a column decoder (not shown) in the memory device 108 will not fail to read data through the default read threshold voltage setting due to the unstable loading condition of the word line when the word line is driven. The load effect variation of the word line will be described with reference to fig. 4.
On the other hand, since the purpose of the dummy read operation is not to perform data reading, the type of implementation of the dummy read operation and the type of data storage in the target storage unit do not necessarily correspond to each other. For example, whether the memory cells in the target memory cell are programmed as SLC or MLC, the dummy read operation may be implemented as a read operation of SLC, i.e., a single read threshold voltage is applied to the dummy read target. Similarly, a dummy read operation can also be implemented as a read operation of an MLC.
In addition to interspersing virtual read operations with storage 108 during execution of non-read instructions, in one embodiment, processing unit 110 may actively perform virtual read operations with a particular group or groups of storage units in storage 108 in the form of background operations when host 104 is not operating on storage system 102.
According to this embodiment, each or each group of memory cells (e.g., a block, a page of data, etc.) is assigned a corresponding counter to record the number of accesses, such as the number of reads, to the memory cells.
The processing unit 110 may classify the memory cells into a plurality of groups corresponding to different access frequency intervals according to the access frequency of the memory cells. The different access times intervals respectively represent a range of access times. By this classification, each group corresponds to a specific read hot and cold level.
For example, according to the number of accesses to the memory cells, the memory cells having the number of accesses falling within the first access number interval may be divided into the "always read" group G1, the memory cells having the number of accesses falling within the second access number interval may be divided into the "frequently read" group G2, the memory cells having the number of accesses falling within the third access number interval may be divided into the "occasionally read" group G3, and the memory cells having the number of accesses falling within the fourth access number interval may be divided into the "less read" group G4. Wherein the lower limit of the access times of the first access times interval is more than or equal to the upper limit of the access times of the second access times interval; the lower limit of the access times of the second access times interval is more than or equal to the upper limit of the access times of the third access times interval; the lower limit of the access times of the third access times interval is larger than or equal to the upper limit of the access times of the fourth access times interval. Therefore, the read hot and cold levels of the group are G1, G2, G3, G4 in order from "hot" to "cold".
Then, the processing unit 110 may record the sending frequency of the host command and perform the dummy read operation on one or more groups of the plurality of groups according to the sending frequency of the host command. The host command sending frequency refers to, for example, the frequency at which the host 104 sends a read command (or other host command) to the storage system 102.
Take the following table one as an example:
watch 1
| Host command transmission frequency | Group to perform dummy read operation |
| Always send | All groups (G1-G4) |
| Constantly sending | G1、G2、G3 |
| Occasionally transmitting | G1、G2 |
| Less transmission | G1 |
| Hardly transmit | Is free of |
According to the example of table one, if the host 104 accesses the data to the storage system 108 frequently, the processing unit 110 performs a dummy read operation on all or most of the groups of the storage devices 108 through a background operation to ensure the correctness of the data read. Conversely, the processing unit 110 will perform dummy read operations only on groups that are relatively "hot" in their partial read hot and cold levels, even without performing dummy read operations.
FIG. 2 is a schematic diagram illustrating the interleaving of dummy read operations on the storage device 108 during execution of a non-read instruction. As shown in FIG. 2, the host interface 112 includes a CMD for receiving non-read commandsnr Non-read command queue 202 and receive read command CMDrThe read instruction queue 204. Non-read command CMDnrBroadly refers to any memory operation instruction that is not indicative of performing a read operation, such as a write instruction, an erase instruction, a modify (trim) instruction, and so forth.
The translation unit 118 includes an image table 210 that maps host commands (e.g., non-read commands CMD)nrAnd a read command CMDr) To physical locations in the storage 108. Translation unit 118 may also translate the host instructions into one or more operations to be performed on storage device 108. For example, the translation unit 118 may schedule write operations to be performed to the storage device 108 in a plurality of sub-periods in response to a write command from the host 104. The order of execution of the different operations is implemented by the execution queue 208 in the storage interface 116. As shown in FIG. 2, the first and third execution units in the execution queue 208 are for a non-read instruction CMDnrFor a non-read operation, the second execution unit of the execution queue 208 is for a virtual read command CMDdrThe dummy read operation of (2).
According to the embodiment of FIG. 2, the processing unit 110 is executing a non-read command CMDnrDuring execution, the read command CMD in the read command queue 204 can be executedrA check is made to determine whether a corresponding dummy read operation needs to be performed on storage device 108.
In one embodiment, the processing unit 110 is executing a non-read command CMDnrOnce the read instruction queue is checked204 has a read command CMD stored thereinrArrange for the read command CMD to correspond torThe dummy read operation of (2). According to this embodiment, a read command CMDrThe logical position of the virtual read operation command CMD is first converted into a corresponding physical positiondrInto the virtual read queue 120. Next, the processing unit 110 inserts instructions in the virtual read queue 120 into the execution queue 208 to perform a virtual read operation on a specific physical location of the storage device 108 while the storage device 108 is idle.
In this manner, the controller 102 is subsequently executing a CMD for the read commandrIn the read operation (actual data to be read), since the dummy read operation is performed on the corresponding memory cell to be read first, the load effect of the associated word line is in a stable state, and the column decoder (not shown) in the memory device 108 will not fail to set the default read threshold voltage due to the unstable load effect of the word line.
In another embodiment, the processing unit 110 is executing a non-read command CMDnrDuring execution, the read command CMD in the read command queue 204 is checkedrWhether a specific condition is met or not, and if the specific condition is met, adding a corresponding virtual read operation command CMD to the virtual read queue 120drTo interleave execution of corresponding virtual read operations in the execution queue 208.
Further, the processing unit 110 can execute a non-read command CMDnrDuring execution, the read command CMD in the read command queue 204 is checkedr. This checking procedure includes, for example: obtaining the corresponding read command CMDrThe last access time of the memory cell to be read; obtaining the current time for executing the checking program; calculating a difference between the last access time and the current time; and selecting the memory cell to be read as an execution object of the virtual read operation, namely a target memory cell, in response to determining that the difference value exceeds a compatible value, otherwise the memory cell to be read is not selected as the target memory cell.
This is because once a word line is accessed, the stable state of its discrete capacitor can usually be maintained for about several minutes, and if the word line is driven by the column driver during this period, the accuracy of reading with the default read threshold voltage setting can still be ensured. Therefore, if the processing unit 110 detects that the interval between the last access time for reading the memory cell and the current time is within a compatible value (e.g., 3 minutes), it is determined that the dummy read operation is not required to be performed on the memory cell, so as to reduce the number of times of performing the dummy read operation, thereby avoiding unnecessary read disturb (read disturb) on the memory cell.
In one embodiment, the virtual read queue 120 may be disposed in the storage device 108. According to this embodiment, the controller 106 may send a dummy read instruction to the storage device 108, where the dummy read instruction indicates a target storage unit of the storage device 108 that needs to perform the dummy read operation. If the memory device 108 receives the dummy read command from the controller 106 while in the idle state, the dummy read operation is performed on the target memory cell according to the dummy read command. Otherwise, if the storage device 108 does not receive the dummy read command, the idle state is continuously maintained.
FIG. 3 is a sequence diagram illustrating an example of the operation of the memory device 108. According to the embodiment of FIG. 3, the execution period of the non-read instruction includes a plurality of sub-periods SI separated from each other1～SIMWherein M is a positive integer greater than 1. In response to a non-read command from the host 104, the processing unit 110 may perform a plurality of non-read operations on the storage device 108, wherein the non-read operations are SI during the sub-period1～SIMAnd (4) performing. In the sub-period SI1～SIMIn the interval period between two adjacent ones, e.g. interval period DI1、DI2Processing unit 110 may arrange to perform a dummy read operation on the target storage unit.
As shown in FIG. 3, the conversion unit 118 may convert a non-read instruction into a plurality of non-read operation sub-instructions, and SI is performed during the sub-period1～SIMTo the storage device 108. The processing unit 110 may arrange the dummy read operation command in two non-consecutive sub-periods (e.g., the sub-period SI)1、SI2) In the above-mentioned manner,during a neutral period (e.g., interval period DI) during which a non-read operation is performed1、DI2) A dummy read operation is performed on the target storage unit.
FIG. 4 is a schematic diagram showing the variation of the potential of the discrete capacitor of the word line in the memory device with time. As mentioned above, the discrete capacitance of the word line affects the loading effect of the column decoder when driving the word line. Generally, if a word line of memory cells is not read for a long time, the discrete capacitance of the word line is in an unstable state due to charge dissipation, so that the column decoder needs to repeatedly adjust the magnitude of the default read threshold voltage to find an appropriate read threshold voltage setting to read data from the memory cells when driving the word line. This is particularly true for memory devices having 3D stacks or other closely packed structures, such as 3D NAND flash memory.
As shown in FIG. 4, during the period Δ st from T1 to T2, the discrete capacitor potential of the word line is charged to a stable state due to the previous read/dummy read operation. If the row decoder drives the word line within the period Δ st, for example, the period Δ th, the row decoder can correctly read data through the default reading threshold voltage. On the contrary, if the row decoder drives the word line outside the period Δ st, the row decoder may fail to read due to the instability of the word line discrete capacitance.
In one embodiment, the last accessed time of each storage unit may be recorded by a global timer, such as a Real Time Clock (RTC). When the processing unit 110 determines whether to perform the dummy read operation on a memory cell, the processing unit 110 first calculates whether a difference between a last access time of the memory cell and a current time is greater than a length (compatible value) of a period Δ th. If so, it indicates that the word line associated with the memory cell may be in an unstable state, and it is necessary to charge the memory cell back to a stable state by a dummy read operation before the memory cell is actually read. Otherwise, the dummy read operation is not selected to be performed on the memory cell, so as to save the number of times of performing the dummy read operation.
FIG. 5 is a block diagram of a memory system 500 according to another embodiment of the invention. In this embodiment, storage system 500 includes a host 502 and a storage device 504. The storage device 504 does not have its own controller 106 like the storage device 108, but is directly controlled by the driver module 506 provided in the host 502.
The driver module 506 may be implemented, for example, as a software element (e.g., program, file, instructions, data), a hardware element (e.g., logic circuit), or a combination of both. The driving module 506 includes a read command queue 508 and a non-read command queue 510, and may perform an operation method of the memory device according to an embodiment of the present invention. Since the operation of the driving module 506 is similar to that of the controller 106 in the previous embodiment, it is not described herein again.
FIG. 6 is a flow chart showing a method of operating a memory device according to an embodiment of the invention. The method of operation of the memory device may be implemented by a processing circuit, such as (but not limited to) the controller 106 of fig. 1 or the driver module 506 of fig. 5.
In step S602, the processing circuit executes a non-read instruction.
In step S604, the processing circuit selects a target memory cell from a plurality of memory cells of the memory device during execution of the non-read instruction. The way of selecting the target storage unit is, for example: (1) selecting a memory cell corresponding to the read instruction in the read instruction queue from a plurality of memory cells, the corresponding memory cell having a physical location converted from the logical location of the read instruction; or (2) selecting the memory cells that are more suitable for a specific condition, such as the memory cells with access time interval exceeding a compatible value (e.g., exceeding the period Δ th of fig. 4), from among the memory cells that satisfy the condition (1).
In step S606, the processing circuit executes a specific program on the target memory cell, wherein the specific program includes: providing a virtual read instruction to a virtual read queue, wherein the virtual read instruction includes a physical location of a target memory cell; and arranging the virtual read operation on the target storage unit in the execution period according to the virtual read queue.
In addition, the processing circuit may also perform a virtual execution operation on a group of one or more storage units in a background operation according to a host instruction transmission frequency.
In summary, the present invention provides an operating method of a memory device and a memory system thereof, which can restore the loading effect (e.g. discrete capacitance of a word line) of the relevant word line to a stable state by performing a dummy read operation on the memory cell. In this way, the column decoder will not fail to read due to the instability of the word line loading effect when driving the relevant word line in response to the host read command.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto. Those skilled in the art to which the invention pertains will readily appreciate that various modifications and adaptations can be made without departing from the spirit and scope of the invention. Therefore, the protection scope of the present invention is subject to the claims defined by the claims.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. A method of operating a memory device, performed by a processing circuit, the method comprising:
executing a non-read instruction; and
during an execution period of executing the non-read instruction, selecting a target memory cell from a plurality of memory cells of a memory device, and executing a specific program to the target memory cell, wherein the specific program comprises:
providing a virtual read command to a virtual read queue, wherein the virtual read command includes a physical location of the target memory cell; and
arranging a virtual read operation to the target memory cell during the execution period according to the virtual read queue;
wherein the virtual read operation is interspersed on the storage device during execution of the non-read instruction; or, actively executing virtual read operation on the target storage unit in a background operation mode;
the execution period includes a plurality of sub-periods, and the interspersing execution of the virtual read operation on the storage device during execution of the non-read instruction includes: in response to the non-read command, performing a plurality of non-read operations on the memory device, wherein the non-read operations are performed during the sub-periods: and performing the dummy read operation on the target memory cell during an interval between adjacent ones of the sub-periods;
the method for actively executing the virtual read operation on the target storage unit in the background operation mode comprises the following steps: recording the access times of the storage units; classifying the storage units into a plurality of groups corresponding to different access frequency intervals according to the access frequency of the storage units; recording a host command sending frequency; and executing the dummy read operation to one or more of the groups according to the host command sending frequency.
2. The method of operation of a storage device of claim 1, further comprising:
during the execution period, executing a check program for a read instruction in a read instruction queue, the check program comprising:
obtaining a last access time of a to-be-read storage unit corresponding to the read instruction in the storage units;
obtaining a current time for executing the checking program;
calculating a difference between the last access time and the current time; and
in response to determining that the difference exceeds a compatible value, the memory cell to be read is selected as the target memory cell.
3. A storage system, comprising:
a memory device comprising a plurality of memory cells; and
a processing circuit coupled to the memory device and configured to:
executing a non-read instruction; and
during an execution period of executing the non-read instruction, selecting a target memory cell from the memory cells, and executing a specific program to the target memory cell, wherein the specific program comprises:
providing a virtual read command to a virtual read queue, wherein the virtual read command includes a physical location of the target memory cell; and
arranging a virtual read operation to the target memory cell during the execution period according to the virtual read queue;
wherein the virtual read operation is interspersed on the storage device during execution of the non-read instruction; or, actively executing virtual read operation on the target storage unit in a background operation mode;
the execution period includes a plurality of sub-periods, and the interspersing execution of the virtual read operation on the storage device during execution of the non-read instruction includes: in response to the non-read command, performing a plurality of non-read operations on the memory device, wherein the non-read operations are performed during the sub-periods: and performing the dummy read operation on the target memory cell during an interval between adjacent ones of the sub-periods;
the method for actively executing the virtual read operation on the target storage unit in the background operation mode comprises the following steps: recording the access times of the storage units; classifying the storage units into a plurality of groups corresponding to different access frequency intervals according to the access frequency of the storage units; recording a host command sending frequency; and executing the dummy read operation to one or more of the groups according to the host command sending frequency.
4. The memory system of claim 3, wherein the processing circuit is further configured to:
during the execution period, executing a check program for a read instruction in a read instruction queue, the check program comprising:
obtaining a last access time of a to-be-read storage unit corresponding to the read instruction in the storage units;
obtaining a current time for executing the checking program;
calculating a difference between the last access time and the current time; and
in response to determining that the difference exceeds a compatible value, the memory cell to be read is selected as the target memory cell.
5. The memory system of claim 3, wherein the non-read command is stored in a non-read command queue, and the non-read command queue is included in a host.
6. The storage system of claim 3, wherein the virtual read queue is included in the storage device.
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| TW473713B (en) * | 1999-08-09 | 2002-01-21 | Samsung Electronics Co Ltd | Semiconductor memory device and method for controlling memory cell array block thereof |
| TW200529238A (en) * | 2003-09-17 | 2005-09-01 | Sandisk Corp | Non-volatile memory and method with bit line compensation dependent on neighboring operating modes |
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