CN110007285B - FPGA-based ground penetrating radar distributed filtering method - Google Patents

FPGA-based ground penetrating radar distributed filtering method Download PDF

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CN110007285B
CN110007285B CN201910304370.7A CN201910304370A CN110007285B CN 110007285 B CN110007285 B CN 110007285B CN 201910304370 A CN201910304370 A CN 201910304370A CN 110007285 B CN110007285 B CN 110007285B
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input data
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word length
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CN110007285A (en
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白旭
李季蹊
张佳岩
高玉龙
姜建禹
安维乐
张延家
崔海涛
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Dalian Zhongrui Science & Technology Development Co ltd
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Harbin Institute of Technology
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/41—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00 using analysis of echo signal for target characterisation; Target signature; Target cross-section
    • G01S7/414—Discriminating targets with respect to background clutter

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Abstract

A ground penetrating radar distributed filtering method based on an FPGA belongs to the technical field of signal processing of ground penetrating radars. The invention solves the problem of low signal processing efficiency when the existing filtering method is realized in the FPGA. The invention uses distributed algorithm to realize digital filtering in FPGA, the distributed structure uses the character that binary data can be processed bit by bit, the same bit of input data is used as pre-addition result pre-stored before address searching, the partial product output by the searching table is shifted, the filtering result can be obtained after the shifting result is accumulated. The method can be applied to the technical field of signal processing of the ground penetrating radar.

Description

FPGA-based ground penetrating radar distributed filtering method
Technical Field
The invention belongs to the technical field of signal processing of ground penetrating radar, and particularly relates to a distributed filtering method of the ground penetrating radar.
Background
The ground penetrating radar is a nondestructive testing instrument for geophysical research of shallow earth surface. The detection personnel can know the underground situation by utilizing the characteristics of different electromagnetic properties of underground substances and collecting and processing high-speed and high-frequency ground penetrating radar echo data through the FPGA. In actual operation, as the ground penetrating radar is often used for performing tasks such as road layer detection, water depth and ice thickness detection and the like, clutter interference is introduced into underground metal and floating objects in water, and filtering of echoes is very important in detection construction. However, the existing filtering method occupies a lot of hardware resources and has large logic delay when being implemented in the FPGA, so that the signal processing efficiency is low and the speed is slow.
Disclosure of Invention
The invention aims to solve the problem of low signal processing efficiency when the existing filtering method is realized in an FPGA.
The technical scheme adopted by the invention for solving the technical problems is as follows: a ground penetrating radar distributed filtering method based on FPGA comprises the following steps:
acquiring relevant parameters and data word length of a filter for filtering by a ground penetrating radar; the filter related parameters comprise cut-off frequency, sampling frequency, filter order and filter coefficient; the data word length comprises the word length of impulse response and the word length of input data;
step two, combining and adding the filter coefficient and the binary address to obtain a partial product, and storing the obtained partial product and the corresponding binary address into a lookup table;
thirdly, simplifying the input data in a pre-addition mode to obtain simplified input data;
step four, carrying out bit-by-bit right shift operation on the simplified input data to splice search addresses, and obtaining a partial product in a search table according to the spliced search addresses;
and fifthly, performing shift operation on the partial product obtained in the fourth step, and accumulating the shift operation results to obtain an accumulation result, namely the ground penetrating radar distributed filtering result.
The invention has the beneficial effects that: the invention provides a ground penetrating radar distributed filtering method based on FPGA, which applies a distributed algorithm to realize digital filtering in FPGA, the distributed structure utilizes the characteristic that binary data can be processed bit by bit, the same bit of input data is taken as a pre-addition result pre-stored before address search, partial product output by a lookup table is subjected to shift operation, and the shift operation result is accumulated to obtain a filtering result, the invention replaces limited hardware multiplier resources with abundant memory resources, and replaces slow multiplication operation with rapid lookup operation and shift operation, the method of the invention can effectively suppress noise by performing signal processing on ground penetrating radar echo in FPGA, solves the problem of low efficiency of the existing method for signal processing, compared with the existing multiply-accumulate method, the method of the invention can reduce logic delay by 50%, the occupation of hardware resources is reduced by 30%, and the signal processing speed is effectively improved.
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FIG. 1 is a flow chart of a distributed filtering method of a ground penetrating radar based on an FPGA according to the invention;
FIG. 2 is a block diagram of ground penetrating radar filtering based on a distributed architecture;
FIG. 3 is a look-up table structure diagram for implementing a distributed algorithm using the method of the present invention;
in FIG. 3, X '[ 3] [0], X' [2] [0], X '[ 1] [0] and X' [0] [0] form a 4-bit binary address, 040 represents group 1 filter symmetry coefficient, 0f0 represents group 2 filter symmetry coefficient, 2a8 represents group 3 filter symmetry coefficient, and 428 represents group 4 filter symmetry coefficient.
FIG. 4 is a schematic diagram of a distributed bitwise operation implemented using the method of the present invention;
FIG. 5 is a diagram of an original signal;
FIG. 6 is a signal diagram after filtering an original signal;
FIG. 7 is a graph of the spectrum of an original signal;
fig. 8 is a spectrum diagram of an original signal after filtering.
Detailed Description
The first embodiment is as follows: as shown in fig. 1, the ground penetrating radar distributed filtering method based on FPGA according to this embodiment includes the following steps:
acquiring relevant parameters and data word length of a filter for filtering by a ground penetrating radar; the filter related parameters comprise cut-off frequency, sampling frequency, filter order and filter coefficient; the data word length comprises the word length of impulse response and the word length of input data;
step two, combining and adding the filter coefficient and the binary address to obtain a partial product, and storing the obtained partial product and the corresponding binary address into a lookup table;
thirdly, simplifying the input data in a pre-addition mode to obtain simplified input data;
step four, carrying out bit-by-bit right shift operation on the simplified input data to splice search addresses, and obtaining a partial product in a search table according to the spliced search addresses;
and fifthly, performing shift operation on the partial product obtained in the fourth step, and accumulating the shift operation results to obtain an accumulation result, namely the ground penetrating radar distributed filtering result.
The basic idea of this embodiment is to use a distributed architecture instead of a hardware filter multiply accumulate architecture to implement a convolution operation to complete the filtering. In digital signal processing, a bitwise operation method can be generally used to simplify operations, and a distributed structure utilizes this characteristic to implement filtering, and the overall structure is shown in fig. 2. Compared with a filtering method utilizing a multiply-accumulate structure, the distributed structure can effectively suppress noise and reduce occupied FPGA hardware resources and logic delay.
The second embodiment is as follows: the first difference between the present embodiment and the specific embodiment is: the filter order is 2N, the word length of the input data is T, and the word length of the filter coefficients is also T.
The third concrete implementation mode: the second embodiment is different from the first embodiment in that: the specific process of the second step is as follows:
for an FIR filter with order of 2N, N sets of symmetric filter coefficients of the FIR filter are respectively C0、C1、C2、…、CN-1Wherein: c0、C1、C2、…、CN-1Respectively represent a first group, a second group, a third group, … and an Nth group of symmetric filter coefficients;
the filter coefficient of the FIR filter with the order of 2N is C0、C1、…、CN-1、…、C2N-1I.e. 2N in total, since the 2N coefficients of the FIR filter are symmetrically equal end to end, i.e. C0＝C2N-1、C1＝C2N-2…, 2N coefficients can thus be written as N sets of symmetric filter coefficients, respectively: c0、C1、C2、…、CN-1；
The input address of the lookup table is an N-bit binary address { B }0、B1、B2、…、BN-1}，B0、B1、B2、…、BN-1The first bit, the second bit, the third bit, … and the Nth bit of the N-bit binary address respectively; then N-bit binary address B0、B1、B2、…、BN-1Corresponding partial product LUT (B)0,B1,…,BN-1) Comprises the following steps:
LUT(B0,B1,…,BN-1)＝B0×C0+B1×C1+…+BN-1×CN-1
will N bit binary address B0、B1、B2、…、BN-1And N-bit binary address B0、B1、B2、…、BN-1Corresponding partial product LUT (B)0,B1,…,BN-1) Storing the data into a lookup table;
the same principle is that: and obtaining partial products corresponding to the N-bit binary addresses, and storing the obtained partial products and the corresponding N-bit binary addresses into a lookup table.
For example: for a 3-bit binary address B0、B1、B2The partial product stored at 8 addresses of the lookup table can be obtained for a 4-bit binary address { B }0、B1、B2、B3Obtaining the partial products stored at 16 addresses of the lookup table, and so on, according with the binary address rule, solving the partial product of each binary address, and then combining the partial product with the corresponding binary addressAnd storing the partial products into a lookup table, wherein each partial product corresponds to a binary address one by one.
And calculating according to the filter coefficient to obtain a lookup table, wherein the address word length is N bits and corresponds to N data obtained by pre-adding in the third step. When N is 4, the lookup table structure is as shown in fig. 3, the first four columns of each row form the lookup table address, and the values in the last column are all partial products, which are obtained by combining and adding 4 sets of filter symmetric coefficients in the first row bracket.
The fourth concrete implementation mode: the third difference between the present embodiment and the specific embodiment is that: the specific process of the third step is as follows:
dividing the frequency of the main clock, obtaining 2N input data with the word length of T by controlling a T +2 frequency division clock, and inputting the obtained 2N input data with the word length of T into the shift register 1;
selecting data needing to be multiplied by the same filter coefficient from the shift register 1 according to the T +2 frequency division clock, adding the selected data in advance to obtain simplified input data, and storing the simplified input data into the shift register 2;
the simplified input data comprises N data with the word length of T + 1;
the expression of the data with the n +1 th word length of T +1 in the simplified input data is as follows:
x′[n]＝x[n]+x[2N-1-n](n＝0,1,2,...,N-1)
wherein: x' N is the N +1 th data in the input data after being reduced, x N is the N +1 th data in the input data with 2N word length T, x 2N-1-N is the 2N-N data in the input data with 2N word length T; x 2N-1-N is data symmetrical to x N.
For example: if x [ N ] is input for 4 data (i.e., N is 2), the following results are obtained by adding in advance: x '[ 0] + x [3], x' [1] + x [2], and if x [ N ] is 8 data (that is, N is 4), the sum is obtained: x '[ 0] + x [7], x' [1] + x [6], x '[ 2] + x [5], x' [3] + x [4], and so on.
The fifth concrete implementation mode: as shown in fig. 4, the fourth difference between the present embodiment and the specific embodiment is that: the specific process of the step four is as follows:
step four, splicing the lowest bits of each data in the simplified input data into an N-bit search address { x' [0]][0]、x′[1][0]、x′[2][0]、…、x′[N-1][0]}，{x′[0][0]、x′[1][0]、x′[2][0]、…、x′[N-1][0]Corresponding to the N-bit binary address B in step two0、B1、B2、…、BN-1}, wherein: x' [ N-1]][0]For the lowest bit of the Nth data in the reduced input data, x' 0][0]For the lowest bit of the 1 st data in the reduced input data, x' [1]][0]For the lowest order bit of the 2 nd data in the reduced input data, x' 2][0]The lowest bit of the 3 rd data in the input data after the simplification is carried out;
step two, inputting the N-bit search addresses spliced in the step four into the search table in the step two to output corresponding partial products;
LUT(x′[0][0],…,x′[N-1][0])＝C0·x′[0][0]+…+CN-1·x′[N-1][0]
step three, shifting each data in the input data after simplification to the right by one bit, and splicing the lowest bit of each data after right shifting into N-bit new search addresses { x '[ 0] [1], x' [1] [1], x '[ 2] [1], … and x' [ N-1] [1] }; inputting the spliced N-bit new search addresses { x '[ 0] [1], x' [1] [1], x '[ 2] [1], … and x' [ N-1] [1] } into the search table in the second step to output corresponding partial products LUT (x '[ 0] [1], … and x' [ N-1] [1 ]); wherein: x '[ 0] [1] represents the lowest bit of the 1 st data after right shifting, x' [1] [1] represents the lowest bit of the 2 nd data after right shifting, x '[ 2] [1] represents the lowest bit of the 3 rd data after right shifting, and x' [ N-1] [1] represents the lowest bit of the N th data after right shifting;
step four, repeating the process of the step four and the step three (continuously shifting each data in the input data after the simplification to the right by one bit) until all bits of each data are processed; obtaining the corresponding partial product of each spliced search address in a search table; the same bits of N pre-addition results (namely N data in the input data after simplification) with the word length of T +1 in the shift register 2 are spliced into T + 1N-bit search addresses, and the spliced T + 1N-bit search addresses are sequentially input into a search table to obtain corresponding partial products LUT (x '[ 0] [0], …, x' [ N-1] [0]), …, LUT (x '[ 0] [ T-1], …, x' [ N-1] [ T-1]), LUT (x '[ 0] [ T ], …, x' [ N-1] [ T ]).
The pre-addition result (i.e. the (n + 1) th data in the input data after the simplification) x 'n is written in the following form by bit so as to carry out the bitwise operation, wherein x' n < T > is the (T + 1) th bit of the (n + 1) th data of the pre-addition result:
Figure BDA0002029320160000051
n results (namely N data in the input data after being reduced) x' 0 of the pre-addition results]、x′[1]、x′[2]、…、x′[N-1]And filter coefficient C0、C1、C2、…、CN-1And correspondingly multiplying and accumulating to obtain a current moment filtering output result y:
Figure BDA0002029320160000052
wherein x' n]·CnCan be output by the table lookup in the fourth step and 2tMultiplication means:
Figure BDA0002029320160000061
the sixth specific implementation mode: the fifth embodiment is different from the fifth embodiment in that: the concrete process of the step five is as follows:
step five, the partial products obtained in the step four are shifted to the left according to the number of bits of the right shift in the step four (because each splicing address corresponds to one partial product, each partial product is shifted to the left according to the right shift number corresponding to the partial product in the step four), and then 2 is completedt×LUT(x′[0][t],…,x′[N-1][t]) The operation of (1); that is, for the partial product obtained by right shifting t bits in step four, the partial product obtained by right shifting t bits needs to be left shifted by t bitsThe partial product obtained by right shifting by t bits is compared with 2tMultiplying;
Figure BDA0002029320160000062
step five and two, each partial product is corresponding to 2tAnd accumulating the multiplied results to obtain an accumulated result, namely a ground penetrating radar distributed filtering result.
Partial product corresponding to N-bit search address spliced by shifting right 0 bit (namely N-bit search address spliced by lowest bit of each data in the input data after simplification) and 20Multiplication, the partial product corresponding to N-bit search address formed by right shift by 1-bit splicing and 21And (4) multiplying, and so on, until all the partial products obtained in the step four are correspondingly multiplied, accumulating the multiplication results, and obtaining an accumulation result, namely the ground penetrating radar distributed filtering result.
Based on a distributed structure, the low-delay and high-efficiency filtering of noise in radar echo by a filter is realized in the FPGA for further analysis:
fig. 5 shows a diagram of an original signal, fig. 6 shows a diagram of a filtered original signal, fig. 7 shows a diagram of a spectrum of an original signal, and fig. 8 shows a diagram of a spectrum of a filtered original signal.
The above-described calculation examples of the present invention are merely to explain the calculation model and the calculation flow of the present invention in detail, and are not intended to limit the embodiments of the present invention. It will be apparent to those skilled in the art that other variations and modifications of the present invention can be made based on the above description, and it is not intended to be exhaustive or to limit the invention to the precise form disclosed, and all such modifications and variations are possible and contemplated as falling within the scope of the invention.

Claims (2)

1. A ground penetrating radar distributed filtering method based on an FPGA is characterized by comprising the following steps:
acquiring relevant parameters and data word length of a filter for filtering by a ground penetrating radar; the filter related parameters comprise cut-off frequency, sampling frequency, filter order and filter coefficient; the data word length comprises the word length of impulse response and the word length of input data;
step two, combining and adding the filter coefficient and the binary address to obtain a partial product, and storing the obtained partial product and the corresponding binary address into a lookup table;
the specific process of the second step is as follows:
for an FIR filter with order of 2N, N sets of symmetric filter coefficients of the FIR filter are respectively C0、C1、C2、…、CN-1Wherein: c0、C1、C2、…、CN-1Respectively represent a first group, a second group, a third group, … and an Nth group of symmetric filter coefficients;
the input address of the lookup table is an N-bit binary address { B }0、B1、B2、…、BN-1}，B0、B1、B2、…、BN-1The first bit, the second bit, the third bit, … and the Nth bit of the N-bit binary address respectively; then N-bit binary address B0、B1、B2、…、BN-1Corresponding partial product LUT (B)0,B1,…,BN-1) Comprises the following steps:
LUT(B0,B1,…,BN-1)＝B0×C0+B1×C1+…+BN-1×CN-1
will N bit binary address B0、B1、B2、…、BN-1And N-bit binary address B0、B1、B2、…、BN-1Corresponding partial product LUT (B)0,B1,…,BN-1) Storing the data into a lookup table;
the same principle is that: obtaining partial products corresponding to the N-bit binary addresses, and storing the obtained partial products and the corresponding N-bit binary addresses into a lookup table;
thirdly, simplifying the input data in a pre-addition mode to obtain simplified input data;
the specific process of the third step is as follows:
dividing the frequency of the main clock, obtaining 2N input data with the word length of T by controlling a T +2 frequency division clock, and inputting the obtained 2N input data with the word length of T into the shift register 1;
selecting data needing to be multiplied by the same filter coefficient from the shift register 1 according to the T +2 frequency division clock, adding the selected data in advance to obtain simplified input data, and storing the simplified input data into the shift register 2;
the simplified input data comprises N data with the word length of T + 1;
the expression of the data with the n +1 th word length of T +1 in the simplified input data is as follows:
x′[n]＝x[n]+x[2N-1-n] (n＝0,1,2,...,N-1)
wherein: x' N is the N +1 th data in the input data after being reduced, x N is the N +1 th data in the input data with 2N word length T, x 2N-1-N is the 2N-N data in the input data with 2N word length T;
step four, carrying out bit-by-bit right shift operation on the simplified input data to splice search addresses, and obtaining a partial product in a search table according to the spliced search addresses;
the specific process of the step four is as follows:
step four, splicing the lowest bit of each data in the input data after simplification into N-bit searching addresses { x '[ 0] [0], x' [1] [0], x '[ 2] [0], … and x' [ N-1] [0] }, wherein: x '[ N-1] [0] is the lowest order bit of the Nth data in the reduced input data, x' [0] [0] is the lowest order bit of the 1 st data in the reduced input data, x '[ 1] [0] is the lowest order bit of the 2 nd data in the reduced input data, and x' [2] [0] is the lowest order bit of the 3 rd data in the reduced input data;
step two, inputting the N-bit search addresses spliced in the step four into the search table in the step two to output corresponding partial products;
step three, shifting each data in the input data after simplification to the right by one bit, and splicing the lowest bit of each data after right shifting into N-bit new search addresses { x '[ 0] [1], x' [1] [1], x '[ 2] [1], … and x' [ N-1] [1] }; inputting the spliced N-bit new search addresses { x '[ 0] [1], x' [1] [1], x '[ 2] [1], … and x' [ N-1] [1] } into the search table in the second step to output corresponding partial products LUT (x '[ 0] [1], … and x' [ N-1] [1 ]); wherein: x '[ 0] [1] represents the lowest bit of the 1 st data after right shifting, x' [1] [1] represents the lowest bit of the 2 nd data after right shifting, x '[ 2] [1] represents the lowest bit of the 3 rd data after right shifting, and x' [ N-1] [1] represents the lowest bit of the N th data after right shifting;
step four, repeating the process of the step four and the step three until all the bits of each datum are processed; obtaining the corresponding partial product of each spliced search address in a search table;
fifthly, shifting the partial product obtained in the fourth step, and accumulating the shifting operation result to obtain an accumulation result, namely a ground penetrating radar distributed filtering result;
the concrete process of the step five is as follows:
step five, the partial product obtained in the step four is left-shifted according to the number of bits of right shift in the step four, namely for the partial product obtained by right shift t bit in the step four, the partial product obtained by right shift t bit needs to be left-shifted by t bit, and the partial product obtained by right shift t bit and 2 are combinedtMultiplying;
step five and two, each partial product is corresponding to 2tAccumulating the multiplied results to obtain an accumulated result, namely a ground penetrating radar distributed filtering result;
the ground penetrating radar distributed filtering result y is as follows:
Figure FDA0002873364850000031
2. the FPGA-based ground penetrating radar distributed filtering method as recited in claim 1, wherein the filter order is 2N, and the word length of the input data is T.
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