CN109996077B - Logical image decompression method suitable for display panel detection - Google Patents
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Abstract
The invention discloses a logical image decompression method suitable for display panel detection, which comprises the steps of reading code stream data, receiving a data packet, analyzing the data packet containing a line template and line coordinate information, and acquiring the code stream information of the line template and the line coordinate; decoding the code stream information of the row template and the code stream information of the row coordinate to obtain original row template information and row coordinate information and generate a corresponding row template list and a corresponding row coordinate sequence list; and combining and sequencing the row templates according to the row coordinate sequence list, thereby realizing the reconstruction of the logic image. Aiming at the conditions of large error and easy distortion in the logic image reconstruction process in the prior art, the technical scheme of the invention adopts a mode of combining the line template and the line coordinate sequence mark, thereby facilitating the transmission and reconstruction of the logic image, and the logic image obtained by reconstruction has high precision and high reconstruction speed.
Description
Technical Field
The invention belongs to the field of display panel detection and logic image lossless compression, and particularly relates to a logic image decompression method suitable for display panel detection.
Background
In the detection process of the novel display panels such as LCD and OLED, a specific logic image needs to be displayed on the display, so that the human eye or an industrial camera can observe or shoot specific defects such as dead pixels and mura. In the prior art, the logic image generator is based on FPGA.
Specifically, there are currently two ways to generate logical images: and generating a logic image or directly transmitting a bitmap image according to an instruction sent by the upper computer and a specific rule. When a logic image is generated according to an instruction and a specific rule sent by an upper computer, the rule needs to be designed in advance, manual drawing is performed by using a matched vector diagram, the logic image can be drawn only according to the existing rule in the manual drawing process, and the drawing cannot be supported to be completed for the logic image without the corresponding existing rule. For the bitmap image which is directly transmitted, the bitmap image needs to be directly transmitted to the logic image generator through the upper computer. Due to the structural load, the bitmap image is transmitted in a direct transmission mode in the process, and is not processed at all.
However, when the first logical image generation method is used to generate a logical image, since the drawing rule must be stored in advance, and many new logical image types are often encountered in the actual logical image generation process, in this case, since the rule corresponding to the logical image is not stored in advance, the corresponding logical image cannot be acquired by using the logical image generation method. That is, a bitmap direct transmission mode is adopted, and the transmission mode generally occurs in the case that the existing rule cannot support the newly-appeared logic image type, or the logic image needing to be transmitted is too complex and the rule cannot be found manually. It should be noted that, the upper computer is used to directly transmit the bitmap image to the logic image generator, and the transmission and storage costs of bitmap during transmission are very high due to the requirements of the image signal generator on the data transmission speed and the storage space.
Further, for the received logic image compression packet (which may be an "instruction + rule" issued by the upper computer, or other forms of logic image compression packets), the receiving end needs to decompress the compression packet to restore the content of the original logic image, and finally apply the content to the detection of the display panel. However, in the process of decompressing the compressed packet, a content loss situation often occurs, so that the finally obtained logical image has a certain difference from the original image.
Disclosure of Invention
The above-identified deficiencies in the art or needs in the art are addressed, at least in part, by the present invention, which provides a method for logical image decompression suitable for display panel inspection. Aiming at the conditions of large error and easy distortion in the logic image reconstruction process in the prior art, the technical scheme of the invention adopts a mode of combining the line template and the line coordinate sequence mark, thereby facilitating the transmission and reconstruction of the logic image, and the logic image obtained by reconstruction has high precision and high reconstruction speed.
To achieve the above object, according to one aspect of the present invention, there is provided a logical image decompression method suitable for display panel detection, comprising
S1 reading code stream data and receiving data packets, analyzing the data packets containing row template and row coordinate information, and obtaining code stream information of the row template and the row coordinate;
s2, decoding the code stream information of the line template and the code stream information of the line coordinate to obtain the original line template information and the line coordinate information, and generating a corresponding line template list and a corresponding line coordinate sequence list;
s3, the row templates are combined and sorted according to the row coordinate sequence list, and therefore the reconstruction of the logic image is achieved.
As a preferred embodiment of the present invention, step 2 comprises,
s21, decoding the code stream information of the line template and the code stream information of the line coordinates to obtain the sub-template information and the line coordinate information of the original line template;
s22, identifying the information of the plurality of sub-templates, and dividing the sub-template information of the same row of templates into a group;
s23, combining the sub templates of the same line template into a corresponding line template, and acquiring an original line template according to the sub template information and generating a line template list;
s24 generates a row coordinate sequence list according to the row coordinate information.
As a preferable aspect of the present invention, step S3 includes,
s31 reading the serial number of any row template in the row coordinate sequence list and the corresponding row coordinate serial number;
s32, acquiring a corresponding line template from the line template list according to the serial number of the line template, and then adding the line template at the corresponding line position according to the corresponding line coordinate serial number;
and S33 traversing the row coordinate sequence list, completing the addition of all templates, and realizing the reconstruction of the logic image.
As an optimization of the technical solution of the present invention, the code stream information of the row template may be one or more columns of code streams.
As a preferred embodiment of the present invention, the code stream information of the row coordinate is a single column of code streams.
As a preferred embodiment of the present invention, the line template is a line of pixels with a certain number.
As a preferred embodiment of the present invention, the row coordinate is a row template serial number used by each row of pixel points in the logical image.
As a preferred embodiment of the present invention, the sub-template in step S21 is a sub-pixel template decomposed by R, G, B channels corresponding to the row template.
According to one aspect of the invention, there is provided a memory device having stored therein a plurality of instructions adapted to be loaded and executed by a processor:
s1 reading code stream data and receiving data packets, analyzing the data packets containing row template and row coordinate information, and obtaining code stream information of the row template and the row coordinate;
s2, decoding the code stream information of the line template and the code stream information of the line coordinate to obtain the original line template information and the line coordinate information, and generating a corresponding line template list and a corresponding line coordinate sequence list;
s3, the row templates are combined and sorted according to the row coordinate sequence list, and therefore the reconstruction of the logic image is achieved.
According to an aspect of the present invention, there is provided a terminal comprising a processor adapted to implement instructions; and a storage device adapted to store a plurality of instructions, the instructions adapted to be loaded and executed by the processor to:
s1 reading code stream data and receiving data packets, analyzing the data packets containing row template and row coordinate information, and obtaining code stream information of the row template and the row coordinate;
s2, decoding the code stream information of the line template and the code stream information of the line coordinate to obtain the original line template information and the line coordinate information, and generating a corresponding line template list and a corresponding line coordinate sequence list;
s3, the row templates are combined and sorted according to the row coordinate sequence list, and therefore the reconstruction of the logic image is achieved. Generally, compared with the prior art, the above technical solution conceived by the present invention has the following beneficial effects:
1) according to the technical scheme, the transmission mode of the line template and the line coordinate sequence is adopted, so that the method has good adaptability to the logic images with various resolutions, the reconstruction process of the logic images can be realized only by the line template and the line coordinate sequence after decompression and reconstruction, and the images with various bit depths can be accurately displayed.
2) The technical scheme of the invention greatly simplifies the design in the aspect of software, does not need self-research vector diagram drawing software, can directly use any third-party image drawing software to generate the required image, and can accurately reproduce the logic image only by acquiring the line template and the line coordinate sequence of the required image.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other. The present invention will be described in further detail with reference to specific embodiments.
In the embodiment of the technical scheme of the invention, a logic image compression and decompression method suitable for liquid crystal screen detection is provided.
Specifically, the compression of the logical image mainly comprises two parts, namely, line template matching classification firstly, and then line template and line coordinate sequence compression.
Specifically, the logic image in this embodiment is in a matrix form composed of a plurality of pixel points, the pixel point matrix may be expressed in a row or column form, and in this embodiment, the expression is preferably performed in a row form, that is, the pixel point matrix corresponding to the logic image is regarded as being composed of a plurality of rows of pixels, and one row of pixel points in the pixel point matrix is a row unit. Taking this as an example, the following further describes a specific technical solution of the present application.
First, a row template database is provided, which is empty before a specific row is processed, i.e. a row template list is initialized. Also initialized at the same time is an initial row coordinate sequence list and a match flag list. The line template list (i.e., the line template database) is used to store the line templates forming the logical image, and preferably, no line template exists in the line template list before the logical image is analyzed. In fact, in the case of a row unit, each row of the entire logical image corresponds to a row template, which has a certain repeatability. That is, a logical image is formed by a number of line templates combined by some form of arrangement. On this basis, the row coordinate sequence list in this embodiment is used to correspondingly record which pixel matrix rows of the pixel matrix correspond to each row template.
And then, numbering rows of the pixel point matrix of the logic image according to the sequence, and traversing all rows of the logic image. Specifically, it is preferable that the pixel point in the first line of the logical image is stored in a line template list (line template database) as a first line template, and is listed in the line coordinate series list as the first line template. And then, matching and comparing the pixel points of the second row with the first row, if the pixel points of the first row and the second row are completely consistent, indicating that the matching is successful, and adding the row sequence number of the second row into the row coordinate sequence list of the corresponding row template. And if the matching is unsuccessful, adding the current row serving as a new row template into the row template database, updating the row coordinate sequence list, generating a new row template serial number, and recording the row number of the corresponding logic image matrix.
As a specific preference in this implementation, a matching flag table is further involved, and the matching flag table is used to record the serial numbers of the pixel matrix rows that have been matched, that is, to distinguish the pixel matrix rows that have been marked from those that have not been marked, so as to avoid matching or classification errors.
It should be particularly noted that, in the row template matching in this embodiment, pixel values of corresponding positions of two rows of images are compared one by one, and if each pixel value is equal, it is determined that the two rows of images are matched; if any of the values are not equal, the judgment is not matched.
On the basis, the obtained row template and the row coordinate sequence list are further compressed, and the specific process is as follows.
Firstly, acquiring a complete row template list and a row coordinate sequence list of the whole logic image, and initializing a code stream. And then reading the line template in the line template list, decomposing the line template into R, G, B sub-pixel line templates of three channels, respectively carrying out run length coding on each sub-pixel line template, and outputting the obtained code stream data to the code stream.
For the row coordinate sequence list, since it adopts the way of numbering rows of the pixel matrix to mark the pixel rows corresponding to the same row template, for the convenience of compression, it is preferable to process it in the form of "delta encoding + run encoding" in this embodiment. Specifically, a row coordinate sequence is read from a row coordinate sequence list, then incremental coding is performed on the row coordinate sequence, then run-length coding is performed on the row coordinate sequence subjected to incremental coding, and code stream data obtained by the run-length coding is output to a code stream.
For the code stream containing the code stream data of the row template list and the row coordinate sequence list, in this embodiment, it is preferable to further encapsulate the code stream, that is, encapsulate the code stream into a specific data packet format, and then send the data packet format to the data bus for transmission.
Meanwhile, for the problem of decompression of logical images, the embodiment further provides a decompression method, which includes the following steps:
the first step is as follows: and reading code stream data from the data bus and analyzing the received data packet to obtain a line template code stream and a line sequence code stream. The line template code stream contains line template list information, and the line sequence code stream contains line coordinate sequence list information. After the data packet is analyzed, the encapsulated code stream data can be obtained. In some preferred embodiments, in consideration of the data transmission channel rate, the data code stream is grouped before being encapsulated to increase the transmission rate. Taking the encapsulation form in this embodiment as an example, if the code stream information of multiple line templates needs to be encapsulated in groups, it is preferable to first group the line templates, then correspondingly encode each line template, and finally encapsulate multiple sub-line templates possibly included in one line template into one data packet according to the grouping form of the line templates. It should be noted that, in the encoding process, the sub-line templates corresponding to each line template are numbered correspondingly to indicate the affiliation of the line template, so that the code stream data obtained by decoding can be quickly classified, and a plurality of sub-line templates belonging to the same line template can be identified.
The second step is that: and decoding the code stream data obtained by unpacking to obtain original coding information. To facilitate data transmission, the original information generally needs to be encoded to reduce the amount of information and then added to the code stream. Therefore, decoding of the code stream data obtained by unpacking is required. Taking the data compression method in this embodiment as an example, since the line template and the line coordinate sequence are both subjected to delta coding and/or run coding, respectively, the code stream data needs to be decoded according to a corresponding coding mode. In a particularly preferred embodiment, the original row template and row coordinate sequence are obtained.
The third step: and synthesizing according to the coding information to obtain a corresponding logic image line template. In this embodiment, before encoding, each line template is split into sub-pixel line templates of three RGB channels, then run-length encoding is performed on the sub-pixel line templates, and code stream data obtained by encoding the sub-pixel line templates is output to a code stream. Correspondingly, after the original information is obtained by decoding, the corresponding line template needs to be generated according to the original information. For example, after a line template is split into sub-pixel line templates of three channels of RGB, encoding, packaging and transmitting are performed, after sub-pixel line templates of three channels before encoding are obtained by corresponding decoding, the corresponding line template needs to be synthesized by using the sub-pixel line templates of the three channels, so as to obtain a line template list corresponding to the logical image.
The fourth step: and reconstructing the logic image according to the line template obtained by synthesis and by combining the information of the line coordinate sequence list. After the line templates (or the line template list) corresponding to the logical images are obtained, the entire logical image is composed of the line templates, and therefore the line templates need to be arranged and combined, so that the reconstruction of the logical images is realized. In the process of reconstruction, the arrangement and combination mode of the line template and the line template is the key for realizing the reconstruction of the logic image. In this embodiment, original information is obtained by decoding, so as to obtain a line template (or a line template list) corresponding to the logical image, and a line coordinate sequence list is also obtained along with the arrangement and combination manner of the line template sent by the data stream. And sequencing the row templates according to the row coordinate sequence list to realize the reconstruction of the logic image, wherein each row template can be used for multiple times.
In addition, the logical image compression/decoder in the embodiment has high data throughput rate, occupies less hardware resources, has good applicability, supports images with various resolutions and various display bit depths, and can completely replace the existing logical image generation logic. The design in the aspect of software can be greatly simplified, self-developed vector diagram drawing software is not needed, and any third-party image drawing software can be directly used for generating the required image.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A logical image decompression method suitable for display panel detection is characterized by comprising
S1 reading code stream data and receiving data packets, analyzing the data packets containing row template and row coordinate information, and obtaining code stream information of the row template and the row coordinate;
s2, decoding the code stream information of the line template and the code stream information of the line coordinate to obtain the original line template information and the line coordinate information, and generating a corresponding line template list and a corresponding line coordinate sequence list;
s3, the row templates are combined and sorted according to the row coordinate sequence list, and therefore the reconstruction of the logic image is achieved.
2. The logical image decompression method suitable for display panel detection according to claim 1, wherein the step S2 comprises,
s21, decoding the code stream information of the line template and the code stream information of the line coordinates to obtain the sub-template information and the line coordinate information of the original line template;
s22, identifying the information of the plurality of sub-templates, and dividing the sub-template information of the same row of templates into a group;
s23, combining the sub templates of the same line template into a corresponding line template, and acquiring an original line template according to the sub template information and generating a line template list;
s24 generates a row coordinate sequence list according to the row coordinate information.
3. The logical image decompression method suitable for display panel inspection according to claim 1 or 2, wherein the step S3 comprises,
s31 reading the serial number of any row template in the row coordinate sequence list and the corresponding row coordinate serial number;
s32, acquiring a corresponding line template from the line template list according to the serial number of the line template, and then adding the line template at the corresponding line position according to the corresponding line coordinate serial number;
and S33 traversing the row coordinate sequence list, completing the addition of all templates, and realizing the reconstruction of the logic image.
4. The method for decompressing logical image suitable for display panel detection according to claim 1 or 2, wherein the code stream information of the row template is one or more columns of code streams.
5. The method of claim 1 or 2, wherein the code stream information of the row coordinate is a single column code stream.
6. A method of logical image decompression suitable for display panel detection according to claim 1 or 2, wherein the line template is a determined number of pixels of a line.
7. The method of claim 1 or 2, wherein the row coordinate is a row template serial number used by each row of pixel points in the logical image.
8. The method of claim 2, wherein the sub-templates in step S21 are sub-pixel templates decomposed by R, G, B channels corresponding to the row template.
9. A memory device having stored therein a plurality of instructions adapted to be loaded and executed by a processor:
s1 reading code stream data and receiving data packets, analyzing the data packets containing row template and row coordinate information, and obtaining code stream information of the row template and the row coordinate;
s2, decoding the code stream information of the line template and the code stream information of the line coordinate to obtain the original line template information and the line coordinate information, and generating a corresponding line template list and a corresponding line coordinate sequence list;
s3, the row templates are combined and sorted according to the row coordinate sequence list, and therefore the reconstruction of the logic image is achieved.
10. A terminal comprising a processor adapted to implement instructions; and a storage device adapted to store a plurality of instructions, the instructions adapted to be loaded and executed by the processor to:
s1 reading code stream data and receiving data packets, analyzing the data packets containing row template and row coordinate information, and obtaining code stream information of the row template and the row coordinate;
s2, decoding the code stream information of the line template and the code stream information of the line coordinate to obtain the original line template information and the line coordinate information, and generating a corresponding line template list and a corresponding line coordinate sequence list;
s3, the row templates are combined and sorted according to the row coordinate sequence list, and therefore the reconstruction of the logic image is achieved.
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