CN109991787A - Array substrate and manufacturing method thereof - Google Patents
Array substrate and manufacturing method thereof Download PDFInfo
- Publication number
- CN109991787A CN109991787A CN201910197001.2A CN201910197001A CN109991787A CN 109991787 A CN109991787 A CN 109991787A CN 201910197001 A CN201910197001 A CN 201910197001A CN 109991787 A CN109991787 A CN 109991787A
- Authority
- CN
- China
- Prior art keywords
- passivation layer
- layer
- array substrate
- metal layer
- ethylmercurichlorendimides
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 63
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 24
- 238000002161 passivation Methods 0.000 claims abstract description 156
- 239000002184 metal Substances 0.000 claims abstract description 61
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- HTCXJNNIWILFQQ-UHFFFAOYSA-M emmi Chemical compound ClC1=C(Cl)C2(Cl)C3C(=O)N([Hg]CC)C(=O)C3C1(Cl)C2(Cl)Cl HTCXJNNIWILFQQ-UHFFFAOYSA-M 0.000 claims description 18
- 238000010438 heat treatment Methods 0.000 claims description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 239000012528 membrane Substances 0.000 abstract description 22
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 11
- 239000000853 adhesive Substances 0.000 abstract description 3
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 215
- 239000010408 film Substances 0.000 description 32
- 238000000151 deposition Methods 0.000 description 20
- 230000008021 deposition Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 9
- 238000000034 method Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- 238000004062 sedimentation Methods 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 2
- 241001074085 Scophthalmus aquosus Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920003023 plastic Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000001755 vocal effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Nonlinear Science (AREA)
- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Chemical & Material Sciences (AREA)
- Mathematical Physics (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Liquid Crystal (AREA)
Abstract
The application discloses an array substrate and a manufacturing method thereof. The manufacturing method of the array substrate comprises the following steps: forming a substrate; sequentially forming a first metal layer, a gate insulating layer, a semiconductor layer and a second metal layer on the substrate; forming a passivation layer on the second metal layer; forming a transparent electrode layer on the passivation layer; wherein the thickness of the passivation layer is between 2000 and 3000 angstroms. This application is through changing the membrane thickness of passivation layer, does the passivation layer membrane thickness between 2000 angstroms meters to 3000 angstroms meters, makes the film stress of passivation layer reduce, has increased the adhesive force between passivation layer and the second metal layer, has inhibited the production of undercut, has improved liquid crystal display panel's yield.
Description
Technical field
This application involves field of display technology more particularly to a kind of array substrate and preparation method thereof.
Background technique
It is formed with the development of science and technology with progress, flat-panel monitor due to having thin fuselage, power saving and the low hot spot of radiation
For the main product of display, it is widely applied.Flat-panel monitor includes Thin Film Transistor-LCD (Thin
Film Transistor-Liquid Crystal Display, TFT-LCD) and Organic Light Emitting Diode (Organic
Light-Emitting Diode, OLED) display etc..In liquid crystal display panel manufacturing process, second metal layer (M2, S/D
Metal when the passivation layer on) forms via hole by etching, it is easy to appear undercut, i.e. via bottom generates undercutting.
Undercutting may directly result in liquid crystal display panel display exception, also result in liquid crystal display panel and the problems such as dim spot occur, influence
The quality of liquid crystal display panel.
Summary of the invention
The application provides a kind of array substrate and preparation method thereof, inhibits the generation of undercutting.
This application discloses a kind of production methods of array substrate, comprising steps of
Form substrate；
The first metal layer, gate insulating layer, semiconductor layer and second metal layer are sequentially formed over the substrate；
Passivation layer is formed in the second metal layer；And
Transparent electrode layer is formed on the passivation layer；
Wherein, the passivation layer film thickness is in 2000 Ethylmercurichlorendimides between 3000 Ethylmercurichlorendimides.
Optionally, described in the step of forming passivation layer in second metal layer, the passivation layer film thickness is in 2000 Ethylmercurichlorendimides
To between 2300 Ethylmercurichlorendimides.
Optionally, described after the step of forming passivation layer in second metal layer, it further include that heat is carried out to the passivation layer
The step of processing.
Optionally, in described the step of being heat-treated to passivation layer, to the passivation layer heat treatment time at 50 seconds
To between 120 seconds.
Optionally, in described the step of being heat-treated to passivation layer, to the passivation layer heat treatment time at 50 seconds
To between 75 seconds.
Optionally, in the step of forming passivation layer in the second metal layer, comprising steps of
Passivation layer is formed with the rate of 7.5 Ethylmercurichlorendimide per second to 10 Ethylmercurichlorendimide per second in the second metal layer.
Optionally, in the step of forming passivation layer in the second metal layer, the passivation layer passes through plasmarized
Vapor deposition is learned to be formed.
Disclosed herein as well is a kind of production methods of array substrate, comprising steps of
Form substrate；
The first metal layer, gate insulating layer, semiconductor layer and second metal layer are sequentially formed over the substrate；
Passivation layer is formed with the rate of 7.5 Ethylmercurichlorendimide per second to 10 Ethylmercurichlorendimide per second in the second metal layer；
The passivation layer is heat-treated；And
Transparent electrode layer is formed on the passivation layer；
Wherein, the passivation layer film thickness is in 2000 Ethylmercurichlorendimides between 3000 Ethylmercurichlorendimides.
Disclosed herein as well is a kind of array substrate, the array substrate includes: substrate, be formed on the substrate
One metal layer, the gate insulating layer being formed on the first metal layer, the semiconductor layer being formed on the gate insulating layer,
The second metal layer being formed on the semiconductor layer, the passivation layer being formed in the second metal layer are formed in described blunt
Change the transparent electrode layer on layer；Wherein, the passivation layer film thickness is in 2000 Ethylmercurichlorendimides between 3000 Ethylmercurichlorendimides.
Optionally, the passivation layer film thickness is in 2000 Ethylmercurichlorendimides between 2300 Ethylmercurichlorendimides.
Passivation layer film thickness is arranged in 2000 Ethylmercurichlorendimides between 3000 Ethylmercurichlorendimides the application, reduces the membrane stress of passivation layer,
Increase the adhesive force between passivation layer and second metal layer, it is suppressed that the generation of undercutting improves the yield of liquid crystal display panel.
Detailed description of the invention
Included attached drawing is used to provide that a further understanding of the embodiments of the present application, and which constitute one of specification
Point, for illustrating presently filed embodiment, and with verbal description come together to illustrate the principle of the application.Under it should be evident that
Attached drawing in the description of face is only some embodiments of the present application, for those of ordinary skill in the art, is not paying wound
Under the premise of the property made is laborious, it is also possible to obtain other drawings based on these drawings.In the accompanying drawings:
Fig. 1 is a kind of schematic diagram of illustrative array substrate；
Fig. 2 is a-quadrant enlarged diagram in Fig. 1；
Fig. 3 is the enlarged diagram that a-quadrant forms transparent electrode layer in Fig. 1；
Fig. 4 is a kind of flow chart of the production method of array substrate of one embodiment of the application；
Fig. 5 is the passivation layer thickness of one embodiment of the application and the schematic diagram of membrane stress size；
Fig. 6 is the schematic diagram of the application passivation layer heat treatment time and stress relation；
Fig. 7 is a kind of flow chart of the production method of array substrate of another embodiment of the application；
Fig. 8 is a kind of schematic diagram of array substrate of another embodiment of the application.
Wherein, 100, array substrate；110, substrate；120, the first metal layer；130, gate insulating layer；140, semiconductor
Layer；150, second metal layer；160, passivation layer；170, transparent electrode layer.
Specific embodiment
It is to be appreciated that term used herein above, disclosed specific structure and function details, it is only for description
Specific embodiment is representative, but the application can be implemented by many alternative forms, be not construed as only
It is limited to the embodiments set forth herein.
In the description of the present application, term " first ", " second " are used for description purposes only, and it is opposite to should not be understood as instruction
Importance, or implicitly indicate the quantity of indicated technical characteristic.As a result, unless otherwise indicated, " first ", " are defined
Two " feature can explicitly or implicitly include one or more of the features；The meaning of " plurality " is two or two
More than.Term " includes " and its any deformation, mean and non-exclusive include, it is understood that there may be or addition is one or more that other are special
Sign, integer, step, operation, unit, component and/or combination thereof.
In addition, "center", " transverse direction ", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner",
The term of the orientation or positional relationship of the instructions such as "outside" is that orientation or relative positional relationship based on the figure describe, only
Be that the application simplifies description for ease of description, rather than indicate signified device or element must have a particular orientation,
It is constructed and operated in a specific orientation, therefore should not be understood as the limitation to the application.
Furthermore unless specifically defined or limited otherwise, term " installation ", " connected ", " connection " shall be understood in a broad sense, example
Such as it may be fixed connection or may be dismantle connection, or integral connection；It can be mechanical connection, be also possible to be electrically connected
It connects；It can be directly connected, it can also indirectly connected through an intermediary or the connection inside two elements.For ability
For the those of ordinary skill in domain, the concrete meaning of above-mentioned term in this application can be understood as the case may be.
As shown in Figure 1 to Figure 3, wherein Fig. 1 be a kind of array substrate 100 schematic diagram, the array substrate 100 include according to
The substrate 110 of secondary stacking, the first metal layer 120 (grid layer), gate insulating layer 130, semiconductor layer 140 (active layer and ohm
Contact layer), second metal layer 150 (Source and drain metal level), passivation layer 160 and transparent electrode layer 170；Wherein, transparent electrode layer 170
It is connect by via hole with Source and drain metal level；Fig. 2 is the enlarged diagram of a-quadrant in array substrate 100, it can be seen that passivation layer
160 in via etch, and the passivation layer 160 of via hole two sides is not that but can slope inwardly perpendicular to Source and drain metal level, this
Situation is known as the undercutting of passivation layer 160, the also referred to as undercut of passivation layer 160.Fig. 3 is that a-quadrant is formed in array substrate 100
The schematic diagram of transparent electrode layer 170 forms transparent electrode layer 170 since passivation layer 160 generates undercutting above passivation layer 160
When, the thickness for being deposited on the transparent electrode layer 170 at undercutting is excessively thin, and transparent electrode layer 170 is also resulted in when serious to be broken,
To influence the quality of liquid crystal display panel.
Below as attached drawing and optional embodiment are described further the application.
As shown in figure 4, the embodiment of the present application discloses a kind of production method of array substrate 100, comprising steps of
S1: substrate is formed；
S2: the first metal layer, gate insulating layer, semiconductor layer and second metal layer are sequentially formed over the substrate；
S3: passivation layer is formed in the second metal layer；
S4: transparent electrode layer is formed on the passivation layer；
Wherein, the passivation layer film thickness is in 2000 Ethylmercurichlorendimides between 3000 Ethylmercurichlorendimides.
When passivation layer 160 (Passivation layer, PV) etching forms via hole, because of the pass of 160 film thickness of passivation layer
The phenomenon that being, being easy to happen undercutting causes to form undercutting in via bottom, and the presence of undercutting is unfavorable for transparent electrode layer 170 and exists
Deposition on passivation layer 160；Transparent electrode layer 170 itself is relatively thin, it is possible to because the presence of undercutting causes transparent electrode layer 170
It is broken when deposition.It will have a direct impact on the normal display of liquid crystal display panel when undercut is serious, undercut slightly can also make
Occur the problems such as dim spot in liquid crystal display panel, influences the quality of liquid crystal display panel.The application changes the film thickness of passivation layer 160, will be blunt
Change 160 film thickness monitoring of layer in 2000 Ethylmercurichlorendimides to 160 film thickness of passivation layer between 3000 Ethylmercurichlorendimides, is reduced, reduces the thin of passivation layer 160
Membrane stress increases the adhesive force between passivation layer 160 and second metal layer 150, in this way in etch passivation layer 160, with
Two metal layers 150 fitting 160 part of passivation layer will not etch it is too fast, cause undercutting generate, so as to improve the brill of passivation layer 160
Lose phenomenon.It is positively correlated between 160 film thickness of passivation layer and membrane stress, specifically please refers to table 1.
Table 1: 160 thickness of passivation layer and the relationship of membrane stress, yields and diaphragm failure rate are obtained according to the data of table 1
Fig. 5, wherein Fig. 5 is 160 film thickness of passivation layer and membrane stress relational graph, and conclusion, other in guarantee as can be drawn from Figure 5
When condition is constant, 160 film thickness of passivation layer is thicker, and membrane stress is bigger.It, can be with if reducing the membrane stress of passivation layer 160
It is realized by reducing the thickness of passivation layer 160；160 film thickness of passivation layer is thicker, and membrane stress increases, and undercutting probability is caused to become
Greatly, and the time of formation passivation layer 160 is longer, production capacity can be made to reduce；And if passivation layer 160 is excessively thin, can make passivation layer 160
Declines make diaphragm failure.As can be seen from Table 1, when the thickness of passivation layer 160 is greater than 3000 Ethylmercurichlorendimide, i.e., stress is greater than
6.0Dyne/cm2, product yield can be decreased obviously, and when film thickness is less than 2300 Ethylmercurichlorendimide, yields is higher, so passivation
The film thickness of layer 160 should be certainly more preferable less than 2300 Ethylmercurichlorendimide effects less than 3000 Ethylmercurichlorendimides；In addition when film thickness is less than
When 2000 Ethylmercurichlorendimide, diaphragm failure rate can be relatively high, therefore by the plastics thickness control of passivation layer 160 more than 2000 Ethylmercurichlorendimides.
In conclusion 160 film thickness monitoring of passivation layer can not influenced passivation layer between 3000 Ethylmercurichlorendimides in 2000 Ethylmercurichlorendimides
While 160 effect itself, the membrane stress of passivation layer 160 is reduced, inhibits the generation of undercutting.Further, by passivation layer 160
Film thickness is arranged in 2000 Ethylmercurichlorendimides between 2300 Ethylmercurichlorendimides, and 160 film thickness of passivation layer is further reduced, film is further decreased and answers
Power keeps the improvement of undercutting more preferable.
In one embodiment, it after S3 step, further comprises the steps of:
S31: passivation layer 160 is heat-treated.
Inventor studies discovery by that the membrane stress of passivation layer 160 can be made to reduce the heat treatment of passivation layer 160, in this way
Film thickness is deposited in second metal layer 150 after 2000 Ethylmercurichlorendimides to the passivation layer 160 between 3000 Ethylmercurichlorendimides, then to passivation layer 160
It is heat-treated, further decreases the membrane stress of entire passivation layer 160.In addition passivation layer 160 is heat-treated and may be used also
To promote reliability, the stability of passivation layer 160, increase the compactness of passivation layer 160, reduces the water oxygen in array substrate 100
Gas keeps the performance of entire array substrate 100 more stable.
As shown in table 2 and Fig. 6, when the heat treatment time of passivation layer 160 increases, membrane stress can reduce, when to blunt
When the heat treatment time of change layer 160 is not up to 50 seconds, improvement of the size that the membrane stress of passivation layer 160 changes to undercutting situation
It is smaller, so the heat treatment time of passivation layer 160 is 50 seconds or more；But it is longer to the heat treatment time of passivation layer 160, it will
Cause the processing time of entire array substrate 100 to lengthen, reduces the production capacity of array substrate 100；When the heat treatment to passivation layer 160
When time is more than 120 seconds, the membrane stress improvement degree being heat-treated to passivation layer 160 is lower, and passivation layer can be made by being heat-treated
160 processing time extends, and the production capacity of passivation layer 160 and array substrate 100 is reduced, so the heat treatment of passivation layer 160
Time is between 50 seconds to 120 seconds.Further, since the heat treatment time of passivation layer 160 in Fig. 6 was at 50 seconds to 75 seconds
Curved portion it is steeper, illustrate that stress variation of this part is the most obvious, comprehensive improvement is best, so by passivation layer
160 heat treatment time controls between 50 seconds to 75 seconds, in this way while meeting reduction 160 membrane stress of passivation layer, also
The influence to 100 production capacity of array substrate can be reduced.
Table 2: the time and membrane stress relationship that passivation layer 160 is heat-treated
In the S3 step, comprising steps of
S32: passivation layer is formed with the rate of 7.5 Ethylmercurichlorendimide per second to 10 Ethylmercurichlorendimide per second in the second metal layer.
As shown in table 3, when the deposition velocity of film is faster, membrane stress is bigger, it is possible to by reducing passivation layer
160 deposition rate reduces the stress of passivation layer 160；Inventor is the study found that the deposition rate when passivation layer 160 is more than 10
When Ethylmercurichlorendimide is per second, stress is greater than 3.8Dyne/cm2, so that the probability that undercut occurs increases, so the deposition of passivation layer 160
Rate should be per second less than 10 Ethylmercurichlorendimides；In addition when deposition rate is per second less than 7.5 Ethylmercurichlorendimides, it will lead to the deposition of passivation layer 160
Time increases, because 160 film thickness of passivation layer is related with deposition rate and sedimentation time, i.e. 160 film thickness of passivation layer=deposition rate *
Sedimentation time, within a certain period of time, deposition rate are bigger, and 160 film thickness of passivation layer is bigger；So if deposition rate is too small, it is thin
Film thickness is certain, then sedimentation time can lengthen, the production capacity of array substrate 100 is caused to reduce.Secondly, if passivation layer 160
Deposition rate is too small, which to will lead to membrane stress, becomes compression stress from tensile stress, causes central film portion that can tilt, passivation layer 160
Reduce instead with the adsorption capacity of second metal layer 150, so the deposition rate of passivation layer 160 can be per second to 10 in 7.5 Ethylmercurichlorendimides
Between Ethylmercurichlorendimide is per second.And control is with compared with low rate deposit passivation layer, and it is with can making passivation layer deposition more uniform, passivation layer
Consistency is higher, so that the element characteristic of passivation layer is more preferable.
Table 3: 160 deposition rate of passivation layer and membrane stress relationship
In the method for above-mentioned 160 stress of reduction passivation layer, individually reduce 160 thickness of passivation layer, individually to passivation
Layer 160 carries out the pre-heat treatment, or individually improves 160 undercutting of passivation layer can reach compared with low rate deposit passivation layer 160
The purpose of phenomenon；The pre-heat treatment can also be carried out using first reduction 160 thickness of passivation layer, then to passivation layer 160, or with slower
The lesser passivation layer 160 of rate deposition thickness；It is, of course, also possible to first with the slower lesser passivation layer 160 of rate deposition thickness,
Passivation layer 160 is heat-treated again, in this way can improvement to passivation layer it is more preferable.
In the S3 step, passivation layer 160 passes through plasma activated chemical vapour deposition (Plasma Enhanced Chemical
Vapor Deposition, PECVD) method formed, relative to other deposition methods, the deposition rate of PECVD is very fast, sink
Long-pending film is more uniform.
As another embodiment of the application, as shown in fig. 7, disclosing a kind of production method of array substrate, including step
It is rapid:
S1: substrate is formed；
S2: the first metal layer, gate insulating layer, semiconductor layer and second metal layer are sequentially formed over the substrate；
S31: passivation layer is formed with the rate of 7.5 Ethylmercurichlorendimide per second to 10 Ethylmercurichlorendimide per second in the second metal layer；
S32: the passivation layer is heat-treated；
S4: transparent electrode layer is formed on the passivation layer.
Wherein, the passivation layer film thickness is in 2000 Ethylmercurichlorendimides between 3000 Ethylmercurichlorendimides.
As another embodiment of the application, as shown in figure 8, also disclosing a kind of array substrate 100, the array substrate
100 include: substrate 110, and the first metal layer 120 being formed on the substrate 110 is formed on the first metal layer 120
Gate insulating layer 130, the semiconductor layer 140 being formed on the gate insulating layer 130 is formed in the semiconductor layer 140
On second metal layer 150, the passivation layer 160 being formed in the second metal layer 150 is formed on the passivation layer 160
Transparent electrode layer 170；Wherein, 160 film thickness of passivation layer is in 2000 Ethylmercurichlorendimides between 3000 Ethylmercurichlorendimides.Further, described blunt
Change 160 film thickness of layer in 2000 Ethylmercurichlorendimides between 2300 Ethylmercurichlorendimides.
Wherein, above-mentioned substrate 110 is glass material；The first metal layer 120 is grid layer, and semiconductor layer 140 can be single
Layer structure, i.e. active layer, or double-layer structure, i.e. active layer and ohmic contact layer；Second metal layer 150 is source and drain metal
Layer.
It should be noted that the restriction for each step being related in this programme, in the premise for not influencing concrete scheme implementation
Under, it does not regard as being can be the step of making restriction to step sequencing, write on front what is first carried out, be also possible to
It executes, is possibly even performed simultaneously afterwards, as long as this programme can be implemented, all shall be regarded as belonging to the protection model of the application
It encloses.
The technical solution of the application can be widely applied to various display panels, such as twisted nematic (Twisted
Nematic, TN) display panel, plane conversion type (In-Plane Switching, IPS) display panel, vertical orientation type
(Vertical Alignment, VA) display panel, more quadrant vertical orientation type (Multi-Domain Vertical
Alignment, MVA) display panel, it is of course also possible to be other kinds of display panel, such as Organic Light Emitting Diode
(Organic Light-Emitting Diode, OLED) display panel, applicable above scheme.
The above content is combining specific optional embodiment to be further described to made by the application, cannot recognize
The specific implementation for determining the application is only limited to these instructions.For those of ordinary skill in the art to which this application belongs,
Without departing from the concept of this application, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the application
Protection scope.
Claims (10)
1. a kind of production method of array substrate, which is characterized in that comprising steps of
Form substrate；
The first metal layer, gate insulating layer, semiconductor layer and second metal layer are sequentially formed over the substrate；
Passivation layer is formed in the second metal layer；And
Transparent electrode layer is formed on the passivation layer；
Wherein, the passivation layer film thickness is in 2000 Ethylmercurichlorendimides between 3000 Ethylmercurichlorendimides.
2. a kind of production method of array substrate as described in claim 1, which is characterized in that the shape in second metal layer
In the step of passivation layer, the passivation layer film thickness is in 2000 Ethylmercurichlorendimides between 2300 Ethylmercurichlorendimides.
3. a kind of production method of array substrate as described in claim 1, which is characterized in that the shape in second metal layer
After the step of passivation layer, further include the steps that being heat-treated the passivation layer.
4. a kind of production method of array substrate as claimed in claim 3, which is characterized in that described to carry out hot place to passivation layer
In the step of reason, to the passivation layer heat treatment time between 50 seconds to 120 seconds.
5. a kind of production method of array substrate as claimed in claim 4, which is characterized in that described to carry out hot place to passivation layer
In the step of reason, to the passivation layer heat treatment time between 50 seconds to 75 seconds.
6. a kind of production method of array substrate as described in claim 1, which is characterized in that the shape in second metal layer
In the step of passivation layer, comprising steps of
Passivation layer is formed with the rate of 7.5 Ethylmercurichlorendimide per second to 10 Ethylmercurichlorendimide per second in the second metal layer.
7. a kind of production method of array substrate as described in claim 1, which is characterized in that the shape in the second metal layer
In the step of passivation layer, the passivation layer is formed by plasma activated chemical vapour deposition.
8. a kind of production method of array substrate, which is characterized in that comprising steps of
Form substrate；
The first metal layer, gate insulating layer, semiconductor layer and second metal layer are sequentially formed over the substrate；
Passivation layer is formed with the rate of 7.5 Ethylmercurichlorendimide per second to 10 Ethylmercurichlorendimide per second in the second metal layer；
The passivation layer is heat-treated；And
Transparent electrode layer is formed on the passivation layer；
Wherein, the passivation layer film thickness is in 2000 Ethylmercurichlorendimides between 3000 Ethylmercurichlorendimides.
9. a kind of array substrate characterized by comprising
Substrate；
The first metal layer is formed on the substrate；
Gate insulating layer is formed on the first metal layer；
Semiconductor layer is formed on the gate insulating layer；
Second metal layer is formed on the semiconductor layer；
Passivation layer is formed in the second metal layer；And
Transparent electrode layer is formed on the passivation layer；
Wherein, the passivation layer film thickness is between 2000 angstroms to 3000 angstroms.
10. a kind of array substrate as claimed in claim 9, which is characterized in that the passivation layer film thickness is arrived in 2000 Ethylmercurichlorendimides
Between 2300 Ethylmercurichlorendimides.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910197001.2A CN109991787B (en) | 2019-03-15 | 2019-03-15 | Array substrate and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910197001.2A CN109991787B (en) | 2019-03-15 | 2019-03-15 | Array substrate and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109991787A true CN109991787A (en) | 2019-07-09 |
| CN109991787B CN109991787B (en) | 2022-06-07 |
Family
ID=67129333
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910197001.2A Active CN109991787B (en) | 2019-03-15 | 2019-03-15 | Array substrate and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109991787B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112750764A (en) * | 2020-12-30 | 2021-05-04 | 滁州惠科光电科技有限公司 | Array substrate manufacturing method, array substrate and display panel |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58112365A (en) * | 1981-12-26 | 1983-07-04 | Fujitsu Ltd | Manufacture of thin film transistor |
| CN104934330A (en) * | 2015-05-08 | 2015-09-23 | 京东方科技集团股份有限公司 | Film transistor and preparation method thereof, array substrate and display panel |
| CN105070684A (en) * | 2015-07-17 | 2015-11-18 | 京东方科技集团股份有限公司 | Array substrate preparation method, array substrate and display device |
| CN107507850A (en) * | 2017-08-11 | 2017-12-22 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN108155196A (en) * | 2017-12-28 | 2018-06-12 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate and preparation method thereof |
| CN108598174A (en) * | 2018-05-09 | 2018-09-28 | 深圳市华星光电半导体显示技术有限公司 | The production method of array substrate |
-
2019
- 2019-03-15 CN CN201910197001.2A patent/CN109991787B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58112365A (en) * | 1981-12-26 | 1983-07-04 | Fujitsu Ltd | Manufacture of thin film transistor |
| CN104934330A (en) * | 2015-05-08 | 2015-09-23 | 京东方科技集团股份有限公司 | Film transistor and preparation method thereof, array substrate and display panel |
| CN105070684A (en) * | 2015-07-17 | 2015-11-18 | 京东方科技集团股份有限公司 | Array substrate preparation method, array substrate and display device |
| CN107507850A (en) * | 2017-08-11 | 2017-12-22 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN108155196A (en) * | 2017-12-28 | 2018-06-12 | 深圳市华星光电半导体显示技术有限公司 | A kind of array substrate and preparation method thereof |
| CN108598174A (en) * | 2018-05-09 | 2018-09-28 | 深圳市华星光电半导体显示技术有限公司 | The production method of array substrate |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112750764A (en) * | 2020-12-30 | 2021-05-04 | 滁州惠科光电科技有限公司 | Array substrate manufacturing method, array substrate and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109991787B (en) | 2022-06-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108231800B (en) | A kind of flexible display panels and preparation method thereof, display device | |
| CN110082977B (en) | TFT array substrate and display panel | |
| WO2020000609A1 (en) | Display panel and manufacturing method therefor | |
| US20180301806A1 (en) | Scanning antenna and method for manufacturing same | |
| US10748862B2 (en) | TFT substrate, scanning antenna comprising TFT substrate, and TFT substrate production method | |
| CN104752344A (en) | Thin film transistor array substrate and manufacturing method thereof | |
| CN103681488A (en) | Array substrate, manufacturing method thereof and display device | |
| US11024960B2 (en) | Scanned antenna and method of manufacturing scanned antenna | |
| CN110453198A (en) | Manufacturing method of indium tin oxide film, display panel and display device | |
| US20150171209A1 (en) | Thin film layer and manufacturing method thereof, substrate for display and liquid crystal display | |
| US20200083604A1 (en) | Tft substrate, scanning antenna comprising tft substrate, and tft substrate production method | |
| CN104538407A (en) | Display panel, manufacturing method thereof and display device | |
| US20220068976A1 (en) | Array substrate, manufacturing method therefor and display panel | |
| CN102593050B (en) | Method for manufacturing liquid crystal display panel array substrate | |
| CN103165680A (en) | Transparent film, manufacturing method thereof, base plate for displaying and display device | |
| CN104752345A (en) | Thin film transistor array substrate and manufacturing method thereof | |
| CN109991787A (en) | Array substrate and manufacturing method thereof | |
| CN105259712B (en) | Curved surface liquid crystal panel, the method for manufacturing it and curved surface liquid crystal display device | |
| CN109755260A (en) | Display panel, manufacturing method of display panel and display device | |
| CN101666949A (en) | IPS type TFT-LCD array substrate and manufacturing method thereof | |
| US11094719B2 (en) | Method of manufacturing display panel, display panel, and display device | |
| CN110379819A (en) | Array substrate, manufacturing method thereof and display panel | |
| US11342666B2 (en) | TFT substrate, scanning antenna provided with TFT substrate, and method for manufacturing TFT substrate | |
| CN103236402A (en) | Thin film transistor as well as production method thereof, array substrate and display device | |
| CN109950254A (en) | Array substrate, manufacturing method thereof and display panel |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |