CN109977540A - Integrated circuit standard cell library method for building up - Google Patents
Integrated circuit standard cell library method for building up Download PDFInfo
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- CN109977540A CN109977540A CN201910231277.8A CN201910231277A CN109977540A CN 109977540 A CN109977540 A CN 109977540A CN 201910231277 A CN201910231277 A CN 201910231277A CN 109977540 A CN109977540 A CN 109977540A
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- Prior art keywords
- reference line
- standard cell
- integrated circuit
- building
- cell library
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2115/00—Details relating to the type of the circuit
- G06F2115/06—Structured ASICs
Abstract
It include: by the standard unit picture regularization of minimum constructive height the invention discloses a kind of integrated circuit standard cell library method for building up；It determines that first kind transistor extends reference line, and extends reference line domain rule；It determines that Second Type transistor extends reference line, and extends reference line domain rule；The all levels that first kind transistor extends above baseline are extended into specified altitude assignment to first direction；The all levels that Second Type transistor extends above baseline are extended into specified altitude assignment to second direction；Determine the origin of standard block after modifying；Above-mentioned modification is carried out to units all in standard cell lib.It is customized that the present invention only needs the standard cell lib for developing a set of minimum constructive height to be able to achieve integrated circuit standard cell library height, largely reduces the development time of different height standard cell lib.
Description
Technical field
The present invention relates to integrated circuit fields, more particularly to a kind of integrated circuit standard cell library method for building up.
Background technique
In semiconductor integrated circuit manufacturing field, each technique has required a set of corresponding standard cell lib,
It needs to carry out AUTOMATIC LOGIC SYNTHESIS and laying out pattern wiring using the standard block in standard cell lib before carrying out flow.It is based on
The advantages of design method of standard cell lib is under some certain types of process node, and standard cell lib only needs to carry out one
After secondary design and good authentication, it can unceasingly be reused in design backward, greatly improve design efficiency, point
Design cost is spread out.
In existing method, the foundation of standard cell lib be all based on manpower work carry out circuit build and parameter modification, exploitation
Cell library is specified altitude assignment exploitation, and client determines the height of standard cell lib, standard block according to the demand of performance and power consumption
Library development teams are met customer need according to the corresponding IP of the high level of development, when the standard cell lib of each height of industry is developed
Between need 3 months, it is long there are the response time, the problem of low efficiency.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of standard cell lib development cycles that can be shortened different height, subtract
The integrated circuit standard cell library method for building up of the development time of few different height standard cell lib.
In order to solve the above technical problems, integrated circuit standard cell library method for building up provided by the invention, including following step
It is rapid:
1) by the standard unit picture regularization of minimum constructive height；
2) it determines that first kind transistor extends reference line, and extends reference line domain rule；
3) it determines that Second Type transistor extends reference line, and extends reference line domain rule；
4) all levels that first kind transistor extends above baseline are extended into specified altitude assignment to first direction；
5) all levels that Second Type transistor extends above baseline are extended into specified altitude assignment to second direction；
6) origin of standard block after modifying is determined；
7) above-mentioned modification is carried out to units all in standard cell lib.
2. integrated circuit standard cell library method for building up as described in claim 1, it is characterised in that: implementation steps 1)
When, according to minimum design rule in design rule file by the standard unit picture regularization of minimum constructive height.
Wherein, first kind transistor is PMOS.
It is further improved the integrated circuit standard cell library method for building up, implementation steps 4) when, the start bit of extension
Between top margin and contact hole (Contact) setting in first kind transistor active area, includes source region boundary but do not include
The boundary of contact hole (Contact).
It is further improved the integrated circuit standard cell library method for building up, implementation steps 5) when, the start bit of extension
Between top margin and contact hole (Contact) setting in Second Type transistor active area, includes source region boundary but do not include
The boundary of contact hole (Contact).
It is further improved the integrated circuit standard cell library method for building up, implementation steps 6) when, it will by eda software
The origin of modified standard block is grouped into home position.
It is further improved the integrated circuit standard cell library method for building up, implementation steps 7) when, it will be marked by script
All units are modified in quasi- cell library.
It is further improved the integrated circuit standard cell library method for building up, PMOS extends reference line domain rule such as
Under:
A) it is identical to extend distance of the reference line in each minimum unit of cell library (Cell) relative to origin by PMOS；
B) PMOS active area extends reference line with PMOS as the part of source/drain (Source/Drain) and overlaps；
C) PMOS active area is only used as the part of source/drain (Source/Drain) to extend reference line in the presence of friendship with PMOS
It is folded；
D) there is no overlapping for contact hole (Contact) and via hole (Via) and institute PMOS extension reference line；
E) polysilicon (POLY) only has grid (Gate) and PMOS extends reference line in the presence of overlapping.
Wherein, first direction is top.
Be further improved the integrated circuit standard cell library method for building up, step B) in overlapping refer to reference line position
Between the upper edge and lower edge of the part PMOS active area source/drain (Source/Drain).
Wherein, Second Type transistor is NMOS.
It is further improved the integrated circuit standard cell library method for building up, NMOS extends reference line domain rule such as
Under:
A) it is identical to extend distance of the reference line in each minimum unit of cell library (Cell) relative to origin by NMOS；
B) NMOS active area extends reference line with NMOS as the part of source/drain (Source/Drain) and overlaps；
C) NMOS active area is only used as the part of source/drain (Source/Drain) to extend reference line in the presence of friendship with NMOS
It is folded；
D) there is no overlapping for contact hole (Contact) and via hole (Via) and NMOS extension reference line；
E) polysilicon (POLY) only has grid (Gate) and NMOS extends reference line in the presence of overlapping.
Wherein, second direction is lower section.
It is further improved the integrated circuit standard cell library method for building up, overlapping in step b) refers to reference line position
Between the upper edge and lower edge of the part NMOS active area source/drain (Source/Drain).
The present invention only needs to develop the standard cell lib of a set of minimum constructive height, by advising the standard unit picture of minimum constructive height
Then change；Determine that pmos type transistor extends reference line；Determine that NMOS type transistor extends reference line；Determine standard block after modifying
Origin；The method that Run Script realizes customized height, so that batch modification, energy can be carried out by way of script by reaching
It realizes that integrated circuit standard cell library height is customized, largely reduces the development time of different height standard cell lib.
The standard cell lib development time of each height of industry needs 3 months, when the present invention develops the cell library of a set of new high degree
Between only need 7 days, and be more flexible.
Detailed description of the invention
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the schematic diagram one of the embodiment of the present invention.
Fig. 2 is the schematic diagram two of the embodiment of the present invention.
Fig. 3 is the schematic diagram three of the embodiment of the present invention.
Fig. 4 is the schematic diagram four of the embodiment of the present invention.
Fig. 5 is the schematic diagram five of the embodiment of the present invention.
Description of symbols
L1 is that PMOS extends reference line.
L2 is that NMOS extends reference line.
E2 is shown between the upper edge and lower edge of the part Source/Drain that reference line is located at PMOS/NMOS active area.
E3 shows the only Source/Drain of PMOS/NMOS active area and extends reference line in the presence of overlapping.
E45 shows contact hole and via hole and institute PMOS/NMOS extension reference line, and there is no overlapping.
E5 shows that polysilicon (POLY) only has grid (Gate) and PMOS extends reference line in the presence of overlapping.
H shows that PMOS/NMOS extends distance of the reference line in each minimum unit of cell library relative to origin.
Specific embodiment
Illustrate embodiments of the present invention below by way of particular specific embodiment, those skilled in the art can be by this explanation
Book disclosure of that is fully understood from other advantages and technical effect of the invention.The present invention can also be by different specific
Embodiment is embodied or practiced, and the various details in this specification can also be applied based on different viewpoints, is not having
Various modifications or alterations are carried out under total mentality of designing away from inventing.It should be noted that in the absence of conflict, implementing below
Feature in example and embodiment can be combined with each other.
One embodiment of integrated circuit standard cell library method for building up provided by the invention, the following steps are included:
1) refering to what is shown in Fig. 1, the present invention provides a kind of standard cell lib domain of 7T structure as a specific example to help
Assistant solves the present invention.According to minimum design rule in design rule file by the standard unit picture regularization of minimum constructive height.
2) with reference to shown in L1 in Fig. 1, determine that PMOS extends reference line, and extend reference line domain rule；
3) with reference to shown in L2 in Fig. 1, determine that NMOS extends reference line, and extend reference line domain rule
4) refering to what is shown in Fig. 2, the PMOS all levels for extending above baseline are extended to specified altitude assignment upwards；
Wherein, the initial position of extension be located at first kind transistor active area top margin and contact hole (Contact) it
Between, it include source region boundary but the boundary for not including contact hole (Contact).
5) refering to what is shown in Fig. 3, extending downward the NMOS all levels for extending above baseline to specified altitude assignment；
Wherein, the initial position of extension be located at Second Type transistor active area top margin and contact hole (Contact) it
Between, it include source region boundary but the boundary for not including contact hole (Contact).
6) refering to what is shown in Fig. 4, the origin of modified standard block is grouped into home position by eda software, determination is repaired
Change the origin of rear standard block；
7) units all in standard cell lib are modified by script.
Based on the above embodiment, it is as follows to extend reference line domain rule by PMOS:
A) with reference to shown in H in Fig. 5, PMOS extends reference line in each minimum unit of cell library (Cell) relative to origin
Distance it is identical.
B) with reference to shown in E2 in Fig. 5, PMOS active area extends base with PMOS as the part of source/drain (Source/Drain)
Directrix is overlapping；It is overlapping to refer to that reference line is located between the upper edge and lower edge of the part PMOS active area source/drain (Source/Drain).
C) with reference to shown in E3 in Fig. 5, PMOS active area is only used as the part of source/drain (Source/Drain) to prolong with PMOS
Reference line is stretched in the presence of overlapping.
D) with reference to shown in E4 in Fig. 5, contact hole (Contact) and via hole (Via) extend reference line with institute PMOS and are not present
It is overlapping.
E) with reference to shown in E5 in Fig. 5, polysilicon (POLY) only has grid (Gate) and PMOS extends reference line in the presence of overlapping.
Based on the above embodiment, it is as follows to extend reference line domain rule by NMOS:
A) with reference to shown in H in Fig. 5, NMOS extends reference line in each minimum unit of cell library (Cell) relative to origin
Distance it is identical.
B) with reference to shown in E2 in Fig. 5, NMOS active area extends base with NMOS as the part of source/drain (Source/Drain)
Directrix is overlapping；It is overlapping to refer to that reference line is located between the upper edge and lower edge of the part NMOS active area source/drain (Source/Drain).
C) with reference to shown in E3 in Fig. 5, NMOS active area is only used as the part of source/drain (Source/Drain) to prolong with NMOS
Reference line is stretched in the presence of overlapping.
D) with reference to shown in E4 in Fig. 5, contact hole (Contact) and via hole (Via) and NMOS extend reference line and friendship are not present
It is folded.
E) with reference to shown in E5 in Fig. 5, polysilicon (POLY) only has grid (Gate) and NMOS extends reference line in the presence of overlapping.
Above by specific embodiment and embodiment, invention is explained in detail, but these are not composition pair
Limitation of the invention.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and change
Into these also should be regarded as protection scope of the present invention.
Claims (14)
1. a kind of integrated circuit standard cell library method for building up, which comprises the following steps:
1) by the standard unit picture regularization of minimum constructive height；
2) it determines that first kind transistor extends reference line, and extends reference line domain rule；
3) it determines that Second Type transistor extends reference line, and extends reference line domain rule；
4) all levels that first kind transistor extends above baseline are extended into specified altitude assignment to first direction；
5) all levels that Second Type transistor extends above baseline are extended into specified altitude assignment to second direction；
6) origin of standard block after modifying is determined；
7) above-mentioned modification is carried out to units all in standard cell lib.
2. integrated circuit standard cell library method for building up as described in claim 1, it is characterised in that: implementation steps 1) when, root
According to minimum design rule in design rule file by the standard unit picture regularization of minimum constructive height.
3. integrated circuit standard cell library method for building up as described in claim 1, it is characterised in that: first kind transistor is
PMOS。
4. integrated circuit standard cell library method for building up as described in claim 1, it is characterised in that: implementation steps 4) when, prolong
The initial position stretched is located between the top margin of first kind transistor active area and contact hole (Contact), includes active area side
Boundary but the boundary for not including contact hole (Contact).
5. integrated circuit standard cell library method for building up as described in claim 1, it is characterised in that: implementation steps 5) when, prolong
The initial position stretched is located between the top margin of Second Type transistor active area and contact hole (Contact), includes active area side
Boundary but the boundary for not including contact hole (Contact).
6. integrated circuit standard cell library method for building up as described in claim 1, it is characterised in that: implementation steps 6) when, lead to
It crosses eda software and the origin of modified standard block is grouped into home position.
7. integrated circuit standard cell library method for building up as described in claim 1, it is characterised in that: implementation steps 7) when, lead to
It crosses script units all in standard cell lib are modified.
8. integrated circuit standard cell library method for building up as claimed in claim 3, it is characterised in that: PMOS extends reference line version
Rule map is as follows:
A) it is identical to extend distance of the reference line in each minimum unit of cell library (Cell) relative to origin by PMOS；
B) PMOS active area extends reference line with PMOS as the part of source/drain (Source/Drain) and overlaps；
C) PMOS active area is only used as the part of source/drain (Source/Drain) to extend reference line in the presence of overlapping with PMOS；
D) there is no overlapping for contact hole (Contact) and via hole (Via) and institute PMOS extension reference line；
E) polysilicon (POLY) only has grid (Gate) and PMOS extends reference line in the presence of overlapping.
9. integrated circuit standard cell library method for building up as claimed in claim 8, it is characterised in that: first direction is top.
10. integrated circuit standard cell library method for building up as claimed in claim 8, it is characterised in that: it is overlapping in step B)
Refer to that reference line is located between the upper edge and lower edge of the part PMOS active area source/drain (Source/Drain).
11. integrated circuit standard cell library method for building up as described in claim 1, it is characterised in that: Second Type transistor
It is NMOS.
12. integrated circuit standard cell library method for building up as claimed in claim 11, it is characterised in that: NMOS extends reference line
Domain rule is as follows:
A) it is identical to extend distance of the reference line in each minimum unit of cell library (Cell) relative to origin by NMOS；
B) NMOS active area extends reference line with NMOS as the part of source/drain (Source/Drain) and overlaps；
C) NMOS active area is only used as the part of source/drain (Source/Drain) to extend reference line in the presence of overlapping with NMOS；
D) there is no overlapping for contact hole (Contact) and via hole (Via) and NMOS extension reference line；
E) polysilicon (POLY) only has grid (Gate) and NMOS extends reference line in the presence of overlapping.
13. integrated circuit standard cell library method for building up as claimed in claim 11, it is characterised in that: under second direction is
Side.
14. integrated circuit standard cell library method for building up as claimed in claim 11, it is characterised in that: it is overlapping in step b)
Refer to that reference line is located between the upper edge and lower edge of the part NMOS active area source/drain (Source/Drain).
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910231277.8A CN109977540B (en) | 2019-03-26 | 2019-03-26 | Method for establishing standard cell library of integrated circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910231277.8A CN109977540B (en) | 2019-03-26 | 2019-03-26 | Method for establishing standard cell library of integrated circuit |
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| CN109977540B CN109977540B (en) | 2023-08-15 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110660792A (en) * | 2019-09-30 | 2020-01-07 | 上海华力微电子有限公司 | Method for generating filling pattern of FDSOI standard cell and layout method |
| CN112818625A (en) * | 2021-02-05 | 2021-05-18 | 上海华虹宏力半导体制造有限公司 | Layout and layout modification method |
| CN113221487A (en) * | 2021-04-27 | 2021-08-06 | 上海华虹宏力半导体制造有限公司 | Standard unit layout drawing method |
| CN113221487B (en) * | 2021-04-27 | 2024-04-23 | 上海华虹宏力半导体制造有限公司 | Standard unit layout stretching method |
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| CN103022032A (en) * | 2012-12-07 | 2013-04-03 | 中国科学院微电子研究所 | Domain design method and domain layout method of standard unit library and standard unit library |
| CN105868449A (en) * | 2016-03-24 | 2016-08-17 | 中国科学院微电子研究所 | Optimization method and system for standard unit library |
| CN106981484A (en) * | 2017-03-28 | 2017-07-25 | 上海理工大学 | The layout design method of standard cell lib area is reduced using local interlinkage |
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2019
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103022032A (en) * | 2012-12-07 | 2013-04-03 | 中国科学院微电子研究所 | Domain design method and domain layout method of standard unit library and standard unit library |
| CN105868449A (en) * | 2016-03-24 | 2016-08-17 | 中国科学院微电子研究所 | Optimization method and system for standard unit library |
| CN106981484A (en) * | 2017-03-28 | 2017-07-25 | 上海理工大学 | The layout design method of standard cell lib area is reduced using local interlinkage |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110660792A (en) * | 2019-09-30 | 2020-01-07 | 上海华力微电子有限公司 | Method for generating filling pattern of FDSOI standard cell and layout method |
| CN112818625A (en) * | 2021-02-05 | 2021-05-18 | 上海华虹宏力半导体制造有限公司 | Layout and layout modification method |
| CN112818625B (en) * | 2021-02-05 | 2024-03-15 | 上海华虹宏力半导体制造有限公司 | Layout and layout modification method |
| CN113221487A (en) * | 2021-04-27 | 2021-08-06 | 上海华虹宏力半导体制造有限公司 | Standard unit layout drawing method |
| CN113221487B (en) * | 2021-04-27 | 2024-04-23 | 上海华虹宏力半导体制造有限公司 | Standard unit layout stretching method |
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