CN109976442B - Slave clock information optimization method and device, electronic equipment and storage medium - Google Patents
Slave clock information optimization method and device, electronic equipment and storage medium Download PDFInfo
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Abstract
The invention provides a slave clock information optimization method, a slave clock information optimization device, electronic equipment and a storage medium, wherein the method comprises the following steps: step A, acquiring master clock information; b, processing the master clock information through a sliding mode controller to obtain first information; step C, processing the first information after the interference processing through a controlled object function to obtain second information; d, processing the second information subjected to the noise processing through a Kalman filter to obtain slave clock information; step E, judging whether the deviation of the master clock information and the slave clock information meets a preset condition or not; and F, when the deviation of the master clock information and the slave clock information does not meet the preset condition, inputting the deviation of the master clock information and the slave clock information into the sliding mode controller, and executing the steps B to E until the deviation of the master clock information and the slave clock information meets the preset condition, so that the target slave clock information is obtained. The invention reduces the deviation of the master clock and the slave clock and realizes more accurate master clock and slave clock synchronization.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a slave clock information optimization method and apparatus, an electronic device, and a storage medium.
Background
In 2008, the IEEE (Institute of Electrical and Electronics Engineers) protocol organization proposed IEEE1588V2 precision time transfer protocol, which can realize sub-microsecond precision master-slave clock synchronization and is the hottest time transfer protocol in the industry.
In the prior art, a method for realizing master-slave clock synchronization by adopting a 1588 protocol is that a message is quickly exchanged between a slave clock and a master clock to obtain a timestamp; and calculating the relative difference value of the values of the timestamps of the adjacent synchronization periods, taking the difference value as the drift value of the slave clock relative to the frequency of the master clock, and adjusting the slave clock according to the drift value so as to realize the frequency synchronization of the master clock and the slave clock.
The inventor finds that in the existing method for realizing master-slave clock synchronization by adopting a 1588 protocol, the stability of a clock crystal oscillator seriously influences the IEEE1588 clock synchronization precision. When the crystal oscillator is in a higher temperature environment, the stability of the crystal oscillator is greatly reduced, which is mainly indicated by larger frequency drift of the oscillation frequency of the clock crystal oscillator. Without timely correction of this frequency drift, the master-slave clock bias will become larger and larger as time goes on. Therefore, how to reduce the deviation of the master-slave clock and further realize the precise master-slave clock synchronization still remains to be solved urgently.
Disclosure of Invention
Embodiments of the present invention provide a method and an apparatus for optimizing slave clock information, an electronic device, and a storage medium, so as to reduce a master-slave clock bias and further achieve relatively precise master-slave clock synchronization. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present invention discloses a slave clock information optimization method, where the method includes:
step A, acquiring master clock information;
b, processing the master clock information through a sliding mode controller to obtain first information;
step C, carrying out interference processing on the first information, and processing the first information subjected to the interference processing through a controlled object function to obtain second information; the controlled object function is a function obtained by performing Laplace transform and discretization on a function expression of slave clock information corresponding to the master clock information;
step D, carrying out noise adding processing on the second information, and processing the second information subjected to the noise adding processing through a Kalman filter to obtain slave clock information;
step E, judging whether the deviation of the master clock information and the slave clock information meets a preset condition or not;
and F, when the deviation between the master clock information and the slave clock information does not meet the preset condition, inputting the deviation between the master clock information and the slave clock information into the sliding mode controller, and executing the steps B to E until the deviation between the master clock information and the slave clock information meets the preset condition, so as to obtain target slave clock information.
Optionally, the processing the master clock information by using a sliding mode controller to obtain first information includes:
inputting the main clock information into a sliding mode controller, and obtaining a first intermediate value through a first formula of the sliding mode controller;
obtaining a second intermediate value through a second formula of the sliding mode controller;
obtaining a third intermediate value according to the first intermediate value and the second intermediate value;
and inputting the third intermediate value into a third formula of the sliding mode controller, and obtaining first information through the third formula.
Optionally, the performing interference processing on the first information, and processing the first information after the interference processing through a controlled object function to obtain second information includes:
adding preset interference information to the first information to obtain the first information subjected to interference processing;
processing the first information subjected to interference processing through a controlled object function to obtain second information; wherein the controlled object function is represented as:
x(k)＝Ax(k-1)+B(u(k)+ω(k))
y(k)＝Cx(k)
wherein x (k) represents a state variable at the current time; x (k-1) represents a state variable at the last time; u (k) represents the first information; ω (k) represents process noise; a represents a system matrix; b represents an input matrix; representing an output matrix; y (k) represents the second information.
Optionally, the denoising processing on the second information and processing the second information after the denoising processing through a kalman filter to obtain slave clock information includes:
denoising the second information through a preset formula; the preset formula is expressed as:
yv(k)＝y(k)+v(k)
wherein, yv(k) Representing the second information after the noise adding processing; y (k) represents the second information; v (k) represents measurement noise;
and calculating the second information subjected to the noise adding treatment through a preset equation set of a Kalman filter to obtain slave clock information.
In a second aspect, an embodiment of the present invention discloses a slave clock information optimization apparatus, where the apparatus includes:
the master clock information acquisition module is used for acquiring master clock information;
the first information determining module is used for processing the master clock information through a sliding mode controller to obtain first information;
the second information determining module is used for carrying out interference processing on the first information and processing the first information subjected to the interference processing through a controlled object function to obtain second information; the controlled object function is a function obtained by performing Laplace transform and discretization on a function expression of slave clock information corresponding to the master clock information;
the slave clock information determining module is used for carrying out noise adding processing on the second information and processing the second information subjected to the noise adding processing through a Kalman filter to obtain slave clock information;
the master-slave clock deviation judging module is used for judging whether the deviation of the master clock information and the slave clock information meets a preset condition or not;
and the target slave clock information determining module is used for inputting the deviation of the master clock information and the slave clock information into the sliding mode controller when the deviation of the master clock information and the slave clock information does not meet the preset condition, returning to the first information determining module and continuing to execute until the deviation of the master clock information and the slave clock information meets the preset condition, and obtaining target slave clock information.
Optionally, the first information determining module includes:
the first intermediate value determining submodule is used for inputting the main clock information into the sliding mode controller and obtaining a first intermediate value through a first formula of the sliding mode controller;
the second intermediate value determining submodule is used for obtaining a second intermediate value through a second formula of the sliding mode controller;
a third intermediate value determining submodule, configured to obtain a third intermediate value through the first intermediate value and the second intermediate value;
and the first information determining submodule is used for inputting the third intermediate value into a third formula of the sliding mode controller, and obtaining first information through the third formula.
Optionally, the second information determining module includes:
the interference processing submodule is used for adding preset interference information to the first information to obtain the first information after interference processing;
the second information determining submodule is used for processing the first information subjected to interference processing through a controlled object function to obtain second information; wherein the controlled object function is represented as:
x(k)＝Ax(k-1)+B(u(k)+ω(k))
y(k)＝Cx(k)
wherein x (k) represents a state variable at the current time; x (k-1) represents a state variable at the last time; u (k) represents the first information; ω (k) represents process noise; a represents a system matrix; b represents an input matrix; representing an output matrix; y (k) represents the second information.
Optionally, the slave clock information determining module includes:
the noise adding processing submodule is used for adding noise to the second information through a preset formula; the preset formula is expressed as:
yv(k)＝y(k)+v(k)
wherein, yv(k) Representing the second information after the noise adding processing; y (k) represents the second information; v (k) represents measurement noise;
and the slave clock information determination submodule is used for calculating the second information subjected to the noise adding processing through a preset equation set of a Kalman filter to obtain slave clock information.
In a third aspect, an embodiment of the present invention discloses an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete mutual communication through the communication bus;
the memory is used for storing a computer program;
the processor is configured to implement the method steps of any of the above-described slave clock information optimization methods when executing the program stored in the memory.
In a fourth aspect, an embodiment of the present invention discloses a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method steps of any one of the above slave clock information optimization methods are implemented.
In the method, the device, the electronic device and the storage medium for optimizing the slave clock information, provided by the embodiment of the invention, firstly, the sliding mode controller is utilized to process the deviation between the slave clock information and the master clock information, so that the effective control and optimization of the master-slave clock crystal oscillator frequency drift can be realized, then, the Kalman filter is adopted to process the output information of the sliding mode controller, the effective suppression of the external interference influence such as the slave clock crystal oscillator jitter and the random error can be realized, and further, the target slave clock information corresponding to the condition that the deviation between the slave clock information and the master clock information meets the preset condition is obtained. The obtained target slave clock information reduces the influence of oscillation frequency drift of the slave clock crystal oscillator and the influence of jitter and random errors of the slave clock crystal oscillator on the accuracy of the slave clock information, thereby effectively reducing the deviation of the master clock and the slave clock and realizing more accurate master clock and slave clock synchronization.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a precision time protocol PTP delay response mechanism according to an embodiment of the present invention;
FIG. 2 is a flow chart of a slave clock information optimization method according to an embodiment of the present invention;
FIG. 3 is a system framework diagram for slave clock information optimization according to an embodiment of the present invention;
FIG. 4 is a simulation comparison diagram of processing results of a slave clock information optimization method using a Kalman filter and a Kalman filter in the prior art;
fig. 5 is a simulation result diagram of a slave clock information optimization method according to an embodiment of the present application, where a synchronization period of T ═ 1s is used;
FIG. 6 is a diagram illustrating a comparison of simulation results of master and slave clocks in master and slave clock information at different synchronization cycles according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a slave clock information optimization apparatus according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the study of time synchronization of a 1588 protocol, master-slave time synchronization precision is related to frequency drift, frequency jitter and random error of a clock crystal oscillator, and a Kalman filter and a sliding mode controller are adopted to realize control and optimization of three factors of a slave clock, so that master-slave time high-precision synchronization is realized.
Firstly, a Protocol Time synchronization principle and influencing factors, a Precision clock synchronization principle of a Precision Time Protocol (PTP) and a proposed delay response mechanism are mainly divided into six steps. Referring to fig. 1, a diagram of a precision time protocol PTP delay response mechanism according to an embodiment of the present invention is shown. In fig. 1, a is a sync message, b is a Follow message, c is a Delay _ req Delay request message, d is a Delay _ req Delay request response message, Master is a Master clock, and Slave is a Slave clock. The message receiving and sending process of the delayed response synchronization mechanism is as follows:
the master clock periodically sends out the sync message, and records the precise sending time t1 when the sync message leaves the master clock. The master clock encapsulates the precise transmit time t1 into a Follow _ up message for transmission to the slave clock. The slave clock records the exact time of arrival t2 of the sync message at the slave clock. A delay _ req message is sent from the clock and the exact time of transmission t3 is recorded. The master clock records the exact arrival time t4 at which the delay _ req message arrived at the master clock. The master clock sends a delay _ resp message carrying precise timestamp information t4 to the slave clock. The time deviation of the master clock and the slave clock of the mechanism is offset; the average time delay of message transmission in the network is delay; it is assumed that the time delay of the transmission link of the synchronization packet is symmetric:
according to the above two equations, the time offset and the average delay can be obtained.
The high-precision clock synchronization protocol of the 1588 protocol is based on an ideal situation, and in an actual network measurement and control system, many influence factors, such as timestamp accuracy, transmission link asymmetry, network delay inherent jitter, master-slave clock crystal oscillator drift and jitter, are present. To realize high-precision master-slave clock synchronization of the 1588 protocol, two factors, namely asymmetry of a transmission link and crystal oscillator drift and jitter of the master-slave clock, are greatly influenced. In the calculation of the time offset and the average delay, it is assumed that transmission links of the message in the network are symmetrical, but transmission in the actual network may pass through a switch or other devices, which may cause an unequal delay of the round-trip path of the message in transmission. The application mainly studies the influence of the master-slave clock crystal oscillator drift, so that, here, according to a general control variable method, it is assumed that transmission links of messages in a network are symmetrical.
According to the slave clock information optimization method, the sliding mode controller, the Kalman filter and the 1588 protocol of the current-stage research hotspot are effectively and organically combined based on the sliding mode control and the 1588 protocol time synchronization of the Kalman filter, so that the higher-precision time synchronization of the 1588 protocol is realized. Aiming at the error of approximate linear growth caused by the frequency drift of the master clock oscillator and the slave clock oscillator, the sliding mode control is adopted to realize effective control and optimization; aiming at random errors caused by clock frequency jitter, external interference and the like, the Kalman filter is adopted to filter the noise such as the random errors, and effective suppression is realized. Specific methods are described in detail in the following examples.
In a first aspect, an embodiment of the present invention discloses a slave clock information optimization method, as shown in fig. 2. Fig. 2 is a flowchart of a slave clock information optimization method disclosed in the embodiment of the present invention, where the method includes:
s201, acquiring master clock information.
In the application, the master clock information is set as a standard clock source, and the time expressed by the slave clock is the time accumulation of the oscillation frequency of the local crystal oscillator. The oscillation frequency of the crystal oscillator not only depends on the inherent characteristics of the crystal oscillator such as material, corner cut, shape, aging and the like, but also depends on the external environment such as temperature, humidity, pressure and the like. Due to the influence of factors such as ambient temperature and self aging of the crystal oscillator, the crystal oscillator generates certain errors and accumulates with time, so that error deviation is generated between the slave clock and the master clock, and the synchronization precision is seriously influenced. The self-aging of the crystal oscillator has relatively slow influence on the frequency drift of the crystal oscillator, and the environmental temperature has real-time influence on the crystal oscillator.
In this step, master clock information is obtained, and the master clock information may be specific time or an initial value defined by an implementer. Setting the master clock information as: m (t) t.
S202, the main clock information is processed through the sliding mode controller to obtain first information.
In the step, main clock information is input into a sliding mode controller, and clock crystal oscillation frequency drift is effectively controlled and optimized through the sliding mode controller based on an exponential approach law. The input master clock information may be represented by yd.
Optionally, in S202, the processing the master clock information by the sliding mode controller to obtain first information, including:
the first formula for this sliding mode controller is expressed as:
yd (k+1)＝2yd (k)-yd (k-1)
wherein, yd(k) The position instruction corresponding to the current input information of the sliding mode controller is input for the first time, namely the position instruction corresponding to the main clock information; y isd(k-1) the implementer may be y when the master clock information is the first input of the sliding mode controller, corresponding to the position command of the last input information of the sliding mode controllerd(k-1) setting an initial value; y isd(k +1) corresponds to a position command of the next input information of the sliding mode controller.
The first intermediate value y can be obtained by the first formulad(k+1)。
the first formula for this sliding mode controller is expressed as:
dyd (k+1)＝2dyd (k)-dyd (k-1)
wherein dyd(k) The rate of change of the position command corresponding to the current input information of the sliding mode controller; dyd(k-1) a rate of change of the position command corresponding to last input information of the sliding mode controller; dyd(k +1) corresponds to the rate of change of the position command of the next input information of the sliding mode controller.
The second intermediate value y can be obtained by the second formulad(k+1)、dyd(k)。
And 3, obtaining a third intermediate value through the first intermediate value and the second intermediate value.
Y is obtained by calculation in the stepd＝[yd(k)dyd(k)]TAnd Yd1＝[yd(k+1)dyd(k+1)]TAnd obtaining a switching function s (k) Ce(Yd-x)。
And 4, inputting the third intermediate value into a third formula of the sliding mode controller, and obtaining the first information through the third formula.
The third formula of the sliding mode controller is expressed as:
u(k)＝(CeB)-1(CeYd1-CeAx(k)-s(k)-ds(k))
wherein u (k) represents first information obtained by sliding mode control of exponential approximation law; ceRepresents a sliding mode controller coefficient matrix, meets the Hurwitz condition, Ce＝[c 1]C is a constant and c>0; b represents an input matrix; y isd1＝[yd(k+1)dyd(k+1)]T(ii) a A represents a system matrix; x (k) represents information input to the sliding mode controller, the first time is master clock information, and the later time is deviation between the slave clock information and the master clock information; s (k) denotes a switching function, s (k) is Ce(Yd-x); ds (k) — Tsgn (s (k)) -qts (k), meaning that T denotes the synchronization period of the message, sgn () denotes a step function, and q denotes an exponential term coefficient.
S203, carrying out interference processing on the first information, and processing the first information subjected to the interference processing through a controlled object function to obtain second information; the controlled object function is a function obtained by performing laplace transform and discretization on a function expression of slave clock information corresponding to the master clock information.
The controlled object function of the step is a process of output change caused by state and input, and the information output by the sliding mode controller is optimized through the controlled object function to obtain second information.
The transfer function of the controlled object is obtained by performing Laplace transform on a function expression of the slave clock information and discretizing.
The functional expression of the slave clock information is:
wherein the content of the first and second substances,
to influence the frequency offset rate of the slave clock signal by temperature, u (t) is the random error that is generated.
The controlled object transfer function of the sliding mode controller system can be obtained by performing Laplace transform on the function expression of the slave clock information,
wherein S, S2Represents a variable transformed by laplace; the discrete sampling is performed according to the above formula, for example, the sampling time Ts is 0.001s, and the above formula is discretized into the controlled object function of the present application.
Optionally, the performing interference processing on the first information in S203, and processing the first information after the interference processing through a controlled object function to obtain second information includes:
step a, adding preset interference information to the first information to obtain the first information after interference processing.
In this step, if the preset interference information w is added to the first information, the first information after the interference processing may be denoted as u (k) ═ u (k) + wn (k).
B, processing the first information subjected to interference processing through a controlled object function to obtain second information; wherein, the controlled object function is expressed as:
x(k)＝Ax(k-1)+B(u(k)+ω(k))
y(k)＝Cx(k)
wherein x (k) represents a state variable at the current time; x (k-1) represents a state variable at the last time; u (k) represents the first information; ω (k) represents process noise; a represents a system matrix; b represents an input matrix; c represents an output matrix; y (k) represents the second information.
And S204, performing noise adding processing on the second information, and processing the second information subjected to the noise adding processing through a Kalman filter to obtain a slave clock signal.
The step realizes effective inhibition of external interference influence such as clock crystal oscillator jitter, random error and the like through Kalman filtering.
Optionally, in S204, the noise-adding processing is performed on the second information, and the second information after the noise-adding processing is processed through a kalman filter, so as to obtain the slave clock information, where the noise-adding processing includes:
step 1), carrying out noise adding processing on the second information through a preset formula; the preset formula is expressed as:
yv(k)＝y(k)+v(k)
wherein, yv(k) Representing the second information after the noise adding process; y (k) represents second information; v (k) represents measurement noise.
And step 2), calculating the second information subjected to the noise adding treatment through a preset equation set of a Kalman filter to obtain slave clock information.
The predetermined system of equations for the kalman filter is expressed as:
x(k)＝Ax(k-1)+Mn(k)(yv(k)-CAx(k-1))
ye(k)＝Cx(k)
wherein M isn(k) A gain representing a blending factor or residue; a represents a system matrix; b represents a matrix of input variables; c represents an output matrix; p (k) represents the a posteriori estimated covariance;
an intermediate calculation result representing the prior estimated covariance at time k; r represents; p (k-1); q represents process excitation noise covariance; x (k) represents the current time state equation of the kalman filter; y isv(k) Representing the second information after the noise adding process; x (k-1) represents a last moment state equation of the Kalman filter; y ise(k) The slave clock information, which represents the output, may be represented in form by ye.
And S205, judging whether the deviation of the master clock information and the slave clock information meets a preset condition.
In the embodiment of the invention, the preset condition is a preset numerical value close to zero, and the specific numerical value is set by an implementer. In this step, it is determined whether the deviation of the slave clock information from the master clock information is equal to or less than a threshold value. I.e., it is determined whether the difference in the master clocks yd-ye is equal to or less than the threshold. The difference of yd-ye physically means the time offset between the upper master and slave clocks:
s206, when the deviation between the master clock information and the slave clock information does not meet the preset condition, inputting the deviation between the master clock information and the slave clock information into the sliding mode controller, and executing S202-S205 until the deviation between the master clock information and the slave clock information meets the preset condition, so as to obtain the target slave clock information.
When the difference of yd-ye is judged to be larger than the threshold value in the above S205, the step S202-S205 is continuously executed with the difference of yd-ye being input to the sliding mode controller until the difference of yd-ye is equal to or smaller than the threshold value. The corresponding slave clock information at this time is taken as the target slave clock information, which shows that the influence of the frequency offset rate and the random error on the slave clock accuracy is optimized at this time, the target slave clock information at this time is more accurate, and the master-slave clock synchronization is more accurately realized.
In the method for optimizing the slave clock information provided by the embodiment of the invention, firstly, the sliding mode controller is utilized to process the deviation between the slave clock information and the master clock information, so that the effective control and optimization of the crystal oscillator frequency drift of the master clock and the slave clock can be realized, then, the Kalman filter is adopted to process the output information of the sliding mode controller, so that the effective inhibition of the influence of external interference such as the crystal oscillator jitter of the slave clock, random errors and the like can be realized, and further, the target slave clock information corresponding to the condition that the deviation between the slave clock information and the master clock information meets the preset condition is obtained. The obtained target slave clock information reduces the influence of oscillation frequency drift of the slave clock crystal oscillator and the influence of jitter and random errors of the slave clock crystal oscillator on the accuracy of the slave clock information, thereby effectively reducing the deviation of the master clock and the slave clock and realizing more accurate master clock and slave clock synchronization.
To better illustrate a slave clock information optimization method of the present invention, there may be a slave clock information optimization system framework diagram of the embodiment of the present invention as shown in fig. 3.
In the embodiment of the invention, firstly, main clock information yd is input into a sliding mode controller, and is processed by the sliding mode controller to obtain first information; adding control interference w into the first information, and processing the first information added with the control interference through a controlled object function to obtain second information; adding measurement noise v into the second information processed by the controlled object function, and inputting the second information added with the measurement noise v into a Kalman filter; processing the information through a Kalman filter, and outputting to obtain slave clock information ye; and calculating the difference value of the yd-ye, judging whether the difference value of the yd-ye meets a preset condition or not, inputting the difference value of the yd-ye into the sliding mode controller when the difference value of the yd-ye does not meet the preset condition, and repeatedly executing the steps until the difference value of the yd-ye meets the preset condition, wherein the value of the ye at the moment is used as target slave clock information.
Advantages of embodiments of the present invention may be illustrated using simulink simulations as follows.
Aiming at the slave clock information optimization method, a system matrix can be set
Input matrix
Input matrix C ═ 10](ii) a The transmission matrix D is 0; white noise signal ω (k) is [ -0.80.8](ii) a White noise signal v (k) is [ -0.0010.001]In the Kalman filter, the covariance Q of process excitation noise is 10; observation noise covariance R ═ 10; in sliding mode controllers, coefficient matrix CeConstant c of (1) 25; the rate of approach to the switching plane is 130; the index term coefficient q is 280; setting the deviation of the initial master clock information and the slave clock information to be 0.000001 s; the deviation threshold value of the master clock information and the slave clock information is 10 us; the offset of the master clock information from the slave clock information, plus the kalman filter, is compared with the results of the un-timed kalman filter, and this comparison is shown in fig. 4. Fig. 4 is a simulation comparison diagram of processing results of a slave clock information optimization method using a kalman filter and a method for optimizing slave clock information in the prior art. In fig. 4, offset1 represents the result of the kalman filter of the present application, and offset2 represents the result of the prior art kalman filter in the natural state.
As can be seen from fig. 4, when the master clock and the slave clock are not synchronized, the time deviation increases approximately linearly and is accompanied by a slight jitter, but after the kalman filter filtering, the curve becomes significantly smooth, the jitter is smaller, and the jitter of the time deviation is significantly suppressed. Therefore, the Kalman filter is adopted in the method, so that the master-slave time synchronization precision of the 1588 protocol is improved to a certain extent.
When a synchronization period of T ═ 1s is used, a graph of the results from one of the slave clock information optimization methods of the present application can be seen in fig. 5. Fig. 5 is a simulation result diagram of a slave clock information optimization method according to an embodiment of the present application, where a synchronization period of T ═ 1s is used.
As can be seen from fig. 5, in the slave clock information optimization method of the present application, through the processing of the kalman filter and the sliding mode controller, the master-slave time offset is not only effectively suppressed and optimized by the approximately linearly increasing portion caused by the clock frequency drift, but also well controlled by the random error caused by the slave clock frequency jitter, so that the offset rapidly converges to a value near a minimum value within 5s, the curve becomes smoother, and remains stable to a great extent. Therefore, in the slave clock information optimization method, the sliding mode controller and the Kalman filter are used for improving the master-slave time synchronization precision of the 1588 protocol, and the method has great practicability and feasibility.
The master-slave clock information of three different synchronization periods (T1 ═ 0.1s, T2 ═ 0.5s, and T3 ═ 1.0s) is processed by the slave clock information optimization method of the present application, and the result comparison graph shown in fig. 6 can be obtained. Fig. 6 is a comparison diagram of simulation results of master and slave clocks in master and slave clock information in different synchronization cycles according to an embodiment of the present invention.
As can be seen from fig. 6, when the synchronization period T3 is 1s, it converges rapidly within about 5 s; when T2 is 0.5s, convergence is fast approximately within 3 s; when T1 is 0.1s, convergence is fast approximately within 2 s. That is, as the message synchronization period is continuously reduced, the master-slave time deviation converges faster, and the accuracy of time synchronization is higher. According to the slave clock information optimization method, based on the Kalman filter and the sliding mode controller, the slave clock speed can be effectively regulated and controlled for signals with different synchronization periods, so that the signals can quickly follow the master clock, and better time synchronization precision is achieved, so that control and optimization of 1588 protocol different master-slave clock synchronization periods are realized, the time synchronization precision is improved, and the requirements of 5G (5G network, fifth generation mobile communication network) on time synchronization nanosecond level are met.
In a second aspect, an embodiment of the present invention discloses a slave clock information optimization apparatus, which can be seen in fig. 7. Fig. 7 is a schematic structural diagram of a slave clock information optimization apparatus according to an embodiment of the present invention, where the apparatus includes:
a master clock information obtaining module 701, configured to obtain master clock information;
a first information determining module 702, configured to process the master clock information through a sliding mode controller to obtain first information;
a second information determining module 703, configured to perform interference processing on the first information, and process the first information after the interference processing through a controlled object function to obtain second information; the controlled object function is a function obtained by performing Laplace transform and discretization on a function expression of slave clock information corresponding to the master clock information;
a slave clock information determining module 704, configured to perform noise addition on the second information, and process the second information subjected to noise addition through a kalman filter to obtain slave clock information;
a master-slave clock deviation determining module 705, configured to determine whether a deviation between master clock information and slave clock information meets a preset condition;
and the target slave clock information determining module 706 is configured to, when the deviation between the master clock information and the slave clock information does not meet the preset condition, input the deviation between the master clock information and the slave clock information to the sliding mode controller, return to the first information determining module, and continue to execute until the deviation between the master clock information and the slave clock information meets the preset condition, so as to obtain the target slave clock information.
Optionally, in an embodiment of the slave clock information optimization apparatus of the present invention, the first information determining module 702 includes:
the first intermediate value determining submodule is used for inputting the main clock information into the sliding mode controller and obtaining a first intermediate value through a first formula of the sliding mode controller;
the second intermediate value determining submodule is used for obtaining a second intermediate value through a second formula of the sliding mode controller;
the third intermediate value determining submodule is used for obtaining a third intermediate value through the first intermediate value and the second intermediate value;
and the first information determining submodule is used for inputting the third intermediate value into a third formula of the sliding mode controller, and obtaining first information through the third formula.
Optionally, in an embodiment of the slave clock information optimization apparatus of the present invention, the second information determining module 703 includes:
the interference processing submodule is used for adding preset interference information to the first information to obtain the first information after interference processing;
the second information determining submodule is used for processing the first information subjected to the interference processing through a controlled object function to obtain second information; wherein, the controlled object function is expressed as:
x(k)＝Ax(k-1)+B(u(k)+ω(k))
y(k)＝Cx(k)
wherein x (k) represents a state variable at the current time; x (k-1) represents a state variable at the last time; u (k) represents the first information; ω (k) represents process noise; a represents a system matrix; b represents an input matrix; representing an output matrix; y (k) represents the second information.
Optionally, in an embodiment of the slave clock information optimization apparatus of the present invention, the slave clock information determining module 704 includes:
the noise adding processing submodule is used for adding noise to the second information through a preset formula; the preset formula is expressed as:
yv(k)＝y(k)+v(k)
wherein, yv(k) Representing the second information after the noise adding process; y (k) represents second information; v (k) represents measurement noise;
and the slave clock information determination submodule is used for calculating the second information subjected to the noise adding processing through a preset equation set of the Kalman filter to obtain the slave clock information.
In a third aspect, an embodiment of the present invention discloses an electronic device, as shown in fig. 8. Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, which includes a processor 801, a communication interface 802, a memory 803, and a communication bus 804, where the processor 801, the communication interface 802, and the memory 803 complete communication with each other through the communication bus 804;
a memory 803 for storing a computer program;
the processor 801 is configured to implement the method steps of any of the above-described slave clock information optimization methods when executing the program stored in the memory 803.
The communication bus 804 mentioned in the above electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus 804 may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface 802 is used for communication between the above-described electronic apparatus and other apparatuses.
The Memory 803 may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory 803 may also be at least one storage device located remotely from the processor 801.
The Processor 801 may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
In the electronic device provided by the embodiment of the invention, the sliding mode controller is used for processing the deviation between the slave clock information and the master clock information, so that the frequency drift of the master-slave clock crystal oscillator can be effectively controlled and optimized, and then the Kalman filter is used for processing the information output by the sliding mode controller, so that the influence of external interference such as the jitter of the slave clock crystal oscillator, random errors and the like can be effectively inhibited, and the target slave clock information corresponding to the condition that the deviation between the slave clock information and the master clock information meets the preset condition is obtained. The obtained target slave clock information reduces the influence of oscillation frequency drift of the slave clock crystal oscillator and the influence of jitter and random errors of the slave clock crystal oscillator on the accuracy of the slave clock information, thereby effectively reducing the deviation of the master clock and the slave clock and realizing more accurate master clock and slave clock synchronization.
In a fourth aspect, an embodiment of the present invention discloses a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed by a processor, the method steps of any one of the above slave clock information optimization methods are implemented.
In the computer-readable storage medium provided by the embodiment of the invention, firstly, the sliding mode controller is used for processing the deviation between the slave clock information and the master clock information, so that the effective control and optimization of the crystal oscillator frequency drift of the master clock and the slave clock can be realized, then, the Kalman filter is used for processing the output information of the sliding mode controller, so that the effective suppression of the influence of external interference such as the crystal oscillator jitter of the slave clock, random errors and the like can be realized, and further, the target slave clock information corresponding to the condition that the deviation between the slave clock information and the master clock information meets the preset condition is obtained. The obtained target slave clock information reduces the influence of oscillation frequency drift of the slave clock crystal oscillator and the influence of jitter and random errors of the slave clock crystal oscillator on the accuracy of the slave clock information, thereby effectively reducing the deviation of the master clock and the slave clock and realizing more accurate master clock and slave clock synchronization.
The computer instructions may be stored on or transmitted from one computer-readable storage medium to another computer-readable storage medium, e.g., from one website site, computer, server, or data center via wired (e.g., coaxial cable, optical fiber, digital subscriber line (DS L)) or wireless (e.g., infrared, wireless, microwave, etc.) means to another website site, computer, server, or data center, the computer-readable storage medium may be any available medium accessible by a computer or including one or more available media, such as a Solid State Disk, a magnetic storage medium (e.g., a floppy Disk, a Solid State Disk, a floppy Disk, a Solid State Disk, a magnetic storage medium (e.g., a Solid State Disk, a floppy Disk, a Solid State Disk, a magnetic storage medium, a hard Disk, a Solid State Disk, a magnetic storage medium, a magnetic Disk, a magnetic storage medium, a magnetic Disk, a magnetic storage medium, a magnetic Disk, or the like.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the device, the electronic apparatus and the storage medium embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and the relevant points can be referred to the partial description of the method embodiments.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A method for slave clock information optimization, the method comprising:
step A, acquiring master clock information;
b, processing the master clock information through a sliding mode controller to obtain first information;
step C, carrying out interference processing on the first information, and processing the first information subjected to the interference processing through a controlled object function to obtain second information; the controlled object function is a function obtained by performing Laplace transform and discretization on a function expression of slave clock information corresponding to the master clock information;
step D, carrying out noise adding processing on the second information, and processing the second information subjected to the noise adding processing through a Kalman filter to obtain slave clock information;
step E, judging whether the deviation of the master clock information and the slave clock information meets a preset condition or not;
and F, when the deviation between the master clock information and the slave clock information does not meet the preset condition, inputting the deviation between the master clock information and the slave clock information into the sliding mode controller, and executing the steps B to E until the deviation between the master clock information and the slave clock information meets the preset condition, so as to obtain target slave clock information.
2. The method of claim 1, wherein processing the master clock information through a sliding mode controller to obtain first information comprises:
inputting the main clock information into a sliding mode controller, and obtaining a first intermediate value through a first formula of the sliding mode controller;
obtaining a second intermediate value through a second formula of the sliding mode controller;
obtaining a third intermediate value according to the first intermediate value and the second intermediate value;
and inputting the third intermediate value into a third formula of the sliding mode controller, and obtaining first information through the third formula.
3. The method according to claim 1, wherein the performing interference processing on the first information and processing the first information after the interference processing by a controlled object function to obtain second information comprises:
adding preset interference information to the first information to obtain the first information subjected to interference processing;
processing the first information subjected to interference processing through a controlled object function to obtain second information; wherein the controlled object function is represented as:
x(k)＝Ax(k-1)+B(u(k)+ω(k))
y(k)＝Cx(k)
wherein x (k) represents a state variable at the current time; x (k-1) represents a state variable at the last time; u (k) represents the first information; ω (k) represents process noise; a represents a system matrix; b represents an input matrix; representing an output matrix; y (k) represents the second information.
4. The method according to claim 1, wherein the denoising the second information and processing the denoised second information through a kalman filter to obtain slave clock information comprises:
denoising the second information through a preset formula; the preset formula is expressed as:
yv(k)＝y(k)+v(k)
wherein, yv(k) Representing the second information after the noise adding processing; y (k) represents the second information; v (k) represents measurement noise;
and calculating the second information subjected to the noise adding treatment through a preset equation set of a Kalman filter to obtain slave clock information.
5. A slave clock information optimization apparatus, the apparatus comprising:
the master clock information acquisition module is used for acquiring master clock information;
the first information determining module is used for processing the master clock information through a sliding mode controller to obtain first information;
the second information determining module is used for carrying out interference processing on the first information and processing the first information subjected to the interference processing through a controlled object function to obtain second information; the controlled object function is a function obtained by performing Laplace transform and discretization on a function expression of slave clock information corresponding to the master clock information;
the slave clock information determining module is used for carrying out noise adding processing on the second information and processing the second information subjected to the noise adding processing through a Kalman filter to obtain slave clock information;
the master-slave clock deviation judging module is used for judging whether the deviation of the master clock information and the slave clock information meets a preset condition or not;
and the target slave clock information determining module is used for inputting the deviation of the master clock information and the slave clock information into the sliding mode controller when the deviation of the master clock information and the slave clock information does not meet the preset condition, returning to the first information determining module and continuing to execute until the deviation of the master clock information and the slave clock information meets the preset condition, and obtaining target slave clock information.
6. The apparatus of claim 5, wherein the first information determining module comprises:
the first intermediate value determining submodule is used for inputting the main clock information into the sliding mode controller and obtaining a first intermediate value through a first formula of the sliding mode controller;
the second intermediate value determining submodule is used for obtaining a second intermediate value through a second formula of the sliding mode controller;
a third intermediate value determining submodule, configured to obtain a third intermediate value through the first intermediate value and the second intermediate value;
and the first information determining submodule is used for inputting the third intermediate value into a third formula of the sliding mode controller, and obtaining first information through the third formula.
7. The apparatus of claim 5, wherein the second information determining module comprises:
the interference processing submodule is used for adding preset interference information to the first information to obtain the first information after interference processing;
the second information determining submodule is used for processing the first information subjected to interference processing through a controlled object function to obtain second information; wherein the controlled object function is represented as:
x(k)＝Ax(k-1)+B(u(k)+ω(k))
y(k)＝Cx(k)
wherein x (k) represents a state variable at the current time; x (k-1) represents a state variable at the last time; u (k) represents the first information; ω (k) represents process noise; a represents a system matrix; b represents an input matrix; c represents an output matrix; y (k) represents the second information.
8. The apparatus of claim 5, wherein the slave clock information determining module comprises:
the noise adding processing submodule is used for adding noise to the second information through a preset formula; the preset formula is expressed as:
yv(k)＝y(k)+v(k)
wherein, yv(k) Representing the second information after the noise adding processing; y (k) represents the second information; v (k) represents measurement noise;
and the slave clock information determination submodule is used for calculating the second information subjected to the noise adding processing through a preset equation set of a Kalman filter to obtain slave clock information.
9. An electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete communication with each other through the communication bus;
the memory is used for storing a computer program;
the processor, when executing the program stored in the memory, implementing the method steps of any of claims 1-4.
10. A computer-readable storage medium, characterized in that a computer program is stored in the computer-readable storage medium, which computer program, when being executed by a processor, carries out the method steps of any one of claims 1 to 4.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201681266U (en) * | 2010-05-31 | 2010-12-22 | 向洪莉 | Clock |
| CN102857315A (en) * | 2011-06-29 | 2013-01-02 | 中兴通讯股份有限公司 | Method and system for serving slave clocks by master clock |
| CN109212285A (en) * | 2018-11-29 | 2019-01-15 | 中电科西北集团有限公司 | Outfield simulator |
| CN109546660A (en) * | 2018-11-22 | 2019-03-29 | 中国航空综合技术研究所 | Active power filter circuit and control method based on neural network sliding mode control strategy |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104392136B (en) * | 2014-11-28 | 2017-12-19 | 东南大学 | A kind of high accuracy data fusion method towards high dynamic LDPC code robust measure |
| US20170108612A1 (en) * | 2015-10-15 | 2017-04-20 | King Saud University | Inertial system for gravity difference measurement |
| CN205725536U (en) * | 2016-04-22 | 2016-11-23 | 湖南工业大学 | A kind of adjacent cross-couplings synchronous control system based on sliding moding structure |
| CN108501944A (en) * | 2018-05-14 | 2018-09-07 | 吕杉 | Automotive tyre explosion safety stable control method |
-
2019
- 2019-04-30 CN CN201910364232.8A patent/CN109976442B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201681266U (en) * | 2010-05-31 | 2010-12-22 | 向洪莉 | Clock |
| CN102857315A (en) * | 2011-06-29 | 2013-01-02 | 中兴通讯股份有限公司 | Method and system for serving slave clocks by master clock |
| CN109546660A (en) * | 2018-11-22 | 2019-03-29 | 中国航空综合技术研究所 | Active power filter circuit and control method based on neural network sliding mode control strategy |
| CN109212285A (en) * | 2018-11-29 | 2019-01-15 | 中电科西北集团有限公司 | Outfield simulator |
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