CN109962869A - Digital signal reception module - Google Patents
Digital signal reception module Download PDFInfo
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- CN109962869A CN109962869A CN201810153550.5A CN201810153550A CN109962869A CN 109962869 A CN109962869 A CN 109962869A CN 201810153550 A CN201810153550 A CN 201810153550A CN 109962869 A CN109962869 A CN 109962869A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
- H04L25/085—Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0292—Arrangements specific to the receiver end
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/0264—Arrangements for coupling to transmission lines
- H04L25/0292—Arrangements specific to the receiver end
- H04L25/0296—Arrangements to ensure DC-balance
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
- H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
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- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Dc Digital Transmission (AREA)
Abstract
The present invention provides a kind of digital received module.The digital received module of one embodiment of the invention can include: voltage follower circuit is output to output node as second voltage for based on the first voltage by the received reception signal of communication link；Filtering voltage output section receives above-mentioned second voltage from above-mentioned output node, exports the filtering voltage of the average value as above-mentioned second voltage；Reference voltage generating unit is the reference voltage for being equivalent to offset voltage to the above-mentioned filtering voltage output correction exported from above-mentioned filtering voltage output section；Comparator is compared said reference voltage and above-mentioned second voltage, exports the output signal based on said reference voltage Yu the comparison result of above-mentioned second voltage；Bit-detector is converted to the bit of output digit signals according to above-mentioned output signal.
Description
Technical field
The present invention relates to the modules that digital signal is received in serial communication (Serial Communication) system.
Background technique
For general serial communication system, signal is transmitted at transmitting terminal (Transmitter), in receiving end
(Receiver) transmitted data are received to restore.If continuing to transmit data in serial communication, each bit is distinguished in receiving end,
Grasp the signal transmitted from transmitting terminal.
But it during above-mentioned signal is transmitted by physical communication link (Communication link), may be present
Shake the distorted signals such as (Jitter) and failure (Glitch).In this case, even at generating in serial communication system
The case where distorted signals, receiving end should also have the circuit structure that can be properly received the data transmitted from transmitting terminal.
In the present invention, as described above, in order to solve the root problem generated in serial communication system, even if proposing to send
There are distorted signals between end and receiving end, also can correctly restore the circuit structure of the receiving end of transmitted data-signal.
Summary of the invention
The technical problem to be solved in the present invention
The technical problem to be solved in the present invention is that providing in the serial communication system of transmission digital signal, even if hair
In the case that life generates distorted signals because of the shake generated in the analog signal of coding, the side of digital bit is also correctly decoded
Method and the module for being applicable in this method.
Another technical problem to be solved by the invention is, provides in the serial communication system of transmission digital signal, i.e.,
Make in the case where generating distorted signals due to the failure because generating in communication link occurs, also correctly decodes the method for digital bit
And it is applicable in the module of this method.
Technical problem of the invention is not limited to technical problem mentioned above, the ordinary skill of technical field of the invention
Personnel can be expressly understood that unmentioned another technical problem by contents below.
Technical solution
For solving the digital received module of one embodiment of the invention of above-mentioned technical problem can include: voltage output electricity
Road is output to output node as second voltage for based on the first voltage by the received reception signal of communication link；Filtering
Voltage output portion receives above-mentioned second voltage from above-mentioned output node, exports the filtering of the average value as above-mentioned second voltage
Voltage；Reference voltage generating unit is equivalent to the above-mentioned filtering voltage output correction exported from above-mentioned filtering voltage output section
The reference voltage of offset voltage；Comparator is compared said reference voltage and above-mentioned second voltage, and output is based on above-mentioned base
The output signal of quasi- voltage and the comparison result of above-mentioned second voltage；Bit-detector is converted to defeated according to above-mentioned output signal
The bit of digital signal out.
In one embodiment, above-mentioned voltage follower circuit utilizes AC coupled (AC Coupling), can be by above-mentioned first electricity
The second voltage as impulse response is pressed to be output to above-mentioned output node.
In one embodiment, above-mentioned voltage follower circuit can be for using the radio-frequency component of above-mentioned first voltage as the second electricity
Pressure is output to the high-pass filter (HPF, High Pass Filter) of above-mentioned output node.
In one embodiment, said reference voltage generating unit is exportable rises or falls above-mentioned filtering voltage to being equivalent to
Included N-type metal-oxide semiconductor (MOS) (NMOS, N-Metal-Oxide- in said reference voltage generating unit
Semiconductor) the reference voltage of the critical voltage of transistor.
In one embodiment, said reference voltage generating unit includes P type metal oxide semiconductor (PMOS, P-metal-
Above-mentioned filtering voltage can be applied to the oxidation of aforementioned p-type metal by oxide-semiconductor) transistor and resistive divider
Object semiconductor transistor is exported the above-mentioned filtering voltage of above-mentioned application for said reference voltage using above-mentioned resistive divider.
In one embodiment, the above-mentioned filtering voltage for being applied to aforementioned p-type metal oxide semiconductor transistor can be
The voltage of the grid of aforementioned p-type metal oxide semiconductor transistor is input to by amplifier.
In one embodiment, said reference voltage generating unit is based on the above-mentioned filtering exported from above-mentioned filtering voltage output section
Voltage exports the first reference voltage and the second reference voltage, and above-mentioned first reference voltage can be to be declined than above-mentioned filtering voltage
To the value for being equivalent to offset voltage, above-mentioned second reference voltage, which can be to rise to than above-mentioned filtering voltage, is equivalent to offset voltage
Value.
In one embodiment, above-mentioned comparator includes first comparator and the second comparator, and above-mentioned first comparator passes through
First reversion terminal receives above-mentioned second voltage, can be received by the first non-inverted terminal above-mentioned first reference voltage as a result,
Export the first output signal based on above-mentioned first reference voltage Yu the comparison result of above-mentioned second voltage, above-mentioned second comparator
Above-mentioned second voltage can be received by the second non-inverted terminal, the knot of above-mentioned second reference voltage is received by the second reversion terminal
Fruit exports the second output signal based on above-mentioned second reference voltage Yu the comparison result of above-mentioned second voltage.
In one embodiment, above-mentioned bit-detector exports digital bit 1 by incuding above-mentioned first output signal, can
Digital bit 0 is exported by above-mentioned second output signal.
In one embodiment, digital received module may also include that the first exposure mask, in first interval, in response to above-mentioned first
The induction of output signal blocks above-mentioned first output signal to be sent to above-mentioned bit-detector, and blocks above-mentioned second output letter
Number it is sent to above-mentioned bit-detector；Second exposure mask, the second interval after above-mentioned first interval terminates, in response to above-mentioned
The induction of two output signals blocks above-mentioned second output signal to be sent to above-mentioned bit-detector, and blocks above-mentioned first output
Signal is sent to above-mentioned bit-detector.
For solving the digital received module of the another embodiment of the present invention of above-mentioned technical problem can include: voltage output
Circuit is output to output node as second voltage for based on the first voltage by the received reception signal of communication link；Filter
Wave voltage output section receives above-mentioned second voltage from above-mentioned output node, and exports average value as above-mentioned second voltage
Filtering voltage；It is electric to be equivalent to imbalance to input the above-mentioned filtering voltage correction exported from above-mentioned filtering voltage output section for comparator
The reference voltage of pressure, and export the output signal of the comparison result based on said reference voltage and above-mentioned second voltage；Bit inspection
It surveys device and the bit of output digit signals is converted to according to above-mentioned output signal.
In one embodiment, above-mentioned comparator includes the first N-type metal oxide semiconductor transistor and the second N-type metal
Oxide semi conductor transistor, said reference voltage output is according to the width of above-mentioned first N-type metal oxide semiconductor transistor
It is poor with the width of above-mentioned second N-type metal oxide semiconductor transistor to spend, exportable to rise as by the voltage of above-mentioned biasing
Or drop to the reference voltage for being equivalent to the value of offset voltage.
In one embodiment, above-mentioned comparator includes first comparator and the second comparator, and above-mentioned first comparator is
One non-inverted terminal has the first imbalance power supply, according to above-mentioned first imbalance power supply, can input and be equivalent to imbalance as dropping to
First reference voltage of the value of voltage, by the first reversion terminal input above-mentioned second voltage as a result, exportable based on above-mentioned
First output signal of the first reference voltage and the comparison result of above-mentioned second voltage, above-mentioned second comparator invert end second
Son has the second imbalance power supply, according to above-mentioned second imbalance power supply, can input as rising to the value for being equivalent to offset voltage
Second reference voltage, by the second non-inverted terminal input above-mentioned second voltage as a result, exportable based on above-mentioned second benchmark
Second output signal of voltage and the comparison result of above-mentioned second voltage.
In one embodiment, above-mentioned bit-detector exports digital bit 1 by incuding above-mentioned first output signal, and
Digital bit 0 can be exported by incuding above-mentioned second output signal.
In one embodiment, digital received module may also include that the first exposure mask, in first interval, in response to above-mentioned first
The induction of output signal blocks above-mentioned first output signal to be sent to above-mentioned bit-detector, and blocks above-mentioned second output letter
Number it is sent to above-mentioned bit-detector；Second exposure mask, the second interval after above-mentioned first interval terminates, in response to above-mentioned
The induction of two output signals blocks above-mentioned second output signal to be sent to above-mentioned bit-detector, and blocks above-mentioned first output
Signal is sent to above-mentioned bit-detector.
For solving the digital received module of the another embodiment of the present invention of above-mentioned technical problem can include: voltage output
Circuit is output to output node as second voltage for based on the first voltage by the received reception signal of communication link；The
One comparator receives above-mentioned second voltage by the first reversion terminal, the first set mark is received by the first non-inverted terminal
Quasi- voltage as a result, output the first output signal based on above-mentioned first normal voltage Yu the comparison result of above-mentioned second voltage；
Second comparator receives above-mentioned second voltage by the second non-inverted terminal, receives set second by the second reversion terminal
Normal voltage as a result, the second output signal of the comparison result of above-mentioned second normal voltage of output and above-mentioned second voltage；The
One exposure mask blocks above-mentioned first output signal to be sent to above-mentioned in first interval in response to the induction of above-mentioned first output signal
Bit-detector, and above-mentioned second output signal is blocked to be sent to above-mentioned bit-detector；Second exposure mask, in above-mentioned first interval
Second interval after end blocks above-mentioned second output signal to be sent in response to the induction of above-mentioned second output signal
Bit-detector is stated, and above-mentioned first output signal is blocked to be sent to above-mentioned bit-detector.
Beneficial effect
According to the present invention, in the serial communication system of transmission digital signal, even if occurring because in the analog signal of coding
The shake of generation and in the case where generating distorted signals, also correctly decode digital bit.Also, in the string of transmission digital signal
In port communications system, even if occurring in the case where generating distorted signals because of the failure generated in communication link, also correctly solve
Code digital bit.
Detailed description of the invention
Fig. 1 is for illustrating to fill using the digital received module of one embodiment of the invention and the host of digital sending module
It sets and the schematic diagram of the digital communication system of client terminal device.
Fig. 2 is logical using the digital received module of one embodiment of the invention and the number of digital sending module for illustrating
The schematic diagram of letter system.
Fig. 3 is the circuit for illustrating the communication mode using the AC coupled for being suitable for the invention several embodiments
Figure.
Fig. 4 is the timing diagram of the output voltage for illustrating to export in ac-coupled circuit.
Fig. 5 is the circuit for illustrating the communication system using the AC coupled for being suitable for the invention several embodiments
Figure.
Fig. 6 is the timing diagram for illustrating the digital communication of the AC coupled using several embodiments of the present invention.
Fig. 7 to Fig. 8 is for illustrating in the digital communication using the AC coupled for being suitable for the invention several embodiments
The timing diagram of the mistake of generation.
Fig. 9 is the figure for illustrating the digital received module of one embodiment of the invention.
Figure 10 is the improvement point for illustrating the digital communication of the digital received module using one embodiment of the invention
Timing diagram.
Figure 11 is an embodiment of the reference voltage generating unit for illustrating to adopt in several embodiments of the invention
Figure.
Figure 12 is another implementation of the reference voltage generating unit for illustrating to adopt in several embodiments of the invention
The figure of example.
Figure 13 is the figure for illustrating the digital received module of another embodiment of the present invention.
Figure 14 is the figure of the comparator for illustrating to adopt in several embodiments of the invention.
Figure 15 is the mistake for generating in illustrating to be suitable for the invention the digital communication of the AC coupled of several embodiments
Timing diagram accidentally.
Figure 16 to Figure 18 is the figure for illustrating the digital received module of another embodiment of the present invention.
Figure 19 is the timing diagram for illustrating the improvement point of the communication of the digital received module using Figure 16 to Figure 18.
Specific embodiment
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.Advantages of the present invention and feature and realize this
A little methods will become clear with the embodiment being described in detail later referring to attached drawing.But the present invention is not limited to reality disclosed below
Example is applied, can be realized with different variforms, only the present embodiment becomes disclosure of the invention completely, in order to give
General technical staff of the technical field of the invention completely informs the scope of invention and provides that the present invention can be wanted by invention
The scope of protection scope is asked to define.In the specification, identical appended drawing reference censures identical structural element.
If without other definition, all terms (including technology and scientific term) used in the present specification be can be used
The meaning that can be commonly understood by for general technical staff of the technical field of the invention.Also, determine in the dictionary generally used
The term of justice just must not be ideal or be excessively explained as long as no specific specifically defined.The term used in the present specification is used
In illustrating embodiment, and the present invention is not limited to this.In the present specification, it is referred to as long as singular type is special not in sentence,
It further include most types.
Used in the specification " including (comprises) " and/or " including (comprising) " for, refer to
Structural element, step, operating and/or device be not excluded for depositing for more than one structural element, step, operating and/or device
Or it is additional.
Before illustrating this specification, it is expressly recited several terms used in this specification.
In the present specification, host apparatus means the electronic device operated by own power source.Host apparatus is packet
Include the electronic device for the digital received module being arranged for digital communication.Client terminal device means and above-mentioned host apparatus electricity
Connect and execute the device of multiple functions.
Host apparatus include the computer installation comprising PC, notebook, tablet computer etc., comprising smart phone,
The mobile device of MP3 player, PMP etc., but not limited to this.
Client terminal device includes the earplug, earphone, headset etc. connecting with above-mentioned computer installation or mobile device, but not office
It is limited to this, above-mentioned computer installation can be become by noticing.
In the following, with reference to the accompanying drawings, several embodiments that the present invention will be described in detail.
Fig. 1 is the host apparatus 10 and client dress for illustrating the digital received module including one embodiment of the invention
Set the schematic diagram of 20 digital communication system.
In several embodiments of the invention, host apparatus 10 and client terminal device 20 execute digital communication.In order to help
In understanding the present invention, host apparatus 10 illustrates the one-way communication that numerical data is received in client terminal device 10.But this
The direction of kind data flow is not limited to this.If the client terminal device 20 with itself digital received module, then can be according to this hair
Bright embodiment transmits numerical data to host apparatus 10 from client terminal device 20.
Host apparatus 10 and client terminal device 20 utilize serial communication mode, execute digital communication.Therefore, host apparatus 10
It can be connected by the communication link 30 of transmission digital bit with client terminal device 20.
Host apparatus 10 and client terminal device 20 utilize the edge (edge) of the pulse voltage Vline by communication link 30
Digital communication can be performed in ingredient.Host apparatus 10 and client terminal device 20 are gone back while executing digital communication using voltage level
Power source communications are executed using communication link 30.In this case, client terminal device 20 has without having the volume for power supply
The advantages of outer power supply source and additional communication link.
Fig. 2 is logical using the digital received module of one embodiment of the invention and the number of digital sending module for illustrating
The schematic diagram of letter system.
Host apparatus may include being encoded to the digital bit of host apparatus for digital serial communication and generating pulse
Voltage Vline, and the pulse voltage is sent to the digital sending module 100 of client terminal device.Client terminal device may include pair
The pulse voltage Vline for transmitting digital sending module 100 is decoded to be supplied to the digital received module of client terminal device
200。
In order to help to understand the present invention, illustrating host apparatus includes digital sending module 100, client terminal device packet
The case where including digital received module 200.But host apparatus and client terminal device include digital sending module 100 and digital received
The mode of module 200 is not limited to this.As described above, when client terminal device transmits data to host apparatus, client terminal device
It may include digital sending module 100, host apparatus may include digital received module 200.
Host apparatus and client terminal device be not merely with one-way communication but also in the way of mutual half-duplex operation
(Half-duplex), two-way communication is executed.
When host apparatus 10 and client terminal device 20 carry out two-way communication, host apparatus 10 and client terminal device 20 can be wrapped
Include digital transmitting and receiving module.
Again, referring to Fig. 2, the number of the digital sending module 100 and another embodiment that illustrate the embodiment of the present invention is connect
Receive module 200.
Numerical data is decoded as pulse voltage Vline and is transmitted to digital received module 200 by digital sending module 100.
Above-mentioned pulse voltage Vline can be sharp during generating the first output signal and the second output signal of aftermentioned comparator
With.The method that digital 100 pulse voltage Vline of sending module is decoded will be aftermentioned.
Digital received module 200 receives pulse voltage Vline from digital sending module 100, will by ac-coupled circuit
Above-mentioned received pulse voltage Vline is transformed to analog signal.Above-mentioned analog signal can be exported by the response of multiple waveforms.It will be defeated
Analog signal out is input to comparator, produces the digital bit of the output signal based on above-mentioned comparator.
Digital received module 200 utilizes pulse voltage Vline, encodes to the output signal exported from comparator,
And restore the numerical data Tx_data for being used for host apparatus.The numerical data Rx_data of recovery can pass through the number of host apparatus 10
It provides according to input terminal to host apparatus.
Fig. 3 is the circuit for illustrating the communication mode using the AC coupled for being suitable for the invention several embodiments
Figure.
As shown in figure 3, if electric signal passes through the communication between transmitting terminal (Transmitter) and receiving end (Receiver)
Link (Communication link) sends to receiving end side, then can confirm the input unit in receiving end (Receiver)
Point node input pulse voltage Vline, the pulse voltage Vline of above-mentioned input, which is applied to, exchanges coupling including capacitor and resistance
Close circuit.For example, above-mentioned ac-coupled circuit can be the circuit structure of HPF (High Pass Filter) form.On at this point,
The cutoff frequency for stating ac-coupled circuit may be defined as.Therefore, in the electric signal of above-mentioned transmitting terminal, frequency higher than Fc at
Point, it is filtered by Vrx, is output to the output node of receiving end (Receiver), block the low frequency of above-mentioned pulse voltage Vline
Rate ingredient.
Fig. 4 is the timing diagram of the output voltage for illustrating to export in ac-coupled circuit.
The serial communication mode being applicable in the present invention can utilize AC coupled.As shown in figure 4, being mentioned in t1, t2, t3 time
Edge (edge) ingredient of data taken signal variation can restore data using the marginal element of extraction.Referring to Fig. 4, area can be confirmed
The pulse voltage Vline and output voltage Vrx of time point t1, t2, t3 of the time T bit (Tbit) of 1 bit of divided data are illustrated
In timing diagram.In the marginal element of above-mentioned t1, t2, t3 display data signal variation.For example, if assuming the time span ratio of Tbit
The time constant (τ=RC) of ac-coupled circuit is sufficiently big, then the output of the ac-coupled circuit of marginal portion (t1, t2, t3)
Voltage Vrx incude the marginal portion of above-mentioned pulse voltage Vline as a result, output voltage Vrx steeply rises, according to above-mentioned exchange
The time constant of coupling circuit converges to bias voltage Vrx_bias again.As described above, in t1, t2, t3, that is, sensed data
(LTH, the Low-To-High) from low to high of conversion timing sequence (Data transition timing) or from low to high (HTL,
High-To-Low), it is used in recovery data.
Fig. 5 is the circuit for illustrating the communication system using the AC coupled for being suitable for the invention several embodiments
Figure.
Referring to Fig. 5, the circuit diagram adopted in the serial communication mode using AC coupled can be confirmed.Transmitting terminal
It (Transmitter) may include current source Itx, switch and load resistance Rtx.Above-mentioned load resistance Rtx, as shown in figure 5, can have
The standby node between the input terminal of the communication link and ac-coupled circuit that are located at the side receiving end (Reciever), but may be used also
Have be located at the side transmitting terminal (Transmitter) current source Itx and communication link (Communication link) it
Between node (not shown).
In the case where the signal of the above-mentioned transmitting terminal side (Transmitter) transmission digital bit 1, above-mentioned switch quilt
Short circuit, the above-mentioned load resistance of current direction of above-mentioned current source Itx, transmit digital bit 0 signal in the case where, above-mentioned switch
It is opened, prevents the current direction load resistance Rtx of current source Itx.Therefore, the pulse voltage Vline of above-mentioned communication link
Swinging (swing) voltage can be defined by swing voltage Vswing=current source Itx* load resistance Rtx.At this point, pulse voltage
The waveform variation of Vline is exported by ac-coupled circuit as output voltage Vrx.
Fig. 6 is the timing diagram for illustrating the digital communication of the AC coupled using several embodiments of the present invention.
If assuming the time span of Tbit situation sufficiently bigger than the time constant of ac-coupled circuit, above-mentioned output
Voltage Vrx can be in the above-mentioned section Tbit, and establishing (settling) is bias voltage Vrx_bias.Above-mentioned Tbit censures a number
It is believed that number unit interval that can be incuded.Also, above-mentioned output voltage Vrx is utilized, when transmitting margin signal, arbitrary electricity can be used
It presses gain amplifier (Optional Gain Amplifier).
Above-mentioned output voltage Vrx can input the input terminal in 2 comparators (Comparator).Suitably set above-mentioned 2
The the first reference voltage Vref1 and the second reference voltage Vref2 of comparator, first comparator can pulse voltage of reaction Vline
HTL.When above-mentioned pulse voltage Vline be HTL when, it is meant that data from 0 be transformed to 1 moment.Second comparator can incude arteries and veins
Rush the LTH of voltage Vline.When above-mentioned pulse voltage Vline be LTH when, it is meant that data from 1 be transformed to 0 moment.Institute as above
It states, due to that can be converted by the 0- > 1 of multiple comparator detection datas transformation and 1- > 0, according to later testing result, utilizes
Logic appropriate produces a variety of digital power signal Rx_data by bit-detector (SRFF).
On the other hand, assume that the time span of Tbit is sufficiently bigger than the time constant of ac-coupled circuit in Fig. 6
Situation, but be actually difficult to set the time constant of above-mentioned ac-coupled circuit and the time relationship of Tbit and based on this relationship
Reference voltage Vref1, Vref2 of comparator.The problem of thus occurring is described in detail in the explanation of Fig. 7 below to Fig. 8.
Fig. 7 to Fig. 8 is for illustrating in the digital communication using the AC coupled for being suitable for the invention several embodiments
The timing diagram of the mistake of generation.
Fig. 7 is the timing for indicating the time very hour problem of time constant ratio Tbit of ac-coupled circuit
Figure.In this case, since the time constant of ac-coupled circuit is very small, the change amount signal of output voltage Vrx is small
In reference voltage Vref1, Vref2 of comparator, comparator does not react, and can finally confirm that digital signal Rx_data is not exported.
On the other hand, in order to solve the problems, such as to illustrate referring to Fig. 7, the time constant of ac-coupled circuit can be set as
Value more higher than Tbit.But the time constant ratio Tbit of above-mentioned AC coupled it is very high when there arises a problem that.This is by reference
Fig. 8 is as described below.
Fig. 8 is to indicate the problem when time constant of ac-coupled circuit is very big compared with the time span of Tbit
Timing diagram.In this case, the change amount signal of output voltage Vrx is sufficiently compared with reference voltage Vref1, Vref2 of comparator
Greatly, in signal intensity time t1 originally, output signal can normally be detected by comparator, but the time of ac-coupled circuit
Constant is more than the time span of Tbit, and during Tbit, output voltage Vrx is not established as bias voltage Vrx_bias.Therefore, directly
To t2, t3, output signal (comparator1_Out, comparator2_Out) can detect reluctantly, but after t 4, it can be true
Recognize output signal not detected normally.It says again, since the time constant of ac-coupled circuit is big, output voltage Vrx is in Tbit
Time span during cannot establish, the average voltage of output voltage Vrx is influenced by pervious data pattern and is slowly occurred
Variation, therefore the situation in the reference voltage that can not react on fixed comparator.In this case, output voltage Vrx
The variation of average voltage can be different according to the structure of data pattern.
In several embodiments of the invention, it as illustrated referring to Fig. 7 to Fig. 8, to propose that AC coupled electricity can be automatically adjusted
The time constant on road, the time span of Tbit and based on this comparator reference voltage Vref1, Vref2 correlativity
Novel circuit structure.
Fig. 9 is the figure for illustrating the digital received module 21 of one embodiment of the invention.But this is only intended to realize this
The preferred embodiment of the purpose of invention, it is of course possible to as needed, additional or deletion part-structure.Hereinafter, referring to Fig. 9, carefully
Illustrate the structure and operating of the digital received module 21 of the present embodiment.
The digital received module 21 of the present embodiment may include voltage follower circuit 201, filtering voltage output section 203, benchmark
Voltage generating unit 205, comparator 207, bit-detector 209.
Voltage follower circuit 201 will be based on passing through communication link (communication in transmitting terminal by AC coupled
Link) the output voltage Vrx of the signal transmitted, is output to output node 202.For example, voltage follower circuit 201 can be exchange
Coupling circuit.Specifically, above-mentioned ac-coupled circuit is also possible to by execution high-pass filter (HPF, High Pass
Filter the circuit diagram that the device of function) is constituted.Therefore, in above-mentioned transmitting terminal, exportable only includes being based on passing through communication chain
The output voltage Vrx of the radio-frequency component of the voltage of the signal of road transmission.
Filtering voltage output section 203 receives above-mentioned output voltage Vrx, incudes the average voltage of above-mentioned output voltage Vrx
Variation, its average value is exported as filtering voltage Vrx_filtered.Above-mentioned filtering voltage Vrx_filtered can be with
Time and changed a reference value.Changed filtering voltage Vrx_filtered, which can become, determines benchmark described below
The benchmark of voltage.Said reference voltage is carried out aftermentioned.
Reference voltage generating unit 205 is based on above-mentioned filtering voltage Vrx_filtered, generates the benchmark for being supplied to comparator
Voltage Vref1, Vref2.Therefore, reference voltage Vref1, the Vref2 and previous base generated in reference voltage generating unit 205
Quasi- voltage (normal voltage) is differently equivalent to the time and changed voltage rather than the voltage of fixation.This is because
Track the variation of the changed filtering voltage Vrx_filtered with the time, said reference voltage Vref1, Vref2
It changes with the time.As a result, when the time span of the time constant ratio T bit of ac-coupled circuit is very big or small
When, it proposes new filtering voltage Vrx_filtered, has the effect of as completely set up above-mentioned output voltage Vrx.
Comparator 207 to the above-mentioned output voltage Vrx and reference voltage Vref1 inputted by the input terminal of comparator,
Vref2 is compared, and exports output signal (comparator1_Out, comparator2_ based on above-mentioned comparison result
Out).According to the type of above-mentioned output signal, the exportable digital bit 0 or 1 in bit-detector.
In one embodiment, digital received module 21 can include: voltage follower circuit 201 will be based on passing through communication link
The second voltage Vrx of output voltage of the received first voltage Vline for receiving signal Tx_data as ac-coupled circuit,
It is output to output node 202；Filtering voltage output section 203 receives second voltage Vrx from output node 202, and output is used as second
The filtering voltage Vrx_filtered of the average value of voltage Vrx；Reference voltage generating unit 205, to from filtering voltage output section 203
The filtering voltage Vrx_filtered output correction of output is the reference voltage Vref for being equivalent to offset voltage；Comparator 207, it is right
Said reference voltage Vref and above-mentioned second voltage Vrx are compared, and output is based on said reference voltage Vref and above-mentioned second
The output signal (comparator_Out) of the comparison result of voltage Vrx；Bit-detector 209, according to above-mentioned output signal
(comparator_Out), the bit Rx_data of output digit signals is converted to.In this case, filtering voltage output section 203
Above-mentioned filtering voltage Vrx_filtered variation can be traced, be even from based on above-mentioned filtering voltage Vrx_filtered correction
It is equivalent to the reference voltage Vref of offset voltage, the shake as distorted signals occurs, is also correctly relatively input to comparator 207
Each voltage, thus have the effect of according to the exportable correct digital signal of above-mentioned comparison result.
In one embodiment, voltage follower circuit 201 utilizes AC coupled, can be using above-mentioned first voltage Vline as arteries and veins
The second voltage Vrx for rushing response, is output to output node 202.It is clear if exporting impulse response (Impulse reponse)
The maximum value or minimum value of second voltage Vrx are exported, therefore the distorted signals because of caused by failure can be reduced, as a result, comparator
207 exportable correct output signals.Also, it shakes even if as described above, also exportable correct digital signal.
In one embodiment, voltage follower circuit 201 is HPF (High Pass Filter), can be by above-mentioned first voltage
Radio-frequency component be output to above-mentioned output node as second voltage.At this point, the cutoff frequency of passband is as determined, only above-mentioned the
High frequency content can just be transmitted as above-mentioned second voltage Vrx in the ingredient of one voltage.
Carefully illustrate that comparator 207 is compared above-mentioned output voltage Vrx and said reference voltage Vref1, Vref2 and
The process of output signal output.This will be referring to illustrating as illustrated in the timing diagram of fig. 10.
For convenience of explanation, in as illustrated in the timing diagram of fig. 10, the section of t2 to t3 is illustrated.Comparator 207 is logical
Cross input terminal receive output voltage Vrx's as a result, can confirm that above-mentioned output voltage Vrx is sharply increased in the section of t2 to t3 and
Slowly reduce.At this point, comparator 207 incudes above-mentioned output voltage Vrx via in the boundary line of the second reference voltage Vref2
First crosspoint A and be detached from, can be in the first crosspoint A to the second crosspoint B then the case where restore via the second crosspoint B
Between opportunity generate output signal (comparator2_Out).Only, in above-mentioned example, although the description of sense be detached from
Crosspoint and the case where restore, and generate the process of output signal (comparator2_Out), but also to notice, incude above-mentioned
Output voltage Vrx reaches the second reference voltage Vref2, and the case where generate output signal (comparator2_Out).
The boundary line of said reference voltage, it is different from Fig. 5 to Fig. 7, can have inclined tracing pattern.This expression, filtered electrical
Vrx_filtered's as a result, generating changed with the time new establish line, base to pressure 203 tracking filter voltage of output section
Line is established in above-mentioned generation, reference voltage can be supplied to above-mentioned comparator.Therefore, it is possible to provide can be with the limited Tbit time
The benchmark electricity that the filtering voltage Vrx_filtered and output voltage Vrx that output voltage Vrx is thoroughly established in length are compared
Vref1, Vref2 are pressed, even if the distorted signals because of caused by shake occurs, can also export correct digital signal.
Bit-detector 209 can be converted to the bit of output digit signals according to above-mentioned output signal.For example, bit is examined
Surveying device 209 can be the logic circuit of SRFF function.In one embodiment, bit-detector 209 can pass through induction above-mentioned first
Output signal (comparator1_Out) exports digital bit 1, and can pass through above-mentioned second output signal of induction
(comparator2_Out) digital bit 0 is exported.
In one embodiment, reference voltage generating unit 205 is based on the above-mentioned filtered electrical exported from filtering voltage output section 203
Vrx_filtered is pressed, the first reference voltage Vref1 and the second reference voltage Vref2, above-mentioned first reference voltage Vref1 is exported
It is that the value for being equivalent to offset voltage Voffset1 is dropped to compared with above-mentioned filtering voltage Vrx_filtered, above-mentioned second benchmark electricity
Pressure Vref2 can be the value for rising to compared with above-mentioned filtering voltage Vrx_filtered and being equivalent to offset voltage Voffset2.
In one embodiment, comparator 207 includes first comparator 217 and the second comparator 227, first comparator 217
Above-mentioned second voltage Vrx is received by the first reversion terminal, above-mentioned first reference voltage is received by the first non-inverted terminal
Vref1's as a result, output first based on above-mentioned first reference voltage Vref1 and the comparison result of above-mentioned second voltage Vrx is defeated
Signal (comparator1_Out) out, above-mentioned second comparator 227 receive above-mentioned second voltage by the second non-inverted terminal
Vrx, and above-mentioned second reference voltage Vref2's as a result, exportable based on above-mentioned second benchmark is received by the second reversion terminal
The second output signal (comparator2_Out) of the comparison result of voltage Vref2 and above-mentioned second voltage Vrx.
Finally, for digital received module as shown in Figure 9, the time constant of ac-coupled circuit and Tbit time
Length comparatively mismatch, in the case that output voltage Vrx cannot correctly establish as bias voltage Vrx_bias, can mention
The new reference voltage that the voltage inputted is compared for comparator.Therefore, digital signal can correctly be detected.Overcome above-mentioned friendship
The time constant for flowing coupling circuit is too small and the case where can not detect output signal while can solve above-mentioned ac-coupled circuit
Time constant it is too big when error detection above-mentioned output signal the problem of.
Figure 11 is an embodiment of the reference voltage generating unit for illustrating to adopt in several embodiments of the invention
Figure.But this is only intended to the preferred embodiment achieved the object of the present invention, it is of course possible to as needed, additional or deletion portion
Separation structure.Hereinafter, referring to Fig.1 1, the structure and operating of the reference voltage generating unit of the present embodiment are illustrated.
Referring to Fig.1 1, the reference voltage generating unit of the present embodiment is constituted according to by N-type metal oxide semiconductor transistor
Source follower (Source-follower) service performance, said reference voltage Vref1, Vref2 may be output as than filtering
The low value for the critical voltage of above-mentioned N-type metal oxide semiconductor transistor or so of voltage Vrx_filtered.Due to tracking
The variation of the filtering voltage Vrx_filtered exported from filtering voltage output section 203, therefore said reference voltage Vref1 also can
It is down to the critical voltage for being equivalent to N-type metal oxide semiconductor transistor in above-mentioned filtering voltage Vrx_filtered output
Reference voltage.Also, the design of change said reference voltage generating unit is also noticed, it is exportable to be up to equivalent to above-mentioned N-type
The voltage of the critical voltage of metal oxide semiconductor transistor.
In one embodiment, reference voltage generating unit 205 includes N-type metal oxide semiconductor transistor, exportable to incite somebody to action
Above-mentioned filtering voltage Vrx_filtered rises or falls to being equivalent to the critical of above-mentioned N-type metal oxide semiconductor transistor
Reference voltage Vref1, Vref2 of voltage.Offset voltage Voffset1, Voffset2 can according to the size of above-mentioned critical voltage and
Setting.Using the service performance of the Source-follower of N-type metal oxide semiconductor transistor, thus having can be reduced
The effect of the error of reference voltage Vref1, Vref2 value.
Figure 12 is another implementation of the reference voltage generating unit for illustrating to adopt in several embodiments of the invention
The figure of example.But this is only intended to the preferred embodiment achieved the object of the present invention, it is of course possible to as needed, additional or deletion
Part-structure.Hereinafter, referring to Fig.1 2, the structure and operating of the reference voltage generating unit of the present embodiment are illustrated.
Referring to Fig.1 2, the reference voltage generating unit of the present embodiment may include P type metal oxide semiconductor transistor, feedback
The operational amplifier and resistive divider (Power divider) of structure.According to structure as shown in figure 12, in filtering voltage
Vrx_filtered produces reference voltage Vref1, Vref2 of low or a height of defined offset voltage or so.
In one embodiment, reference voltage generating unit 205 includes that P type metal oxide semiconductor transistor and resistance distribute
Above-mentioned filtering voltage Vrx_filtered is applied to aforementioned p-type metal oxide semiconductor transistor, utilizes above-mentioned resistance by device
Distributor can export the above-mentioned filtering voltage Vrx_filtered of above-mentioned application for said reference voltage.This utilizes aforementioned p-type
The service performance and resistive divider of metal oxide semiconductor transistor, can arbitrarily adjust said reference voltage Vref1,
The value of Vref2.
In one embodiment, it is applied to the above-mentioned filtering voltage Vrx_ of aforementioned p-type metal oxide semiconductor transistor
Filtered can be the voltage that the grid of aforementioned p-type metal oxide semiconductor transistor is input to by amplifier.
Figure 13 is the figure for illustrating the digital received module 22 of another embodiment of the present invention.But this is only intended to reality
The preferred embodiment of the existing purpose of the present invention, it is of course possible to as needed, additional or deletion part-structure.Hereinafter, to this implementation
The structure of the digital received module 22 of example and operating are illustrated.
The digital received module 22 of the present embodiment may include voltage follower circuit 201, filtering voltage output section 203, compare
Device 208, bit-detector 209.For the knot of voltage follower circuit 201, filtering voltage output section 203 and bit-detector 209
The explanation of structure and the explanation of operating referring to above-mentioned Fig. 9.
On the other hand, the digital received module 21 as shown in Figure 9 of digital received module 22 has filtering as shown in fig. 13 that
Voltage output portion 203, it is identical in the viewpoint of the variation of tracking filter voltage Vrx_filtered.However, the present embodiment
Digital received module 22 does not have reference voltage generating unit separately, can apply defined offset voltage in comparator 208 itself, by
This generates reference voltage Vref1, Vref2.
Referring to Fig.1 3, confirm diagram can be inputted in first comparator 218 and the second comparator 228 as defined in imbalance electricity
The structure of pressure.This is because reference voltage is additionally generated in each comparator, even if generating to filtering voltage Vrx_filtered
In the case where the maximum value of output voltage Vrx and the deviation of minimum value, it may have can correctly incude for the defeated of output comparator
The effect of the signal of signal out.
In one embodiment, digital received module 22 can include: voltage follower circuit 201 will be based on passing through communication link
The received first voltage Vline for receiving signal is output to output node 202 as second voltage Vrx；Filtering voltage output section
203, above-mentioned second voltage Vrx is received from output node 202, exports the filtering voltage of the average value as above-mentioned second voltage
Vrx_filtered；Comparator 208 inputs the above-mentioned filtering voltage Vrx_filtered exported from filtering voltage output section 203
Correction is to be equivalent to the reference voltage Vref of offset voltage Voffset, and export based on said reference voltage Vref and above-mentioned the
The output signal of the comparison result of two voltage Vrx；Bit-detector 209 is converted to output number letter according to above-mentioned output signal
Number bit.Therefore, even if generating the maximum value of output voltage Vrx and the deviation of minimum value to filtering voltage Vrx_filtered
In the case where, it may have it can correctly incude the signal of the output signal for output comparator, and exportable correct data letter
Number effect.
In one embodiment, comparator 208 includes first comparator 218 and the second comparator 228, first comparator 218
There is the first imbalance power supply in the first non-inverted terminal, according to above-mentioned first imbalance power supply, input, which is used as to drop to, is equivalent to mistake
Adjust voltage value the first reference voltage Vref1, by first reversion terminal input above-mentioned second voltage Vrx's as a result, output
The first output signal based on above-mentioned first reference voltage Vref1 Yu the comparison result of above-mentioned second voltage Vrx, the second comparator
228, which invert terminal second, has the second imbalance power supply, and according to above-mentioned second imbalance power supply, input, which is used as to rise to, is equivalent to mistake
The the second reference voltage Vref2 for adjusting the value of voltage inputs above-mentioned second voltage Vrx's as a result, can by the second non-inverted terminal
Export the second output signal based on above-mentioned second reference voltage Vref2 Yu the comparison result of above-mentioned second voltage Vrx.In this reality
It applies in example, due to having 2 comparators, distinguishes data bit 0 or 1 and export, therefore there is exportable correct data-signal
Effect.
Figure 14 is the figure of the comparator for illustrating to adopt in several embodiments of the invention.But this is only intended to
The preferred embodiment achieved the object of the present invention, it is of course possible to as needed, additional or deletion part-structure.Hereinafter, to this reality
The structure and operating for applying the comparator of example are illustrated.
Referring to Fig.1 4, the comparator of the present embodiment is designed by common differential (Differential) input structure, can
Including N-type metal oxide semiconductor transistor M1 and N-type metal oxide semiconductor transistor M2.At this point, above-mentioned comparator
Differently design the intensity of above-mentioned N-type metal oxide semiconductor transistor M1 and N-type metal oxide semiconductor transistor M2
(strength), thus there can be offset voltage.That is, working as above-mentioned N-type metal oxide semiconductor transistor M1 and N-type metal oxygen
When the length (length) of compound semiconductor transistor M2 is identical, if width (width) is different, input imbalance electricity can be generated
Pressure.
For example, if the width of above-mentioned N-type metal oxide semiconductor transistor M2 is greater than above-mentioned N-type metal oxide half
The width of conductor transistor M1, then anode (positive) input voltage In+ is compared with cathode (negative) input voltage In-
It is higher by regulation offset voltage or more, the variation that could be exported.In such a way, it may make up with defined offset voltage
Comparator.Therefore, it even if there is no additional reference voltage generating unit according to the comparator of the present embodiment, can also obtain required
Imbalance power supply.
In one embodiment, above-mentioned comparator includes the first N-type metal oxide semiconductor transistor and the second N-type metal
Oxide semi conductor transistor, said reference voltage can be according to the width of above-mentioned first N-type metal oxide semiconductor transistor
(width) and the difference of the width (width) of above-mentioned second N-type metal oxide semiconductor transistor, exportable as will be above-mentioned
The voltage of biasing rises or falls to the reference voltage for the value for being equivalent to offset voltage.
Figure 15 is the mistake for generating in illustrating to be suitable for the invention the digital communication of the AC coupled of several embodiments
Timing diagram accidentally.
Other than the shake (jitter) generated in the serial communication system illustrated referring to Fig. 7 to Fig. 8, also according to logical
Believe the physical structure of link, it may occur that failure (glitch).
As shown in figure 15, lead to communication link when changing with the Tx_data that transmits from transmitting terminal (Transmitter)
When the voltage of (communication link) sharply changes, there are problems that breaking down on output voltage Vrx.This can be by posting
Raw inductance ingredient etc. occurs in power supply, grounding parts (Ground) or communication link itself.At this point, the failure of above-mentioned generation, such as schemes
Shown in 15, it will lead to when extreme case that there are problems in received data.In t1, according to first comparator
(comparator1) incude HTL signal, when extreme failure occurring at this time, in t2, the second comparator (comparator2)
It is operated, thus it is possible that changing data on wrong opportunity.Similarly, in t3, the second comparator (comparator2) induction
LTH signal, and then in t4, first comparator (comparator1) can incude wrong data because of caused by failure.
On the other hand, in digital received module described below, the letter because of caused by failure as described above is solved
Number distortion, and will propose that above-mentioned bit-detector is properly received the novel circuit structure of output signal.
Figure 16 is the figure for illustrating the digital received module of another embodiment of the present invention.But this is only intended to realize
The preferred embodiment of the purpose of the present invention, it is of course possible to as needed, additional or deletion part-structure.
Referring to Fig.1 6, the structure and operating of the digital received module 23 of the present embodiment are illustrated.As shown in figure 16, than
It is mobile to exposure mask 206 compared with the output signal of device.At this point, can be blocked during stipulated time Tm via the output signal of exposure mask 206
The output signal of the comparator of opposite direction is transmitted to bit-detector.Exposure mask 206 may include the ratio that can incude mutually different direction
Compared with the first exposure mask 216 and the second exposure mask 226 of the output signal of device.First exposure mask 216 makes the first of first comparator to export letter
Number via and the second output signal of the second comparator can be blocked, the second exposure mask 226 of the second comparator makes the second output signal
Via, and can first comparator the first output signal.
In one embodiment, digital received module 23 includes: voltage follower circuit, will be based on received by communication link
The first voltage Vline for receiving signal is output to output node as second voltage Vrx；First comparator passes through the first reversion
Terminal receives above-mentioned second voltage Vrx, and the knot of the first set reference voltage Vset1 can be received by the first non-inverted terminal
Fruit exports the first output signal based on above-mentioned first reference voltage Vset1 Yu the comparison result of above-mentioned second voltage Vrx；The
Two comparators receive above-mentioned second voltage Vrx by the second non-inverted terminal, receive set second by the second reversion terminal
Reference voltage Vset2's as a result, output the comparison result based on above-mentioned second reference voltage Vset2 Yu above-mentioned second voltage Vrx
The second output signal；First exposure mask 226 in response to the induction of above-mentioned first output signal, blocks above-mentioned the in first interval
One output signal is sent to above-mentioned bit-detector, and above-mentioned second output signal is blocked to be sent to above-mentioned bit-detector；The
Two exposure masks 226, the second interval after above-mentioned first interval terminates are blocked in response to the induction of above-mentioned second output signal
Above-mentioned second output signal is sent to above-mentioned bit-detector, and above-mentioned first output signal is blocked to be sent to above-mentioned bit-detection
Device.First interval and second interval in the present embodiment and several embodiments of following embodiment may imply that output digital bit
Time interval.For example, Tbit can become the unit in above-mentioned section, according to setting, masking period Tm can become above-mentioned section
Unit.Also, it notices, according to setting, may be set to a variety of time spans.
The digital received module of several embodiments of the present invention can include: the first exposure mask 216, in first interval, in response to
The induction of above-mentioned first output signal blocks above-mentioned first output signal to be sent to above-mentioned bit-detector, and blocks above-mentioned the
Two output signals are sent to above-mentioned bit-detector；Second exposure mask 226, the second interval after above-mentioned first interval terminates,
In response to the induction of above-mentioned second output signal, above-mentioned second output signal is blocked to be sent to above-mentioned bit-detector, and blocked
Above-mentioned first output signal is sent to above-mentioned bit-detector.
On the other hand, the 9 above-mentioned output signals of explanation are transferred to the specific fortune of bit-detector via exposure mask referring to Fig.1
Turn.Figure 19 is the timing diagram for illustrating the improvement point of the communication of the digital received module using Figure 16 to Figure 18.
Tm is as masking period, it is meant that blocks at least one output signal in first comparator and the second comparator
Time span.In the present embodiment, above-mentioned Tm can be presented as Tm1, Tm2, Tm3.For example, in t1, for the first time by first comparator
Incude HTL signal, by the first output signal of the first exposure mask 216 induction first comparator, plays so that above-mentioned first output letter
It number is transferred to the first exposure mask 216, and the second output signal of the second comparator is blocked to be transferred to bit inspection in stipulated time Tm1
Survey the effect that the mode of device turns on the switch.Therefore, in t2, the second output signal of the second comparator generated by failure is not
It is transferred to above-mentioned bit-detector.Then, in t3, LTH signal is reacted by the second comparator, by the second exposure mask 226 induction the
Second output signal of two comparators plays so that above-mentioned second output signal is transferred to the second exposure mask 226, and blocks the first ratio
The first output signal compared with device is transferred to the effect that the mode of bit-detector turns on the switch in stipulated time Tm2.
Mode as described above is limited in stipulated time Tm, Xiang Fanfang after each comparator generates output signal
To output signal be transferred to bit-detector, be thus actually input to bit-detector and via the of the first exposure mask 216
One mask signal and via the second exposure mask the second mask signal in the case where actually occurring failure not by failure
It influences, therefore above-mentioned bit-detector can be made to generate correct data.The masking period Tm for noticing above-mentioned exposure mask 206 passes through this
The method of the admissible delay circuit of the those of ordinary skill of the technical field of invention (Delay cell) etc. can set a variety of values.
The masking period Tm of above-mentioned exposure mask 206 can be set as being less than data bit time fixed in communication system
Tbit, and it is set greater than the time influenced by failure.In this case, in the section Tbit for generating unit output signal
Correct data are exported, have the effect of can ensure that the operating of stable communication system.
Figure 17 to Figure 18 censures the circuit structure that the digital received module shown in above-mentioned Fig. 9 and Figure 13 also has exposure mask.
As described above, digital received module shown in above-mentioned Fig. 9 and Figure 13 can solve in serial communication system as distorted signals
Shake.At this point, also there is exposure mask in several of the above embodiments where referring to Fig. 9 and Figure 13, the failure other than shake can be solved
The problem of distorted signals.
More than, referring to attached drawing, illustrate the embodiment of the present invention, but the ordinary skill people of technical field belonging to the present invention
Member should be appreciated that in the case where the present invention does not change its technical idea or required feature can be real with a variety of specific forms
It applies.So be on should being appreciated that embodiments described above in all respects it is illustrative, without being restrictive.
Claims (16)
1. a kind of digital received module characterized by comprising
Voltage follower circuit is output to based on the first voltage by the received reception signal of communication link as second voltage
Output node；
Filtering voltage output section receives above-mentioned second voltage from above-mentioned output node, exports being averaged as above-mentioned second voltage
The filtering voltage of value；
Reference voltage generating unit is equivalent to mistake to the above-mentioned filtering voltage output correction exported from above-mentioned filtering voltage output section
Adjust the reference voltage of voltage；
Comparator is compared said reference voltage and above-mentioned second voltage, and output is based on said reference voltage and above-mentioned the
The output signal of the comparison result of two voltages；And
Bit-detector is converted to the bit of output digit signals according to above-mentioned output signal.
2. digital received module according to claim 1, which is characterized in that above-mentioned voltage follower circuit utilizes exchange coupling
It closes, is output to above-mentioned output node for above-mentioned first voltage as the second voltage of impulse response.
3. digital received module according to claim 1, which is characterized in that above-mentioned voltage follower circuit is by above-mentioned first
The radio-frequency component of voltage is output to the high-pass filter of above-mentioned output node as second voltage.
4. digital received module according to claim 1, which is characterized in that the output of said reference voltage generating unit will be above-mentioned
Filtering voltage rises or falls to being equivalent in said reference voltage generating unit included N-type metal-oxide semiconductor (MOS) crystal
The reference voltage of the critical voltage of pipe.
5. digital received module according to claim 1, which is characterized in that said reference voltage generating unit includes p-type gold
Belong to oxide semi conductor transistor and resistive divider, above-mentioned filtering voltage is applied to aforementioned p-type metal-oxide semiconductor (MOS)
Transistor is exported the above-mentioned filtering voltage of above-mentioned application for said reference voltage using above-mentioned resistive divider.
6. digital received module according to claim 5, which is characterized in that be applied to aforementioned p-type metal oxide and partly lead
The above-mentioned filtering voltage of body transistor is the grid that aforementioned p-type metal oxide semiconductor transistor is input to by amplifier
Voltage.
7. digital received module according to claim 1, which is characterized in that said reference voltage generating unit is based on from above-mentioned
The above-mentioned filtering voltage of filtering voltage output section output, exports the first reference voltage and the second reference voltage, above-mentioned first benchmark
Voltage is that the value for being equivalent to offset voltage is dropped to than above-mentioned filtering voltage, and above-mentioned second reference voltage is than above-mentioned filtering voltage
Rise to the value for being equivalent to offset voltage.
8. digital received module according to claim 7, which is characterized in that
Above-mentioned comparator includes first comparator and the second comparator,
Above-mentioned first comparator receives above-mentioned second voltage by the first reversion terminal, is received by the first non-inverted terminal above-mentioned
First reference voltage is exported based on above-mentioned first reference voltage with the first of the comparison result of above-mentioned second voltage as a result, exporting
Signal,
Above-mentioned second comparator receives above-mentioned second voltage by the second non-inverted terminal, is received by the second reversion terminal above-mentioned
Second reference voltage is exported based on above-mentioned second reference voltage with the second of the comparison result of above-mentioned second voltage as a result, exporting
Signal.
9. digital received module according to claim 8, which is characterized in that above-mentioned bit-detector is by incuding above-mentioned the
One output signal exports digital bit 1, by above-mentioned second output signal exports digital bit 0.
10. digital received module according to claim 8, which is characterized in that further include:
First exposure mask blocks above-mentioned first output signal to send in first interval in response to the induction of above-mentioned first output signal
To above-mentioned bit-detector, and above-mentioned second output signal is blocked to be sent to above-mentioned bit-detector；And
Second exposure mask, the second interval after above-mentioned first interval terminates, in response to the induction of above-mentioned second output signal, resistance
Above-mentioned second output signal of breaking is sent to above-mentioned bit-detector, and above-mentioned first output signal is blocked to be sent to above-mentioned bit inspection
Survey device.
11. a kind of digital received module characterized by comprising
Voltage follower circuit is output to based on the first voltage by the received reception signal of communication link as second voltage
Output node；
Filtering voltage output section receives above-mentioned second voltage from above-mentioned output node, and exports as the flat of above-mentioned second voltage
The filtering voltage of mean value；
Comparator, inputting the above-mentioned filtering voltage correction exported from above-mentioned filtering voltage output section is the base for being equivalent to offset voltage
Quasi- voltage, and export the output signal of the comparison result based on said reference voltage and above-mentioned second voltage；And
Bit-detector is converted to the bit of output digit signals according to above-mentioned output signal.
12. digital received module according to claim 11, which is characterized in that
Above-mentioned comparator includes the first N-type metal oxide semiconductor transistor and the second N-type metal-oxide semiconductor (MOS) crystal
Pipe,
Said reference voltage is according to the width of above-mentioned first N-type metal oxide semiconductor transistor and above-mentioned second N-type metal
The width of oxide semi conductor transistor is poor, and output rises or falls as by the voltage of above-mentioned biasing to being equivalent to offset voltage
Value reference voltage.
13. digital received module according to claim 11, which is characterized in that
Above-mentioned comparator includes first comparator and the second comparator,
Above-mentioned first comparator has the first imbalance power supply in the first non-inverted terminal, according to above-mentioned first imbalance power supply, input
As the first reference voltage for dropping to the value for being equivalent to offset voltage, above-mentioned second voltage is inputted by the first reversion terminal
As a result, first output signal of the output based on above-mentioned first reference voltage Yu the comparison result of above-mentioned second voltage,
Above-mentioned second comparator has the second imbalance power supply in the second reversion terminal, and according to above-mentioned second imbalance power supply, input is made
For the second reference voltage for rising to the value for being equivalent to offset voltage, above-mentioned second voltage is inputted by the second non-inverted terminal
As a result, second output signal of the output based on above-mentioned second reference voltage Yu the comparison result of above-mentioned second voltage.
14. digital received module according to claim 13, which is characterized in that above-mentioned bit-detector is above-mentioned by incuding
First output signal exports digital bit 0 by incuding above-mentioned second output signal to export digital bit 1.
15. digital received module according to claim 13, which is characterized in that further include:
First exposure mask blocks above-mentioned first output signal to send in first interval in response to the induction of above-mentioned first output signal
To above-mentioned bit-detector, and above-mentioned second output signal is blocked to be sent to above-mentioned bit-detector；And
Second exposure mask, the second interval after above-mentioned first interval terminates, in response to the induction of above-mentioned second output signal, resistance
Above-mentioned second output signal of breaking is sent to above-mentioned bit-detector, and above-mentioned first output signal is blocked to be sent to above-mentioned bit inspection
Survey device.
16. a kind of digital received module characterized by comprising
Voltage follower circuit is output to based on the first voltage by the received reception signal of communication link as second voltage
Output node；
First comparator receives above-mentioned second voltage by the first reversion terminal, is received by the first non-inverted terminal set
First normal voltage is exported based on above-mentioned first normal voltage with the first of the comparison result of above-mentioned second voltage as a result, exporting
Signal；
Second comparator receives above-mentioned second voltage by the second non-inverted terminal, is received by the second reversion terminal set
Second normal voltage is exported based on above-mentioned second normal voltage with the second of the comparison result of above-mentioned second voltage as a result, exporting
Signal；
First exposure mask blocks above-mentioned first output signal to send in first interval in response to the induction of above-mentioned first output signal
To above-mentioned bit-detector, and above-mentioned second output signal is blocked to be sent to above-mentioned bit-detector；
Second interval after above-mentioned first interval terminates blocks above-mentioned the in response to the induction of above-mentioned second output signal
Two output signals are sent to above-mentioned bit-detector, and above-mentioned first output signal is blocked to be sent to above-mentioned bit-detector.
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Citations (5)
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|---|---|---|---|---|
| US20040233090A1 (en) * | 2003-05-22 | 2004-11-25 | Oki Electric Industry Co., Ltd. | Demodulating circuit and optical receiving circuit |
| US20060158229A1 (en) * | 2005-01-18 | 2006-07-20 | International Business Machines Corporation | Improved signal detector for high-speed serdes |
| US20080205907A1 (en) * | 2007-02-28 | 2008-08-28 | Gil Su Kim | Optical receiver, optical audio apparatus, optical communication apparatus and optical reception method |
| US20100156635A1 (en) * | 2007-11-09 | 2010-06-24 | Matthew Douglas Brown | Signal Level Detection Method |
| CN106130557A (en) * | 2016-06-20 | 2016-11-16 | 中国电子科技集团公司第二十四研究所 | A kind of comparator imbalance voltage self-correcting circuit |
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| KR100250436B1 (en) | 1997-12-03 | 2000-04-01 | 정선종 | Method and apparatus for detecting sync. signal |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040233090A1 (en) * | 2003-05-22 | 2004-11-25 | Oki Electric Industry Co., Ltd. | Demodulating circuit and optical receiving circuit |
| US20060158229A1 (en) * | 2005-01-18 | 2006-07-20 | International Business Machines Corporation | Improved signal detector for high-speed serdes |
| US20080205907A1 (en) * | 2007-02-28 | 2008-08-28 | Gil Su Kim | Optical receiver, optical audio apparatus, optical communication apparatus and optical reception method |
| US20100156635A1 (en) * | 2007-11-09 | 2010-06-24 | Matthew Douglas Brown | Signal Level Detection Method |
| CN106130557A (en) * | 2016-06-20 | 2016-11-16 | 中国电子科技集团公司第二十四研究所 | A kind of comparator imbalance voltage self-correcting circuit |
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| KR20190078019A (en) | 2019-07-04 |
| KR102008245B1 (en) | 2019-10-21 |
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