CN109962605B - Full-bridge rectifier and self-adaptive adjusting device - Google Patents
Full-bridge rectifier and self-adaptive adjusting device Download PDFInfo
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- CN109962605B CN109962605B CN201711433007.2A CN201711433007A CN109962605B CN 109962605 B CN109962605 B CN 109962605B CN 201711433007 A CN201711433007 A CN 201711433007A CN 109962605 B CN109962605 B CN 109962605B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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Abstract
The invention relates to a self-adaptive adjusting circuit of a full-bridge rectifier, which comprises: a judgment circuit and a configurable delay circuit; the judging circuit is connected with the configurable delay circuit and is used for receiving the driving voltage and the starting signal and outputting a control signal; the configurable delay circuit is used for receiving the control signal and the driving voltage and outputting the delayed driving voltage. The self-adaptive adjusting circuit can accurately control the turn-off of 4 MOSFETs in the full-bridge rectifier, thereby improving the efficiency of the full-bridge rectifier.
Description
Technical Field
The invention relates to a full-bridge rectifier, in particular to a self-adaptive adjusting device of the full-bridge rectifier.
Background
A full bridge rectifier is a commonly used circuit in power management, and its main function is to convert an input ac voltage into a dc voltage. As shown in fig. 1, when the input ac current IAC is positive, the diodes D1 and D3 are turned on to charge the output capacitor C0; when the input ac current IAC is negative, the diodes D2, D4 are turned on to charge the output capacitor C0. Since the diodes have a certain threshold of turn-on voltage, 4 diodes are replaced by 4 MOSFETs M1, M2, M3 and M4 in high current applications.
As shown in fig. 2, the diode does not require special circuit control because it is naturally conductive. But in order to make the conduction behavior of 4 MOSFETs similar to a diode, a comparator is needed to detect the voltage or current of the source and drain of the MOSFET: when the MOSFET generates a current from the source to the drain, the comparator controls the gate voltage of the MOSFET to be high so as to turn on the MOSFET; when the MOSFET generates a current from source to drain close to 0, the comparator controls the gate voltage of the MOSFET to be low to turn off the MOSFET.
Due to the symmetry of the input current, M4 is also inevitably on when M2 is on, and M1 is also inevitably on when M3 is on, so the comparator for controlling M1 and the comparator for controlling M3 are usually multiplexed, and the comparators for controlling M2 and M4 are also multiplexed. Meanwhile, the turn-on and turn-off of the MOSFET are usually determined by two different comparators. As shown in fig. 3, in the initial case, the driving voltage Drv _ LD or Drv _ RD of the 4 MOSFETs is low, and thus the 4 MOSFETs are all in the off state. When the input ac current IAC is positive, current flows from the ACP into the full-bridge rectifier, and flows from the ACN out of the full-bridge rectifier: first, the input current IAC will pass through the substrate diodes of M1 and M3, so the drain voltage of M3 equals the negative diode drop, i.e., -VBE; the comparator Cmp1_ ON detects that the drain voltage of M3 reaches a negative diode drop by comparing the drain voltage of M3 with a threshold VTHON for comparing turn-ON voltage, so that the output is high, Drv _ RD is equal to 1, M3 is turned ON, and the drain voltage is greater than-VBE after turn-ON of M3 because the ON-resistance Rdson of M3 is small; when the IAC current gradually decreases close to 0V, the comparator Cmp1_ OFF detects IAC small enough by comparing the drain voltage of M3 with an OFF-voltage comparison threshold VTHOFF, so that the output low level causes Drv _ RD to be 0 and M3 to be turned OFF.
When the input ac current IAC is negative, current flows from ACN into the full-bridge rectifier and flows from ACP out of the full-bridge rectifier. The operation behaviors of the comparators Cmp2_ ON and Cmp2_ OFF are the same as those of Cmp1_ ON and Cmp1_ OFF when the input alternating current is positive. The timing relationship between the driving voltage Drv _ LD or Drv _ RD of the 4 MOSFETs, the input voltage ACN, ACP, and the input current IAC is shown in fig. 4.
This behavior is typical of a full bridge rectifier, and the efficiency is greatly improved because the MOSFET has a very low on-resistance.
However, the turn-off comparison threshold VTHOFF of the comparator is usually between-1 mV to-10 mV because the turn-on voltage of the MOSFET is reduced due to the small turn-on resistance of the MOSFET, and this requires the comparator to have very high resolution and response speed if the input AC current reaches a frequency of 100KHz to 1 MHz. Moreover, since the bridge rectifier circuit usually flows a large current, the noise has a large influence on the comparator.
For integrated circuit design, it is difficult to design a comparator that requires high resolution, high precision, fast response speed and high signal-to-noise rejection ratio.
Disclosure of Invention
The invention adds an automatically adjustable delay unit on the basis of the original circuit, so that the turn-off comparator of the MOSFET can simultaneously achieve high precision, quick response and high signal noise suppression ratio.
In order to achieve the above object, an aspect of the present invention provides a full-bridge rectifier adaptive adjustment circuit, including: a judgment circuit and a configurable delay circuit; the judging circuit is connected with the configurable delay circuit and is used for receiving the driving voltage and the starting signal and outputting a control signal; the configurable delay circuit is used for receiving the control signal and the driving voltage and outputting the delayed driving voltage.
Preferably, the judgment circuit includes: a current period sampling module, an accumulator and a register; the current period sampling module receives the driving voltage and the starting signal and outputs an accumulated signal; the accumulator receives the accumulation signal and the control signal fed back from the register output to accumulate and sum, and outputs an accumulation result; the register stores the accumulation result output by the accumulator and outputs a control signal to the configurable delay circuit and the accumulator.
Preferably, the current period sampling module specifically includes: the circuit comprises an inverter, a first D trigger, a second D trigger and a delay unit; the inverter receives the driving voltage and outputs the driving voltage to the D end of the first D trigger, the CP end of the first D trigger receives the opening signal, the R end of the first D trigger receives the driving voltage, and the Q end of the first D trigger outputs the D end of the second D trigger; one end of the delay unit receives the output end of the phase inverter, and the other end of the delay unit outputs the output end of the phase inverter to the CP end of the second D trigger.
Preferably, the accumulator is determined to be an n-bit accumulator according to the speed, precision and efficiency of the circuit, and n is a positive integer; and the register comprises n D flip-flops; the CP ends of the n D triggers receive the driving voltage, the D ends receive the accumulation result output by the accumulator, and the control signals are output together through the Q ends; and the D flip-flop may be replaced with an RS flip-flop or a JK flip-flop.
Preferably, the configurable delay circuit is a structure for charging the configurable capacitor array by current, and comprises: the circuit comprises n delay MOS tubes, n capacitors, a current source, a first phase inverter, a second phase inverter, a third phase inverter and a drive MOS tube; the first end of the current source is connected with a power supply VDD, the second end of the current source is connected with the drain electrode of the driving MOS tube, the source electrode of the driving MOS tube is grounded, and a driving signal passes through the first phase inverter and the second phase inverter and is connected with the grid electrode of the driving MOS tube; the drain electrodes of the n delay MOS tubes are connected with the second end of the current source, the grid electrodes of the n delay MOS tubes receive control signals, the source electrode of each MOS tube in the n delay MOS tubes is connected with each of the n capacitors, and the other ends of the n capacitors are grounded; one end of the third inverter is connected with the second end of the current source, and the other end of the third inverter outputs the delayed driving voltage.
Preferably, the capacities of the n capacitors are specifically: the second capacitance is 2 times of the first capacitance, the third capacitance is 4 times of the first capacitance, and so on, the nth capacitance is 2 times of the first capacitancen-1And (4) doubling.
Preferably, the first inverter, the second inverter and the third inverter are replaced with a comparator.
Preferably, the structure of the configurable delay circuit is a structure that the configurable capacitor array is charged by a resistor, or a structure that the capacitor is charged by a configurable current array; the control signal is coded as 8421 code or temperature code.
Preferably, a microprocessor is also included; the microprocessor receives the control signal output by the judgment circuit, controls the control signal through software and outputs the control signal to the configurable delay circuit.
In another aspect, the invention provides a full-bridge rectifier, including any of the above circuits.
The self-adaptive adjusting circuit can accurately control the turn-off of 4 MOSFETs in the full-bridge rectifier, thereby improving the efficiency of the full-bridge rectifier.
Drawings
Fig. 1 is a schematic diagram of a full-bridge rectifier provided in the prior art;
FIG. 2 is a schematic diagram of another prior art full bridge rectifier;
FIG. 3 is a schematic diagram of a full bridge rectifier provided in the prior art;
FIG. 4 is a timing waveform diagram of FIG. 3;
FIG. 5 is a schematic diagram of an adaptive adjustment apparatus for a full bridge rectifier according to an embodiment of the invention;
FIG. 6 is a schematic diagram of the adaptive tuning circuit shown in FIG. 5;
FIG. 7 is a schematic diagram of the determining circuit shown in FIG. 6;
FIG. 8 is a schematic diagram of the configurable delay circuit of FIG. 6;
FIG. 9 is a timing waveform diagram of FIG. 5;
FIG. 10 is a flowchart of a method of the M2, M4 control circuit of FIG. 5;
FIG. 11 is a flowchart of a method for controlling the M1 and M3 circuits of FIG. 5.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Fig. 5 is a schematic diagram of an adaptive adjustment apparatus for a full-bridge rectifier according to an embodiment of the invention.
As shown in fig. 5, the adaptive adjusting circuit delays the falling edges of Drv _ LD and Drv _ RD by a delay (td1/td2), and the time length of the delay can be automatically increased or decreased according to the information of Cmp1_ ON and Cmp2_ ON.
The basis for the increase or decrease is: when the gate control signals Drv _ LD _ td and Drv _ RD _ td of the MOSFETs are 0, i.e., the MOSFETs M2 or M3 are turned off, if the drain voltage of M2 or M3 drops to VTHON again, indicating that the IAC current has not crossed zero, thereby causing the substrate diode of M2 or M3 to conduct, the delay time (td1/td2) is increased by one LSB; if the drain voltage of either M2 or M3 does not drop to VTHON, indicating that the IAC current polarity has flipped, the delay time is decreased by one LSB. Finally, the delay time reaches a dynamic balance point, namely in the nth period of the input current, the adaptive adjusting circuit finds that the delay time needs to be increased by one LSB; in the (n + 1) th cycle of the input current, the adaptive adjustment circuit finds that the delay time needs to be reduced by one LSB.
In the following embodiments, taking M2 as an example, the control method in M3 is the same as M2, and is not described herein again.
Fig. 6 is a schematic diagram of the adaptive adjustment circuit shown in fig. 5.
As shown in fig. 6, the present embodiment provides a full-bridge rectifier adaptive adjustment circuit, including: a decision circuit and a configurable delay circuit. The judgment circuit is connected with the configurable delay circuit. And the judging circuit is used for receiving the driving voltage Drv _ LD and the opening signal ON2 and outputting a control signal BRGCal <0:7 >. The configurable delay circuit is used for receiving the control signals BRGCal <0:7> and the driving voltage Drv _ LD and outputting the delayed driving voltage Drv _ LD _ td.
In another embodiment, a full bridge rectifier adaptive regulation circuit comprising a microprocessor MCU is also provided. When the judging circuit works normally, the microprocessor MCU can monitor the control signal output by the judging circuit in real time. Meanwhile, when a circuit has a problem or needs special needs, the control signal can be controlled by the microprocessor through software.
FIG. 7 is a schematic diagram of the determining circuit shown in FIG. 6;
as shown in fig. 7, in the present embodiment, the judgment circuit includes: a current cycle sampling module, an accumulator and a register. The current period sampling module receives the driving voltage Drv _ LD and the ON signal ON2, and outputs an accumulated signal polar. The current period sampling module specifically comprises: the circuit comprises an inverter, a first D trigger, a second D trigger and a delay unit. The inverter receives the driving voltage Drv _ LD and outputs the driving voltage Drv _ LD to the D end of the first D flip-flop, the CP end of the first D flip-flop receives the opening signal ON2, the R end of the first D flip-flop receives the driving voltage Drv _ LD, and the Q end of the first D flip-flop outputs the driving voltage Drv _ LD to the D end of the second D flip-flop. One end of the delay unit receives the output end of the phase inverter, and the other end of the delay unit outputs the output end of the phase inverter to the CP end of the second D trigger.
In one embodiment, when the driving voltage Drv _ LD is 1, the R terminal of the first D flip-flop is also 1, and thus the first D flip-flop resets the Q terminal to 0 regardless of the D terminal and the CP terminal of the first D flip-flop. When the driving voltage Drv _ LD is 0, the first D flip-flop R terminal is 0, and the first D flip-flop outputs Q according to the CP terminal condition. When the CP receives ON2 of 1, the first D flip-flop assigns the inverse of Drv _ LD at the D to the Q, and the Q is 1. When the ON2 received by the CP terminal is 0, the Q terminal remains unchanged. At this time, the delay unit receives the inverse of the Drv _ LD, outputs the inverse of the Drv _ LD to the CP end of the second D flip-flop after a preset delay time, and the second D flip-flop assigns the value of the D end to the Q end to output an accumulation signal polar.
The accumulator receives the accumulation signal Polary and the control signal BRGCal <0:7> fed back from the output of the register to accumulate and sum, and outputs an accumulation result. When the accumulation signal Polary is 1, one LSB is added; when the accumulation signal Polary is 0, one LSB is decremented. Wherein the accumulator is determined to be an n-bit accumulator based on the speed, accuracy and efficiency of the circuit. In this embodiment, n is 8. One skilled in the art will note that n can be any positive integer.
The register stores the accumulation result output by the accumulator and outputs a control signal to the configurable delay circuit and the accumulator. The register comprises n D triggers, the CP ends of the n D triggers receive driving voltage, the D ends receive accumulation results output by the accumulator, and control signals are output together through the Q ends. Those skilled in the art should note that the D flip-flop can be replaced by an RS flip-flop or a JK flip-flop. In this embodiment, n is 8. One skilled in the art will note that n can be any positive integer.
FIG. 8 is a schematic diagram of the configurable delay circuit of FIG. 6;
as shown in fig. 8, in the present embodiment, the configurable delay circuit is a structure for charging the configurable capacitor array by current, and includes: the circuit comprises n delay MOS tubes, n capacitors, a current source, a first phase inverter, a second phase inverter, a third phase inverter and a drive MOS tube. The first end of the current source is connected with a power supply VDD, the second end of the current source is connected with the drain electrode of the driving MOS tube, the source electrode of the driving MOS tube is grounded, and a driving signal passes through the first phase inverter and the second phase inverter and is connected with the grid electrode of the driving MOS tube. The drain electrodes of the n delay MOS tubes are connected with the second end of the current source, the grid electrodes of the n delay MOS tubes receive control signals BRGCal <0:7>, the source electrode of each MOS tube in the n delay MOS tubes is connected with each of the n capacitors, and the other ends of the n capacitors are grounded. One end of the third inverter is connected with the second end of the current source, and the other end of the third inverter outputs the delayed driving voltage.
The capacity of the n capacitors is specifically as follows: the second capacitance is 2 times of the first capacitance, the third capacitance is 4 times of the first capacitance, and so on, the nth capacitance is 2 times of the first capacitancen-1And (4) doubling. In this embodimentIn the above, n is 8. One skilled in the art will note that n can be any positive integer.
In one embodiment, when the driving voltage Drv _ LD is 1, after twice inversion by the first inverter and the second inverter, the gate voltage of the driving MOS transistor is high, and the driving MOS transistor is turned on. The third inverter is connected with the second end of the current source, and the input of the third inverter is 0 and the output of the third inverter is 1 due to the conduction of the driving MOS tube. When the driving voltage Drv _ LD is 0, the driving MOS tube is turned off, and the gates of the n delay MOS tubes are selectively turned on according to the received control signals BRGCal <0:7 >. Due to the selective conduction of the corresponding delay MOS tube, the current source charges the corresponding capacitor. The current of the input end of the phase inverter is inverted when reaching a certain value, so that the charging time of the capacitor is the same according to the difference of the capacitance after the phase inverter is switched on, the inversion time of the third phase inverter is controlled, and the delay effect is achieved. When the current at the input end of the third inverter reaches the threshold value, the output is inverted to 0, and the delayed driving voltage Drv _ LD _ td is output.
In this embodiment, the circuit delays the falling edge of DRV _ LD without delaying the rising edge, and the capacitor array generates a configurable falling edge delay time with the current source I according to the capacitance values with different values of the control signal BRGCal <0:7 >.
In another embodiment, the first inverter, the second inverter and the third inverter are replaced with a comparator.
Those skilled in the art should also note that the configurable delay circuit may also be configured to charge the configurable capacitor array with resistors, or the configurable capacitor array with capacitors, in various combinations. Wherein, the control signal code is 8421 code or temperature code.
FIG. 9 is a schematic diagram of the adaptive tuning circuit shown in FIG. 5;
at the dynamic balance point, the turn-off control of the MOSFET is limited to be near the IAC current zero crossing, and the control and timing relationship of Drv _ LD _ td and Drv _ LD with ACP are shown in fig. 9, taking the control circuit at the ACP terminal as an example. The current IAC is an alternating current, taking ACP as an example. When the ACP voltage is positive, the comparators Cmp2_ ON and Cmp2_ OFF have no output. When the ACP voltage becomes negative, the current will first turn on the M2 substrate diode, and when the M2 substrate diode turns on, a stable voltage of-0.7V will be generated across the diode. The comparator Cmp2_ ON will detect this voltage, producing an ON2 of 1. When the regulator detects ON2 being 1, the output Drv _ LD is 1. After the Drv _ LD is input to the adaptive adjusting circuit, the output Drv _ LD _ td is 1, and the MOS transistor M2 is controlled to be turned on. In this embodiment, the comparator Cmp2_ OFF is set to a signal that is generally known in the art as the front output of the comparison OFF2, thereby turning OFF the MOS transistor. When the regulator receives a signal of OFF2 ═ 1, the control drive voltage Drv _ RD generates a falling edge. After receiving the falling edge generated by the driving voltage Drv _ LD, the adaptive adjusting circuit generates a delay time td, and outputs Drv _ LD _ td as 0 after the delay time td, thereby actually controlling the MOS transistor M2 to be closed. After the MOS transistor is turned off, the adaptive adjusting circuit will detect whether the comparator Cmp2_ ON is turned ON again by 1. Namely, after the MOS tube is closed, whether the substrate diode is conducted again or not is judged. If the control delay time is not reduced by one LSB, the control delay time is used as the starting time of the MOS tube in the next period; if ON is 1, the control delay time is increased by one LSB and is used as the MOS tube opening time of the next period.
FIG. 10 is a flowchart of a method for controlling the M2 and M4 circuits of FIG. 5.
As shown in fig. 10, in the current period [ n ], it is detected whether ON2 of 1 occurs after Drv _ LD _ td is 0. If so, the delay time td2[ n ] is reduced by one LSB as td2[ n +1 ]; if not, the delay time td2[ n ] is increased by one LSB as td2[ n +1 ]. Then, ON2 and Drv _ LD _ td, Drv _ LD _ td are updated as the time for the MOS transistor to turn ON in the next cycle.
FIG. 11 is a flowchart of a method for controlling the M1 and M3 circuits of FIG. 5.
As shown in fig. 11, in the current period [ n ], it is detected whether ON1 of 1 occurs after Drv _ RD _ td is 0. If so, the delay time td1[ n ] is reduced by one LSB as td1[ n +1 ]; if not, the delay time td1[ n ] is increased by one LSB as td1[ n +1 ]. Then, ON1 and Drv _ RD _ td, Drv _ RD _ td are updated as the time for the MOS transistor to turn ON in the next cycle.
It will be appreciated by those skilled in the art that the above embodiments are only exemplified by M2 and M4, and that the control circuits of M1 and M3 on the other side of the full bridge rectifier are the same as M2 and M4. The invention can be controlled and regulated according to the control circuits of M1 and M3.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (9)
1. A full-bridge rectifier adaptive regulation circuit is characterized by comprising: a judgment circuit and a configurable delay circuit;
the judging circuit is connected with the configurable delay circuit and is used for receiving the driving voltage and the starting signal and outputting a control signal;
the configurable delay circuit is used for receiving the control signal and the driving voltage, and a capacitor array in the configurable delay circuit processes the driving voltage according to the control signal and outputs the delayed driving voltage;
the judgment circuit includes: a current period sampling module, an accumulator and a register;
the current period sampling module receives the driving voltage and the starting signal and outputs an accumulated signal;
the accumulator receives the accumulation signal and the control signal fed back from the register output to accumulate and sum, and outputs an accumulation result;
the register stores an accumulation result output from the accumulator and outputs a control signal to the configurable delay circuit and the accumulator.
2. The circuit of claim 1, wherein the current period sampling module specifically comprises: the circuit comprises an inverter, a first D trigger, a second D trigger and a delay unit;
the inverter receives the driving voltage and outputs the driving voltage to the D end of the first D trigger, the CP end of the first D trigger receives the opening signal, the R end of the first D trigger receives the driving voltage, and the Q end of the first D trigger outputs the D end of the second D trigger;
one end of the delay unit receives the output end of the phase inverter, and the other end of the delay unit outputs the output end of the phase inverter to the CP end of the second D trigger.
3. The circuit of claim 1, wherein the accumulator is determined as an n-bit accumulator based on speed, accuracy and efficiency of the circuit, n being a positive integer; and
the register comprises n D flip-flops; and
the CP ends of the n D triggers receive the driving voltage, the D ends receive the accumulation result output by the accumulator, and the control signals are output together through the Q ends; and
and the D trigger is replaced by an RS trigger or a JK trigger.
4. The circuit of claim 1, wherein the configurable delay circuit is a structure for charging a configurable capacitor array with a current, comprising: the circuit comprises n delay MOS tubes, n capacitors, a current source, a first phase inverter, a second phase inverter, a third phase inverter and a drive MOS tube;
the first end of the current source is connected with a power supply VDD, the second end of the current source is connected with the drain electrode of the driving MOS tube, the source electrode of the driving MOS tube is grounded, and the driving voltage is connected with the grid electrode of the driving MOS tube through the first phase inverter and the second phase inverter; the drain electrodes of the n delay MOS tubes are connected with the second end of the current source, the grid electrodes of the n delay MOS tubes receive control signals, the source electrode of each MOS tube in the n delay MOS tubes is connected with each of the n capacitors, and the other ends of the n capacitors are grounded;
one end of the third inverter is connected with the second end of the current source, and the other end of the third inverter outputs the delayed driving voltage.
5. The circuit according to claim 4, wherein the n capacitors have a capacity of: the second capacitance is 2 times of the first capacitance, the third capacitance is 4 times of the first capacitance, and so on, the nth capacitance is 2 times of the first capacitancen-1And (4) doubling.
6. The circuit of claim 4, wherein the first inverter, the second inverter, and the third inverter are replaced with comparators.
7. The circuit of claim 1, wherein the configurable delay circuit is configured to charge a configurable capacitor array with a resistor or to charge a capacitor array with a configurable current array;
the control signal code is 8421 code or temperature code.
8. The circuit of claim 1, further comprising a microprocessor;
and the microprocessor receives the control signal output by the judgment circuit, controls the control signal through software and outputs the control signal to the configurable delay circuit.
9. A full bridge rectifier comprising a circuit as claimed in any one of claims 1 to 8.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106549560A (en) * | 2011-04-25 | 2017-03-29 | 快捷半导体(苏州)有限公司 | For the synchronous rectifier control technology of resonant vibration converter |
| CN106849621A (en) * | 2017-01-03 | 2017-06-13 | 昂宝电子（上海）有限公司 | A kind of system and method for realizing gate driving circuit |
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| JP5315078B2 (en) * | 2009-02-10 | 2013-10-16 | ザインエレクトロニクス株式会社 | Comparator DC-DC converter using synchronous rectification |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106549560A (en) * | 2011-04-25 | 2017-03-29 | 快捷半导体(苏州)有限公司 | For the synchronous rectifier control technology of resonant vibration converter |
| CN106849621A (en) * | 2017-01-03 | 2017-06-13 | 昂宝电子（上海）有限公司 | A kind of system and method for realizing gate driving circuit |
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