CN109951179B - Startup and shutdown circuit - Google Patents
Startup and shutdown circuit Download PDFInfo
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- CN109951179B CN109951179B CN201711370572.9A CN201711370572A CN109951179B CN 109951179 B CN109951179 B CN 109951179B CN 201711370572 A CN201711370572 A CN 201711370572A CN 109951179 B CN109951179 B CN 109951179B
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Abstract
The invention discloses a power on/off circuit, which is used for solving the problem of higher power consumption of the power on/off circuit of a common handheld wearable device in the prior art. The invention provides a startup and shutdown circuit which comprises a first MOS (metal oxide semiconductor) tube M1, a second MOS tube M2, a first switch unit, a second switch unit, a pulse pickup unit and a power management unit. The first switch unit controls the system of the switch circuit to be powered on or powered off through the first MOS tube M1, and the power management unit generates a control signal to be input into the second switch unit, so that the first switch unit is driven to control the system to be powered on or powered off. When the power supply is shut down, the control signal generated by the power supply management unit is input to the second switch unit, the first MOS transistor M1 is cut off by the second switch unit, the electrification of the system is cut off, the whole system is in a state close to zero power consumption, and the power consumption in the shutdown state is reduced.
Description
Technical Field
The invention relates to the technical field of soft switches, in particular to a startup and shutdown circuit.
Background
Handheld wearable devices refer to portable devices that are supported on the wrist or integrated into the user's clothing or accessories, for example, handheld wearable devices can be smart bands, smart watches, and other wearable items, in order to provide convenient scientific and technological lives for people. The wearable device can embed technologies such as multimedia, sensors and wireless communication into clothes of people, and functions of the handheld wearable device are achieved through software support, data interaction and cloud interaction.
A switching circuit scheme commonly used in a handheld wearable device in the prior art is shown in fig. 1, and the switching circuit scheme is mainly implemented inside a chip. The voltage dividing lines of the R6 and the R7 are connected with the negative electrode of the comparator, the ON/OFF PIN is connected with the positive electrode of the comparator, the output of the comparator is connected with the grid of the Q4 (PMOS), and then the starting of the internal circuit is controlled, so that the switching circuit of the handheld wearable device can be awakened to be in a starting normal use state. However, due to the existing comparator and the fact that the power consumption path to the ground formed by the R6 and the R7 cannot be cut off during shutdown, the comparator, the R6 and the R7 have obvious leakage phenomena in the shutdown state, and therefore the shutdown power consumption is increased.
In summary, the power consumption of the power-off of the power-on and power-off circuit of the handheld wearable device commonly used in the prior art is large.
Disclosure of Invention
The invention provides a power on/off circuit which is used for solving the problem that the power consumption of the power on/off circuit of a handheld wearable device in the prior art is high.
The invention provides a startup and shutdown circuit, which comprises: the power supply comprises a first MOS tube, a second MOS tube, a first switch unit, a second switch unit, a pulse pickup unit and a power supply management unit;
the source electrode of the first MOS tube is connected with an external power supply, and the drain electrode of the first MOS tube is connected with a system comprising the on-off circuit;
the first switch unit is connected with the source electrode and the grid electrode of the first MOS tube and is connected with the second switch unit through the drain electrode of the second MOS tube; the second switch unit is respectively connected with a source electrode of a second MOS tube, the pulse pickup unit and the power management unit; the pulse pickup unit is connected with a grid electrode connected with the second MOS tube;
the pulse pickup unit is used for converting the pulse signal into a voltage signal after inputting an external pulse signal and outputting the voltage signal to the power management unit;
the power supply management unit is used for generating a starting control signal to control the second MOS tube to be switched on after the voltage signal is input, and generating a closing control signal to control the second MOS tube to be switched off after a shutdown signal is input;
when the second MOS tube is conducted, the second switch unit is connected with the first switch unit, and when the second MOS tube is cut off, the second switch unit is disconnected with the first switch unit;
the first switch unit is used for inputting a conducting signal to the first MOS tube to enable the first MOS tube to be in a conducting state after the second switch unit is connected with the first switch unit, and inputting a cut-off signal to the first MOS tube to enable the first MOS tube to be in a cut-off state after the second switch unit is disconnected with the first switch unit.
The embodiment of the invention provides a startup and shutdown circuit which comprises a first MOS tube M1, a second MOS tube M2, a first switch unit, a second switch unit, a pulse pickup unit and a power management unit. The first switch unit controls the system of the switch circuit to be powered on or powered off through the first MOS transistor M1, the pulse pickup unit converts the pulse signal into a voltage signal and outputs the voltage signal to the power management unit, the power management unit supplies power to the second switch unit and generates a control signal to be input to the second switch unit, and the second switch unit drives the first switch unit. Because the control signal generated by the power management unit is input to the second switch unit, the first MOS transistor M1 is cut off by the second switch unit, the electrification of the system is cut off, the whole system is in a state close to zero power consumption, and the power consumption in a shutdown state is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required to be used in the description of the embodiments will be briefly introduced below, and it is apparent that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings may be obtained according to the drawings without inventive labor.
Fig. 1 is a schematic structural diagram of a switching on/off circuit in the prior art;
fig. 2 is a schematic structural diagram of a module of a switching circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a first switching unit of a switching circuit according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a second switching unit of the switching circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a pulse pickup unit of a power on/off circuit according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a first signal generation circuit;
FIG. 7 is a circuit schematic of a second generation signal;
FIG. 8 is a schematic diagram of a third signal generation circuit;
fig. 9 is a schematic structural diagram of a power management unit of a switching circuit according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of an anti-false-boot module of a switching circuit according to an embodiment of the present invention;
fig. 11 is a complete circuit diagram of a power on/off circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a switching circuit, and a specific implementation of the switching circuit is described below.
As shown in fig. 2, the switching circuit according to the embodiment of the present invention includes a first MOS transistor M1, a second MOS transistor M2, a first switching unit 11, a second switching unit 12, a pulse picking unit 13, and a power management unit 14.
The source electrode of the first MOS tube M1 is connected with an external power supply, and the drain electrode of the first MOS tube M1 is connected with a system comprising the on-off circuit;
the first switch unit is connected with the source electrode and the grid electrode of the first MOS tube M1 and is connected with the second switch unit through the drain electrode of the second MOS tube M2; the second switch unit is respectively connected with a source electrode of a second MOS tube M2, the pulse pickup unit and the power management unit; the pulse pickup unit is connected with a grid connected with the second MOS tube M2;
the pulse pickup unit is used for converting the pulse signal into a voltage signal after inputting an external pulse signal and outputting the voltage signal to the power management unit;
the power supply management unit is used for generating a starting control signal to control the conduction of the second MOS transistor M2 after the voltage signal is input, and generating a closing control signal to control the cut-off of the second MOS transistor after a shutdown signal is input;
when the second MOS tube is conducted by M2, the second switch unit is connected with the first switch unit, and when the second MOS tube is cut off, the second switch unit is disconnected with the first switch unit;
the first switch unit is used for inputting a conducting signal to the first MOS tube M1 after the second switch unit is connected with the first switch unit, so that the first MOS tube M1 is in a conducting state, and inputting a stopping signal to the first MOS tube M1 after the second switch unit is disconnected with the first switch unit, so that the first MOS tube M1 is in a stopping state.
It should be noted here that the second MOS transistor M2, the first switching unit 11, the second switching unit 12, and the pulse picking unit 13 may be integrated in the chip, which will save the cost of the peripheral circuit and save more resources.
The embodiment of the invention provides a startup and shutdown circuit which comprises a first MOS tube M1, a second MOS tube M2, a first switch unit, a second switch unit, a pulse pickup unit and a power management unit. After an external pulse signal is input, a first switch unit controls a system of the switch circuit to be powered on or powered off through the first MOS transistor M1, the pulse pickup unit converts the pulse signal into a voltage signal and outputs the voltage signal to a power management unit, the power management unit supplies power to the second switch unit and generates a control signal to be input to the second switch unit, and the second switch unit drives the first switch unit. Because the control signal generated by the power management unit is input into the second switch unit, the first MOS transistor M1 is cut off by the second switch unit, and the electrification of the system is cut off, so that the whole system is in a near zero power consumption state, and the power consumption in a shutdown state is reduced.
Alternatively, as shown in fig. 3, the first switching unit 11 includes: a first resistor R1 and a third MOS transistor M3.
One end of the first resistor R1 is connected with the source electrode of the first MOS transistor M1, and the other end of the first resistor R1 is connected with the drain electrode of the third MOS transistor M3; the drain electrode of the third MOS tube M3 is connected with the grid electrode of the first MOS tube M1, the source electrode of the third MOS tube M3 is connected with the ground, and the grid electrode of the third MOS tube M3 is connected with the second switch unit.
When the grid of the third MOS transistor M3 receives a level signal, the third MOS transistor M3 will generate a level signal and transmit the level signal to the grid of the first MOS transistor M1, so as to drive the first MOS transistor M1 to be turned on or off, so that an external power supply can power on or off a system of the switching circuit through the first MOS transistor M1.
Alternatively, as shown in fig. 4, the second switch unit 12 includes: the second resistor R2, the third resistor R3 and the fourth MOS tube M4;
one end of the second resistor R2 is connected with the pulse pickup unit, and the other end of the second resistor R2 is connected with one end of the third resistor R3; the other end of the third resistor R3 is connected with the ground; the following steps: a connection point of the second resistor R2 and the third resistor R3 is respectively connected with a grid electrode of the third MOS transistor M3 and a source electrode of the second MOS transistor M2; the source electrode and the grid electrode of the fourth MOS tube M4 are connected with the power management unit, and the drain electrode of the fourth MOS tube M4 is connected with the source electrode of the second MOS tube M2.
After the second resistor R2 and the third resistor R3 receive pulse signals after the power on/off operation, the pulse signals are converted into voltage signals and transmitted to the grid electrode of the third MOS transistor M3, and the first MOS transistor M1 is driven to be switched on or switched off, so that the first MOS transistor M1 is controlled to be switched on;
when receiving the control signal sent by the power management unit, the fourth MOS transistor M4 is in an on or off state, generates different level signals, transmits the different level signals to the gate of the third MOS transistor M3, and drives the first MOS transistor M1 to be on or off, thereby controlling the system to be powered on or powered off.
Alternatively, as shown in fig. 5, the pulse picking unit 13 includes: a fourth resistor R4 and a fifth resistor R5;
one end of the fourth resistor R4 is connected with the second resistor R2, the other end of the fourth resistor R4 is connected with the fifth resistor R5, and the other end of the fifth resistor R5 is connected with the ground; and the connection point of the fourth resistor R4 and the fifth resistor R5 is respectively connected with the power management unit and the grid electrode connected with the second MOS tube M2.
The pulse pickup unit composed of the fourth resistor R4 and the fifth resistor R5 divides the voltage of the pulse signal, converts the pulse signal into a voltage signal Vdet and transmits the voltage signal Vdet to the power management unit, so that the power management unit generates a corresponding control signal and the fourth MOS transistor M4.
The pulse signal includes, but is not limited to, the following generation forms:
as shown in fig. 6, the pulse signal key generates high and low level signals:
the POWER (POWER) may be the external POWER in the present invention in the embodiment of the present invention, or may be other external POWER, and the embodiment of the present invention is not limited herein. ON is connected to ON pin in an embodiment of the invention (i.e. at the pulse signal in an embodiment of the invention).
When KEY1 is pressed, ON will generate a high level pulse, and when the amplitude and time of the high level pulse satisfy V in the embodiment of the present invention h And T H When the system is in the power-on state, the KEY1 or the KEY2 is pressed, the signal detector can detect that the signal is a high-level pulse or a low-level pulse, and the system is informed to carry out related actions according to the detection result.
As shown in fig. 7, the pulse signal is generated by the combination of the power toggle switch and the RC circuit as a high-low level signal:
the POWER may be an external POWER supply in the embodiment of the present invention, or may be another external POWER supply, and the embodiment of the present invention is not limited herein, and the ON is connected to an ON pin (that is, a pulse signal in the embodiment of the present invention).
When a SWITCH is pressed, a high-level pulse secondary signal is generated ON the process ON of charging the capacitor C by the POWER due to the existence of the resistor R and the capacitor C, the high-level amplitude depends ON the POWER, the charging time depends ON the values of the resistor R and the capacitor C, and when the high-level pulse amplitude is pressedSum time satisfying Vh and T in the embodiment of the present invention H And parameters can prompt the working process of the system in the starting state.
As shown in fig. 8, the pulse signal is output by the single chip or the high-low level signal is generated by the timer:
wherein, the high level pulse signal that external singlechip or timer produced is directly connected to ONpin (namely pulse signal department in this embodiment of this invention) in this invention. When the high level pulse amplitude and time satisfy Vh and T in the embodiment of the present invention H And parameters can trigger the system to be in the starting working process. When the system is in a power-on state, the signal detector can detect whether the signal is a high-level pulse or a low-level pulse, and the system is informed to carry out relevant actions according to the detection result.
Optionally, as shown in fig. 9, the power management unit 14 includes: the device comprises a clock generator, a power supply voltage stabilizer, a signal detector, a reference voltage circuit and an enabling controller;
the power supply voltage stabilizer is connected with the source electrode of the fourth MOS tube M4; the signal detector is respectively connected with the reference voltage circuit, the clock generator, a connection point of a fourth resistor R4 and a fifth resistor R5 and a grid electrode of the second MOS transistor M2; the enabling controller is respectively connected with the signal detector and the grid electrode of the fourth MOS tube M4;
the power supply voltage stabilizer is used for providing electric energy for the power supply management unit and the second switch unit; the reference voltage circuit is used for inputting a reference voltage for the signal detector; the clock generator is used for providing delay filtering for the signal detector;
because the pulse signal can be generated by various forms possibly outside, interference signals such as burrs, short pulses and the like inevitably exist, and if the signal detector of the clock generator is adopted to provide delay filtering, the interference signals can be filtered out, and the condition that the switch circuit is in a power-on state due to false detection is avoided.
When the duration time of the high level of the pulse signal is less than the preset delay time tdelay, the clock generator does not filter the pulse signal, so that the switching circuit is prevented from being in a power-on state due to interference signal access.
For example, assuming that the high level duration t of the pulse signal is 20 seconds, the preset delay time tdelay is 30 seconds, and the high level duration of the pulse signal is less than the preset delay time tdelay, the clock generator does not filter the pulse signal.
The power supply voltage stabilizer is used for providing electric energy for the power supply management unit and the second switch unit; the reference voltage circuit is used for inputting a reference voltage for the signal detector;
the clock generator is used for providing delay filtering for the signal detector;
the signal detector is used for detecting a voltage signal converted by the pulse signal and the pulse high level duration after a reference voltage is input, and outputting a detection result to the enable controller;
the enabling controller is used for generating a starting control signal according to a preset high level voltage signal threshold value, a preset filtering time threshold value and an input detection result after the starting condition is met, inputting the starting control signal into the second MOS tube to be conducted, and enabling the second switch unit to be connected with the first switch unit, for example, generating a low level signal; or
After a shutdown signal is input, a shutdown control signal is generated and input to the second MOS transistor to be conducted, so that the second switch unit is disconnected from the first switch unit, for example, a high level signal is generated.
Wherein the enable controller is specifically configured to:
according to a preset high-level voltage signal threshold value, a preset filtering time threshold value and an input detection result, after a starting condition is met, a starting control signal is generated and input to a second MOS tube to be conducted, so that the second MOS tube is conducted; or after the shutdown signal is input, a shutdown control signal is generated and input to the second MOS tube to be conducted, so that the second MOS tube is cut off.
At the moment that the external power supply is initially connected to Vsupply, and before a pulse signal is generated by an external circuit or a key press, the system is in an unpowered state, a large parasitic capacitor C exists between the gate of the first MOS transistor M1 and the ground, so that the gate of the first MOS transistor M1 is in a low level state, the first resistor R1 is a resistor with a large value, the Vsupply passes through the gate, and the parasitic capacitor C is charged by the first resistor R1 for a long time to enable the gate of the first MOS transistor M1 to be in a high level state, and during the period, the first MOS transistor M1 is easily turned on, so that the system of the switching circuit is powered on.
The Vsupply is a connection position of an external power supply and a source electrode of the first MOS tube M1.
In order to prevent the first MOS transistor M1 from being easily turned on at the time of the initial external power supply access, thereby powering on the system of the switching circuit.
As shown in fig. 10, the switching circuit according to the embodiment of the present invention further includes a power-on error prevention module 15 connected to the gate of the first MOS transistor M1, for generating a high-level signal input to the gate of the first MOS transistor M1.
The false start-up prevention module 15 includes: a sixth resistor R6, a first capacitor C1 and a fifth MOS transistor M5;
one end of the sixth resistor R6 is connected with the source electrode of the first MOS transistor M1, and the other end of the sixth resistor R6 is connected with the first capacitor C1; the other end of the first capacitor C1 is connected with the ground; the grid electrode of the fifth MOS tube M5 is connected with a connection point of a sixth resistor R6 and the first capacitor, the source electrode of the fifth MOS tube M5 is connected with the source electrode of the first MOS tube M1, and the drain electrode of the fifth MOS tube M5 is connected with the grid electrode of the first MOS tube M1.
The sixth resistor R6 and the first capacitor C1 in the anti-false-start module form an RC buffer circuit, when the initial power is switched into Vsupply, and before a pulse signal is not provided by an external circuit or generated by pressing a key, the buffer circuit rapidly absorbs current to drive the second MOS tube M2 to be switched on, so that the grid electrode of the other first MOS tube M1 is in a high-level state, and the first MOS tube is in a cut-off state in the period, so that the system of the switching circuit cannot be powered on.
The first MOS tube M1, the second MOS tube M2 and the fourth MOS tube M4 are P-channel MOS tubes, and the third MOS tube M3 is an N-channel MOS tube.
As shown in fig. 11, the operation of the switching circuit including the first MOS transistor M1, the second MOS transistor M2, the first switching unit, the second switching unit, the pulse pickup unit, and the power management unit will be described in detail below.
1. And the starting-up working process of the switching circuit.
When an external power supply is connected to the switching circuit through Vsupply, a high-level pulse signal von off is generated through the external circuit or the external key, wherein the voltage amplitude of the high-level pulse signal von off may be less than or equal to the voltage amplitude at Vsupply.
After the high-level pulse signal von is connected, vctl = R3/(R2 + R3) × von, and the conduction threshold of the third MOS transistor is met, at this time, the third MOS transistor is conducted and will generate a low-level signal to be transmitted to the gate of the first MOS transistor M1, the first MOS transistor M1 is rapidly driven to be conducted, and at this time, the external power supply will supply power to the system of the switching circuit through Vsupply.
When the system of the switching circuit supplies power, the power voltage stabilizer in the power management unit can be quickly started to supply power to the clock generator, the signal detector, the reference voltage circuit and the enabling controller in the power management unit. The clock generator starts to provide delay filtering for the signal detection circuit, the reference voltage circuit provides reference voltage for the detection circuit, the signal detection circuit starts to detect a level signal at Vdet and a high-level pulse duration Th, a pulse pick-up unit composed of a fourth resistor R4 and a fifth resistor R5 converts the pulse signal into a voltage signal, namely Vdet = R5/(R4 + R5) × von, and the signal detection circuit outputs the high-level pulse duration Th and the level state at Vdet to the enable controller.
The enabling controller is a threshold V with high level according to the preset Vdet H Time filtering threshold T F Comparing with the level state at Vdet when Vdet>＝V H And Th-Tr>＝T F At this time, the on-off of the on-off circuit is satisfiedAnd under the condition, the enable controller generates a low level signal Ven to be transmitted to the grid electrode of the fourth MOS tube M4, the fourth MOS tube M4 is conducted, a low level signal is generated to be transmitted to the grid electrode of the third MOS tube M3, the third MOS tube M3 is driven to be conducted, and then the first MOS tube M1 meets the conduction threshold value and is in a conduction state.
Wherein Vset is a high-level threshold value V H Time filtering threshold T F The numerical value of (A) can be set by the person skilled in the art according to the actual needs.
According to the switching circuit provided by the embodiment of the invention, because two paths exist to control the first MOS transistor M1, even when the level pulse signal Vonoff falls to a low level, the controller can generate a low level signal Ven to be transmitted to the grid electrode of the fourth MOS transistor M4, so that the fourth MOS transistor M4 is conducted to drive the third MOS transistor M3 to be conducted, and further the first MOS transistor M1 meets the conduction threshold value and is in a conduction state, and a system comprising the switching circuit is ensured to be in a continuous power supply state.
2. The normal working process of the switching on/off circuit system comprises the following steps:
the signal detection circuit continuously detects the level state of the Vdet, even if no pulse signal is provided by an external key or an external circuit, the signal detection unit can ensure that the Vdet is in a middle level state, namely V, because the power management unit is in a working state L <Vdet<V H 。
Wherein, V L Detect a minimum threshold of high level at Vdet for the signal detection circuit, where V H The highest threshold of high level at Vdet is detected for the signal detection circuit.
When the detection circuit continuously detects that the time of the high level or the low level at Vdet exceeds the filtering time, the memory in the power management unit generates a corresponding flag bit according to a preset indication for the system to inquire, so that the system executes a corresponding operation.
3. The shutdown working process comprising the switching circuit system comprises the following steps:
when the system is in a shutdown working process, after the shutdown signaler inputs the enable control, the enable control generates a high-level signal Ven and transmits the high-level signal Ven to the grid electrode of the fourth MOS transistor M4, and then the fourth MOS transistor M4 is cut off. At this time, the voltage at the gate of the second MOS transistor M2 is in a high level state, so that the third MOS transistor M3 no longer satisfies the turn-on threshold, and will be turned off, wherein the shutdown signal may be output to the enable controller by software operation or key operation.
Because the drain electrode of the third MOS transistor M3 is connected with the gate electrode of the first MOS transistor M1, when the third MOS transistor M3 is cut off, a high level signal is generated and transmitted to the gate electrode of the first MOS transistor M1, the first MOS transistor M1 no longer meets the conduction threshold value, and the first MOS transistor M1 is cut off, so that an external power supply cannot supply power to a system through the first MOS transistor M1.
After the switching on/off circuit is completely disconnected, except that the first MOS tube M1, the second MOS tube M2, the third MOS tube M3, the first resistor R1 and the Vsupply position at the joint of the external power supply and the first MOS tube M1 have slight electric leakage, other components in the switching on/off circuit are basically in a power-off zero power consumption state, and the power consumption is greatly saved.
The present application is described above with reference to block diagrams and/or flowchart illustrations of methods, apparatus (systems) and/or computer program products according to embodiments of the application. It will be understood that one block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, and/or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer and/or other programmable data processing apparatus, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.
Accordingly, the subject application may also be embodied in hardware and/or in software (including firmware, resident software, micro-code, etc.). Furthermore, the application may take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of this application, a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A power on/off circuit, comprising: the power supply comprises a first MOS tube, a second MOS tube, a first switch unit, a second switch unit, a pulse pickup unit and a power supply management unit;
the source electrode of the first MOS tube is connected with an external power supply, and the drain electrode of the first MOS tube is connected with a system comprising the on-off circuit;
the first switch unit is connected with the source electrode and the grid electrode of the first MOS tube and is connected with the second switch unit through the drain electrode of the second MOS tube; the second switch unit is respectively connected with a source electrode of a second MOS tube, the pulse pickup unit and the power management unit; the pulse pickup unit is connected with a grid connected with the second MOS tube;
the pulse pickup unit is used for converting the pulse signal into a voltage signal after inputting an external pulse signal and outputting the voltage signal to the power management unit;
the power supply management unit is used for generating a starting control signal to control the second MOS tube to be switched on after the voltage signal is input, and generating a closing control signal to control the second MOS tube to be switched off after a shutdown signal is input;
when the second MOS tube is conducted, the second switch unit is connected with the first switch unit, and when the second MOS tube is cut off, the second switch unit is disconnected with the first switch unit;
the first switch unit is used for inputting a conducting signal to the first MOS tube to enable the first MOS tube to be in a conducting state after the second switch unit is connected with the first switch unit, and inputting a cut-off signal to the first MOS tube to enable the first MOS tube to be in a cut-off state after the second switch unit is disconnected with the first switch unit.
2. The switching circuit according to claim 1, wherein the first switching unit includes: a first resistor and a third MOS tube;
one end of the first resistor is connected with the source electrode of the first MOS tube, and the other end of the first resistor is connected with the drain electrode of the third MOS tube;
the drain electrode of the third MOS tube is connected with the grid electrode of the first MOS tube, the source electrode of the third MOS tube is connected with the ground, and the grid electrode of the third MOS tube is connected with the second switch unit.
3. The switching circuit according to claim 2, wherein the second switching unit includes: the second resistor, the third resistor and the fourth MOS tube are connected;
one end of the second resistor is connected with the pulse pickup unit, and the other end of the second resistor is connected with one end of the third resistor; the other end of the third resistor is connected with the ground; the connection point of the second resistor and the third resistor is respectively connected with the grid electrode of the third MOS tube and the source electrode of the second MOS tube;
and the source electrode and the grid electrode of the fourth MOS tube are connected with the power management unit, and the drain electrode of the fourth MOS tube is connected with the source electrode of the second MOS tube.
4. The switching circuit of claim 3, wherein the pulse picking unit comprises: a fourth resistor and a fifth resistor;
one end of the fourth resistor is connected with the second resistor, the other end of the fourth resistor is connected with one end of the fifth resistor, and the other end of the fifth resistor is connected with the ground;
and the connection point of the fourth resistor and the fifth resistor is respectively connected with the source management unit and the grid connected with the second MOS tube.
5. The switch circuit of claim 4, wherein the power management unit comprises: the device comprises a clock generator, a power supply voltage stabilizer, a signal detector, a reference voltage circuit and an enabling controller;
the power supply voltage stabilizer is used for providing electric energy for the power supply management unit and the second switch unit;
the reference voltage circuit is used for inputting a reference voltage for the signal detector;
the clock generator is used for providing delay filtering for the signal detector;
the signal detector is used for detecting a voltage signal converted by the pulse signal and the pulse high level duration after the reference voltage is input, and outputting a detection result to the enable controller;
the enabling controller is used for generating a starting control signal according to a preset high-level voltage signal threshold value, a preset filtering time threshold value and an input detection result after the starting condition is met, inputting the starting control signal into the second MOS tube for conduction, and enabling the second switch unit to be connected with the first switch unit; or after the shutdown signal is input, a shutdown control signal is generated and input to the second MOS tube to be conducted, so that the second switch unit is disconnected with the first switch unit.
6. The switching circuit according to claim 5, wherein the power supply regulator is connected to a source of the fourth MOS transistor; the signal detector is respectively connected with the reference voltage circuit, the clock generator, a connection point of the fourth resistor and the fifth resistor and a grid electrode connected with the second MOS tube; the enabling controller is respectively connected with the signal detector and the grid electrode of the fourth MOS tube;
the enable controller is specifically configured to:
according to a preset high-level voltage signal threshold value, a preset filtering time threshold value and an input detection result, after a starting condition is met, a starting control signal is generated and input to a second MOS tube to be conducted, so that the second MOS tube is conducted; or after the shutdown signal is input, a shutdown control signal is generated and input to the second MOS tube to be conducted, so that the second MOS tube is cut off.
7. The switching circuit according to claim 6, further comprising a false turn-on preventing module connected to the gate of the first MOS transistor for generating a high level signal inputted to the gate of the first MOS transistor.
8. The switch circuit of claim 7, wherein the false boot prevention module comprises: the sixth resistor, the first capacitor and the fifth MOS tube;
one end of the first resistor is connected with a source electrode of the first MOS tube, and the other end of the first resistor is connected with the first capacitor; the other end of the first capacitor is connected with the ground;
the grid electrode of the fifth MOS tube is connected with a connection point of a sixth resistor and the first capacitor, the source electrode of the fifth MOS tube is connected with the source electrode of the first MOS tube, and the drain electrode of the fifth MOS tube is connected with the grid electrode of the first MOS tube.
9. The switching circuit according to claim 8, wherein the first MOS transistor, the second MOS transistor, the fourth MOS transistor, and the fifth MOS transistor are P-channel MOS transistors;
and the third MOS tube is an N-channel MOS tube.
10. An electronic device, characterized in that it comprises a switching circuit according to any one of claims 1 to 9.
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| CN109951179B true CN109951179B (en) | 2022-12-23 |
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