CN109950258A - Semiconductor devices and its manufacturing method - Google Patents
Semiconductor devices and its manufacturing method Download PDFInfo
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- CN109950258A CN109950258A CN201711386306.5A CN201711386306A CN109950258A CN 109950258 A CN109950258 A CN 109950258A CN 201711386306 A CN201711386306 A CN 201711386306A CN 109950258 A CN109950258 A CN 109950258A
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- metal silicide
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
A kind of semiconductor devices, comprising: substrate is provided with the first passivation layer on substrate；It is provided with a groove for exposing substrate in first passivation layer, is filled with germanium layer in groove；Metal silicide layer is arranged above germanium layer；Second passivation layer is arranged on metal silicide layer；Contact hole is arranged in the second passivation layer and part metals silicide layer above metal silicide layer, and the lower surface of contact hole is higher than the upper surface of germanium layer.
Description
Technical field
The present invention relates to semiconductor fields, more particularly, to a kind of semiconductor devices and its manufacturing method.
Background technique
Silicon based photon technology can on same chip integrated optical device and electricity device.By silicon waveguide, modulation
The on piece optic communication of high speed, large capacity, energy may be implemented in the photon link of the silicon photonic device such as device, photoswitch, detector composition
Enough meet it is growing to optical communication system low-power consumption, the requirement of cheap, high speed etc..
Important devices of the detector as on piece photoelectric signal transformation, are constantly subjected to pay close attention to.Via the light of silicon waveguide incidence
Wave forms the strength signal of light under the action of high frequency silicon-based modulator, and the optical signal after being modulated is by certain function
It is received by a detector after silicon-based devices, reconvert becomes the electric signal of high frequency.
The detection of high frequency optical signal at present can be integrated by III-V race's high-performance detector of hybrid integrated and CMOS line
The mode of germanium silicon detector solves.
CMOS integrates absorption characteristic of the germanium silicon detector using germanium (Ge) material in 1550nm wave band and realizes to optical signal
Detection.Optical signal via after silicon waveguide evanescent wave couple under the action of enter germanium layer (Ge-Layer).In germanium layer, photon quilt
It absorbs and generates electron-hole pair.Under the action of extra electric field, electronics, hole drift motion form electric current.
In traditional technology, a contact hole is set above Ge layers, the signal being used for transmission between device and external circuitry, such as
What improves the performance of germanium silicon detector, especially how to improve one of the Important Problems that the formation process of contact hole is research.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of semiconductor structures and forming method thereof, can improve contact hole shape
At technique.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of semiconductor devices, comprising: substrate, the substrate
On be provided with the first passivation layer；It is provided with a groove for exposing the substrate in first passivation layer, is filled out in the groove
Filled with germanium layer；Metal silicide layer is arranged above the germanium layer；Second passivation layer is arranged on the metal silicide layer；
Contact hole is arranged on the second passivation layer above the metal silicide layer, and the lower surface of the contact hole is higher than the germanium
The upper surface of layer.
Optionally, the metal silicide layer is one of tungsten silicon, nickel SiClx, titanizing silicon, cobalt SiClx or a variety of
Combination
Optionally, there is adhesive layer above the contact hole and second passivation layer.
Optionally, metal layer is provided with above the adhesive layer.
Optionally, the thickness of the metal silicide layer is greater than
The present invention also includes a kind of manufacturing method of semiconductor devices, comprising: provides a substrate, is formed over the substrate
First passivation layer；Etching states the first passivation layer to the substrate is exposed to form groove, forms germanium layer in the groove；Institute
It states in groove, form metal silicide layer above the germanium layer；
In second passivation layer of metal silicide layer disposed thereon；It etches second blunt above the metal silicide layer
Change layer and part metals silicide layer forms contact hole, the lower surface of the contact hole is higher than the upper surface of the germanium layer.
Optionally, forming metal silicide layer in the groove, above the germanium layer includes: in the groove,
Silicon layer is formed above the germanium layer；Transition metal is formed, annealing is implemented, chemically reacts the silicon layer and transition metal
To metal silicide layer.
Optionally, etching states the first passivation layer to after exposing the substrate formation groove, using selective growth technique shape
At germanium layer.
Optionally, the silicon layer is formed using growth in situ technique.
Optionally, the thickness of the metal silicide layer is greater than
Optionally, adhesive layer is formed above the contact hole and second passivation layer.
Optionally, further includes: in the adhesive layer disposed thereon initial metal layer, chemistry is carried out to the initial metal layer
Mechanical lapping, removal are higher than the initial metal layer of the contact hole height component, form metal layer.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
Metal silicide layer is arranged in the present invention above germanium layer, when forming contact hole, it is not necessary to exposure germanium layer, to protect
Germanium layer is not damaged.
Detailed description of the invention
Fig. 1 is a kind of a kind of typical structure of integrated germanium silicon detector of CMOS；
Fig. 2-Fig. 3 is that traditional technology forms contact hole step schematic diagram；
Fig. 4-Figure 12 is that the embodiment of the present invention forms contact hole step schematic diagram.
Specific embodiment
Wafer test structure of the invention is described in more detail below in conjunction with schematic diagram, which show this hairs
Bright preferred embodiment, it should be appreciated that those skilled in the art can modify invention described herein, and still realize this hair
Bright advantageous effects.Therefore, following description should be understood as the widely known of those skilled in the art, and be not intended as
Limitation of the present invention.
CMOS integrates a kind of typical structure of germanium silicon detector as shown in Figure 1, substrate 10 can be silicon-on-insulator
(Silicon-On-Insulator, SOI) substrate, silicon-on-insulator (Silicon-On-Insulator, SOI), also referred to as insulate
Silicon on substrate introduces one layer of buries oxide layer (BOX) between top layer silicon and backing bottom, is a kind of with unique " silicon/insulation
The novel silicon base semiconductor material of layer/silicon " three-decker.It by buries oxide layer realize all dielectric of device and substrate every
From.
Passivation layer 11 and germanium layer 14 are set on substrate 10, need manufacture contact hole (Via) to expose germanium layer 14 on germanium layer 14,
Germanium layer 14 is electrically connected with other devices, such as is electrically connected with electrode 15.
Traditional technology forms a kind of method and step of contact hole as shown in Fig. 2-Fig. 3, referring to FIG. 2, it is initially formed substrate 10,
Substrate 10 can be SOI substrate.Contact hole is formed on substrate 10, and forms silicon on the semiconductor substrate being located in contact hole
Compound layer 12, silicide layer 12 can be metal silicide.
Fig. 2, Fig. 3 are please referred to, in 12 disposed thereon passivation layer 11 of substrate 10 and silicide layer, etches 12 top of silicide layer
Passivation layer 11 until exposing silicide layer 12.So far, contact hole 13 is formd.
However the above method can be led to the problem of in the contact hole being applied to above manufacture Ge.For example, in Etch Passivation
In the process, the impurity such as residual polyalcohol can be generated, these impurity are needed using H2O2It is removed, and H2O2It can change with Ge
Reaction is learned, the germanium layer being exposed can be destroyed.
For the problem of manufacture contact hole, to solve the technical problem, the application proposes such as lower section above Ge
Method: a substrate is provided, forms the first passivation layer over the substrate；Etching states the first passivation layer to exposing the substrate to be formed
Groove forms germanium layer in the groove；In the groove, metal silicide layer is formed above the germanium layer；In the gold
Belong to the second passivation layer of silicide layer disposed thereon；Etch the second passivation layer and part metals silicon above the metal silicide layer
Compound layer forms contact hole, and the lower surface of the contact hole is higher than the upper surface of the germanium layer.
Wherein, in the forming method of semiconductor structure of the invention, due to being initially formed metal silicide above germanium layer
Layer, so that germanium layer not will receive destruction in subsequent etching processes, to guarantee the stability of technique.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Referring to figure 4., substrate 100 can be SOI substrate, be also possible to stacking silicon (SSOI) on insulator, on insulator
SiGe (S-SiGeOI), germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI), silicon, SiGe is laminated
(GeSi), the materials such as III-V compound such as silicon carbide (SiC) or GaAs.
Substrate 100 is semiconductor substrate, could be formed with device, such as transistor etc. in substrate 100.In substrate 100
Can also be formed with isolation structure, the isolation structure be shallow trench isolation (STI) structure or selective oxidation silicon (LOCOS) every
From structure.Can also be formed with cmos device in semiconductor substrate, cmos device be, for example, transistor (for example, NMOS and/or
PMOS) etc..Equally, conductive member can also be formed in semiconductor substrate, conductive member can be the grid of transistor, source electrode
Or drain electrode, it is also possible to the metal interconnection structure, etc. being electrically connected with transistor.
The first passivation layer 101 is formed on substrate 100, the material of the first passivation layer 101 can be silica, silicon nitride,
It can be other insulating materials.
Referring to figure 5., the first passivation layer 101 of etching forms groove 111 to substrate 100 is exposed, and etching depth can be carved
Erosion is to substrate 100 is just exposed, and in order to guarantee sufficiently to expose substrate 100, can also slightly cross and carve.
The technique for forming passivation layer can be chemical vapor deposition or sputtering etc., and the technique of Etch Passivation can be dry method
Etching, more preferably plasma etching.In addition, groove can also be cleaned, after the formation of the recess to remove the residual of contact hole
Stay object.
Fig. 6 is please referred to, germanium layer 103 is filled into groove 111, forms silicon layer 104 above germanium layer 103.Wherein, optional
Ground, germanium layer 103 are formed using selective growth technique, specifically, after forming groove 111, expose the silicon face of substrate, at this time
There are surface and the substrate surface of the first passivation layer in the surface of device exposure, such as substrate surface can be the surface Si, the first passivation
The surface of layer can be SiO2Surface.
Germanium layer can use various depositional modes, such as CVD technique, the gas component in depositing operation be adjusted, so that germanium
Layer is relatively easily deposited on the surface Si, and is difficult to be deposited on SiO2Surface, in this way, forming Ge by the technique of selective growth
Layer.Mask plate in deposition process, simple process is omitted in selective growth.
Optionally, silicon layer 104 is formed using growth in situ technique, and compared to other techniques, growth in situ has higher
Craft precision.
Fig. 7 is please referred to, forms transition metal, such as plate transition metal on silicon layer 104, and carry out annealing process, so that
Transition metal is chemically reacted with silicon, is generated metal silicide, is obtained metal silicide layer 105, annealing temperature and technique item
Part can refer to metal silicide formation condition in the prior art.
Metal silicide can be one of tungsten silicon, nickel SiClx, titanizing silicon, cobalt SiClx or a variety of combinations.Metal
Silicide has the characteristics such as fusing point high (being greater than 1000 DEG C), resistivity low (about 10-7 Ω m), can reduce and is subsequently formed
Contact resistance between metal layer and germanium layer.
Metal silicide has good electric conductivity, and the subsequent contact hole lower surface etched above metal silicide is stopped
Only on metal silicide, Ge layers of protection is not exposed out, to prevent Ge layers to be destroyed.Metal silicide layer is as conductive
Ge layers and metal layer is connected in layer, and electric signal is connected.
Preferably, the thickness of metal silicide layer 105 is greater thanDue to metal silicide layer need to protect Ge not by
Be exposed, it is therefore desirable to have certain thickness, in conjunction with prior art, the thickness of metal silicide layer 105 more preferably greater than
Furthermore certain thickness metal silicide can also be further ensured that the stabilization of electric property.
Fig. 8 is please referred to, in 105 the second passivation layer of disposed thereon 106 of metal silicide layer, the material of the second passivation layer can be with
It is silica, silicon nitride, is also possible to other insulating materials.Second passivation layer be in order to prepare to subsequent etching contact hole,
Therefore the height of the second passivation layer will ensure to meet the etching depth of contact hole, guarantee contact hole etching to metal silicide layer,
Ge layers will not be etched into.
Fig. 9 is please referred to, the second passivation layer 106 and part metals the silicide layer formation above metal silicide layer is etched and connects
Contact hole 107, the lower surface of contact hole 107 are higher than the upper surface of germanium layer 103, that is to say, that 107 etching stopping of contact hole is in metal
In silicide layer, Ge layers will not be exposed, to protect Ge layers not to be destroyed.
Contact hole 107 has in device architecture composition as the channel connected between device active region and external circuitry
Important role.Before etching contact hole 107, gate structure, active area, active area can have been formed on substrate 100
The metal silicide and covering gate structure on surface and the nitration case of active area and the passivation layer etc. for being deposited on nitridation layer surface
Deng.In the present embodiment, only show schematically passivation layer on a semiconductor substrate 100, passivation layer using silica, but
It is also possible to canopy silica glass, phosphorosilicate glass, canopy phosphorosilicate glass etc. in other embodiments.It is other such as gate structures, active
Area, surfaces of active regions metal silicide etc. then for simplifying and purpose facilitated to be not shown.
The forming method of contact hole 107 uses method commonly used in the art, for example is coated with back light on 106 surface of the second passivation layer
Photoresist layer is exposed development to the photoresist layer, defines the position of contact hole, is then with the photoresist after exposure development
Then exposure mask recycles dry etching to perform etching to form contact hole 107 to the bottom passivation layer under it.
Figure 10 is please referred to, forms adhesive layer 108 above the contact hole 107 and second passivation layer.
In the present embodiment, adhesive layer 108 covers side wall and the bottom of contact hole 107, while covering the second passivation layer 106 and working as
Before the part that is exposed.
Optionally, the material of adhesion metal layer can be Ti etc., generally form adherency gold using physical vapour deposition (PVD) at present
The technique for belonging to layer.Those skilled in the art can set the thickness of formed adhesion metal layer, example according to actual process demand
As adhesion metal layer with a thickness ofAdhesive layer 108 can also be made of Ti layers and TiN layer, the material not only with
The silica adhesive of contact hole side wall is preferable, also has good adhesiveness with subsequent metal layer, and can prevent metal layer
Diffusion/infiltration of middle metal.
Figure 11 and Figure 12 is please referred to, after completing contact hole technique, carries out the deposition of metal layer.Optionally, metal layer material
It can be tungsten.Specifically, in the adhesive layer disposed thereon initial metal layer 109, chemical machine is carried out to the initial metal layer
Tool grinding, removal are higher than the initial metal layer of the contact hole height component, form metal layer 110.For example, can be using chemistry
Vapor deposition utilizes SiH4And WF6Equal substances form deposited metal tungsten.
The present invention also includes a kind of semiconductor devices, and it is blunt to be provided with first as shown in figure 12, including substrate, on the substrate
Change layer；It is provided with a groove for exposing the substrate in first passivation layer, is filled with germanium layer in the groove；Metallic silicon
Compound layer is arranged above the germanium layer；Second passivation layer is arranged on the metal silicide layer；Contact hole is arranged in institute
It states in the second passivation layer and the part metal silicide layer above metal silicide layer, the lower surface of the contact hole is higher than
The upper surface of the germanium layer.The specific embodiment of the semiconductor devices can refer to the manufacture of the semiconductor devices in present specification
Method is implemented.
The present invention also includes a kind of electronic device comprising semiconductor devices above-mentioned.The electronic device, can be hand
Machine, tablet computer, laptop, net book, game machine, television set, VCD, DVD, navigator, camera, video camera, recording
Any electronic product such as pen, MP3, MP4, PSP or equipment are also possible to the intermediate products with above-mentioned semiconductor device, such as:
Cell phone mainboard etc. with the integrated circuit.
Metal silicide layer is arranged in the present invention above germanium layer, when forming contact hole, it is not necessary to exposure germanium layer, to protect
Germanium layer is not damaged.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (12)
1. a kind of semiconductor devices characterized by comprising substrate is provided with the first passivation layer on the substrate；
It is provided with a groove for exposing the substrate in first passivation layer, is filled with germanium layer in the groove；
Metal silicide layer is arranged above the germanium layer；
Second passivation layer is arranged on the metal silicide layer；
Contact hole is arranged in the second passivation layer above the metal silicide layer and the part metal silicide layer, institute
The lower surface for stating contact hole is higher than the upper surface of the germanium layer.
2. semiconductor devices as described in claim 1, which is characterized in that the metal silicide layer be tungsten silicon, nickel SiClx,
One of titanizing silicon, cobalt SiClx or a variety of combinations.
3. semiconductor devices as described in claim 1, which is characterized in that tool above the contact hole and second passivation layer
There is adhesive layer.
4. semiconductor devices as claimed in claim 3, which is characterized in that be provided with metal layer above the adhesive layer.
5. semiconductor devices as described in claim 1, which is characterized in that the thickness of the metal silicide layer is greater than
6. a kind of manufacturing method of semiconductor devices characterized by comprising
One substrate is provided, forms the first passivation layer over the substrate；
Etching states the first passivation layer to the substrate is exposed to form groove, forms germanium layer in the groove；
In the groove, metal silicide layer is formed above the germanium layer；
In second passivation layer of metal silicide layer disposed thereon；
It etches the second passivation layer and part metals silicide layer above the metal silicide layer and forms contact hole, the contact
The lower surface in hole is higher than the upper surface of the germanium layer.
7. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that in the groove, the germanium layer
Top forms metal silicide layer:
In the groove, silicon layer is formed above the germanium layer；
Transition metal is formed, annealing is implemented, makes the silicon layer and transition metal that chemical reaction occur and obtains metal silicide layer.
8. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that etching states the first passivation layer to exposing
After the substrate forms groove, germanium layer is formed using selective growth technique.
9. the manufacturing method of semiconductor devices as claimed in claim 7, which is characterized in that the silicon layer uses growth in situ work
Skill is formed.
10. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that the thickness of the metal silicide layer
Degree is greater than
11. the manufacturing method of semiconductor devices as claimed in claim 6, which is characterized in that in the contact hole and described
Adhesive layer is formed above two passivation layers.
12. the manufacturing method of semiconductor devices as claimed in claim 11, which is characterized in that further include: in the adhesive layer
Disposed thereon initial metal layer carries out chemical mechanical grinding to the initial metal layer, and removal is higher than contact hole height portion
The initial metal layer divided forms metal layer.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111229342A (en) * | 2020-01-17 | 2020-06-05 | 上海新微技术研发中心有限公司 | Method for manufacturing grating waveguide multi-micro-channel chip based on CMOS image sensing |
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