CN109949825A - Noise classification method based on the FPGA PCNN algorithm accelerated - Google Patents
Noise classification method based on the FPGA PCNN algorithm accelerated Download PDFInfo
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Abstract
The present invention is the noise classification method based on the FPGA PCNN algorithm accelerated, and this method includes the following steps: step 1, with sound pick-up outfit acquisition noise sample, and is trimmed into audio file；Step 2, when audio file carries out-frequency conversion；Step 3, feature extraction: being converted to grayscale image for noise pattern, and using gray value as the input of PCNN model, the acceleration of PCNN algorithm iteration process, and feature extraction of the output time series as different classes of noise are realized by FPGA；Step 4, each noise in noise sample is divided into training set and test set after step 3 handles 50-200 output time series of iteration；Step 5, the time series of each iteration of training set is averaging and is used as reference template, the Euclidean distance between the time series of test set and the time series of reference template is calculated, is determined as same noise when Euclidean distance is less than noise class threshold value, and export recognition result.This method shortens the feature extraction time, has saved time cost.
Description
Technical field
The present invention relates to noise classification technical field, the noise classification of specifically a kind of PCNN algorithm accelerated based on FPGA
Method.
Background technique
Problem of noise pollution all brings serious harm to the even entire ecological environment of human society.But noise pollution
Matter is very special, invisible to can not touch, and will not generate pollutant, and the range of analysis is wide, and type is more, has real-time.
Noise pollution can constitute harm to people, animal, instrument and meter and building, and noise not only can cause to damage to hearing, also
A variety of carcinogenic fatal diseases can be induced.And Chinese population is intensive, living environment is complicated, harm of the ordinarily resident to noise pollution
Consciousness is weak, and influence of the noise pollution to the people is very serious in this day and age.The classification of city noise is and modern
The quality of life of the people improves interwoveness, and it is strong that the classification of noise is not only conducive to improvement noise pollution situation raising people's body
Health is additionally favorable for the equity that the people safeguard itself using legal means, mitigates noise pollution situation.But China is at present for making an uproar
The attention of sound pollution and prevention and treatment system are perfect not enough, need efficient one kind, accuracy height, conducive to hardware realization noise classification side
Method.
Pulse Coupled Neural Network has been promoted to the research of the small-sized mammalians visual cortex such as cat since the nineties
(PCNN) generation and development, in digital image understanding field extensive application.
But it is few based on the achievement that PCNN identifies sound classification, more only it is applied to speech recognition, from present
Achievement and document from the point of view of, in method, the suitable situation of parameter selection, have higher discrimination for speech recognition.Such as
(speech recognition system design [J] of Zhang Xiaojun, Tao Zhi, Gu Jihua, the et al. based on PCNN and DTW is logical by Zhang Xiaojun, Tao Zhi etc.
Letter technology, 2007 (4): 60-62.) the speech recognition system design based on PCNN and DTW, utilize improved PCNN extract
Language atlas image feature is known by the classification that dynamic time warping (DTW) carries out voice later as the characteristic sequence after extracting
Not.Liu Kun, (alone word voice Study of recognition [J] the computer engineering of Liu Kun, inscription on ancient bronze objects mark based on PCNN and RBF such as inscription on ancient bronze objects mark
With design, 2008,29 (24): 6298-6301.) the alone word voice Study of recognition based on PCNN and RBF propose a kind of benefit
Being aided with traditional RBF nerve network with the time series that simplified PCNN extracts sonagram spectrum realizes isolating language
The identification of sound.But above several method time cost is bigger, the process time-consuming of mainly PCNN network iteration is bigger,
And according to existing literature almost without being related to the hardware realization of classifier.
Summary of the invention
In view of the deficiencies of the prior art, the present invention solves the technical problem of, provide it is a kind of based on FPGA accelerate
The noise classification method of PCNN algorithm.Using PCNN algorithm extraction time sequence as the characteristic sequence of noise pattern, pass through
The process of FPGA Accelerated iteration greatly shortens the feature extraction time, has saved time cost.
The present invention solve the technical problem the technical solution adopted is that: provide it is a kind of based on FPGA accelerate PCNN algorithm
Noise classification method, this method includes the following steps:
Step 1, with sound pick-up outfit acquisition noise sample, and it is trimmed into the audio file within 300ms-10s；
Step 2, when audio file carries out-and frequency conversion: Short Time Fourier Transform is carried out to audio file, obtains noise spectrum
Figure；
Step 3, feature extraction: being converted to grayscale image for noise pattern, using gray value as the input of PCNN model, leads to
Cross the acceleration that FPGA realizes PCNN algorithm iteration process, and feature extraction of the output time series as different classes of noise；
The detailed process of the acceleration that PCNN algorithm iteration process is realized by FPGA is:
1) FPGA circuitry is in idle condition, and when reset signal is effective, all variables of FPGA circuitry reset, reset signal
Enter init state after drawing high, each variable is initialized；
2) after initializing, the computing module in FPGA is jumped to, computing module is accomplished that the iteration mistake of PCNN model
Journey, gray value is iterated acceleration as input in computing module, until reaching the number of iterations being set in advance, jumps and makes the return trip empty
Not busy state completes iteration accelerator；
Step 4, each noise in noise sample is divided into after step 3 handles 50-200 output time series of iteration
Training set and test set；
Step 5, the time series of each iteration of training set is averaging and is used as reference template, calculate the time sequence of test set
Euclidean distance between column and the time series of reference template is determined as same when Euclidean distance is less than noise class threshold value
Noise, and export recognition result.
Compared with prior art, the beneficial effects of the present invention are:
The present invention, and will treated noised audio by Short Time Fourier Transform by the pretreatment to noise sample
Noise pattern is converted to, noise pattern is converted into grayscale image, using gray value as the input of PCNN model, passes through FPGA
The pulse coupled neural algorithm of realization is iterated acceleration processing, and output time series are as the feature extracted.Pass through 50-200
The time series of secondary iteration output is divided into test set and training set, determines reference template, test set by training set as feature
PCNN model is inputted, the time series of test set is exported, calculates the time series of test set and the time series of reference template
Euclidean distance (Euclidean Distance) exports recognition result.Pass through the time series conduct exported after PCNN algorithm
The feature of classification sound, has time, scale etc. indeformable, the classification of noise may be implemented, and accelerate by FPGA
The iterative process of PCNN algorithm.The image for being 8 based on the FPGA PCNN algorithm process 128*128 gray scale realized, iteration 100 times
16ms is taken around, time cost is greatly saved.The present invention not only ensure that the accuracy of classification also improves the speed of classification
Degree, is more suitable for the realization of hardware classifier.
Detailed description of the invention
Method of the invention is illustrated with reference to the accompanying drawing.
Fig. 1 is FPGA circuitry modularized design figure.
Fig. 2 is the single neuron models figure of PCNN algorithm.
Fig. 3 is FPGA circuitry state transition graph.
Fig. 4 is spectrogram gray value matrix convolution calculating process schematic diagram.
Fig. 5 is the entire block diagram for the PCNN algorithm noise classification method that FPGA accelerates.
Specific embodiment
Below with reference to embodiment, the invention will be further described, but not in this, as the limit to the application protection scope
It is fixed.
The present invention is based on the noise classification method of the FPGA PCNN algorithm accelerated, this method includes the following steps:
Step 1, with sound pick-up outfit acquisition noise sample, and it is trimmed into the audio file within 300ms-10s；
Step 2, when audio file carries out-and frequency conversion: Short Time Fourier Transform is carried out to audio file, obtains noise spectrum
Figure；
Step 3, feature extraction: being converted to grayscale image for noise pattern, using gray value as the input of PCNN model, leads to
Cross the acceleration that FPGA realizes PCNN algorithm iteration process, and feature extraction of the output time series as different classes of noise；
The detailed process of the acceleration that PCNN algorithm iteration process is realized by FPGA is:
1) FPGA circuitry is in idle condition, and when reset signal is effective, all variables of FPGA circuitry reset, reset signal
Enter init state after drawing high, each variable is initialized；
2) after initializing, the computing module in FPGA is jumped to, computing module is accomplished that the iteration mistake of PCNN model
Journey, in computing module gray value as input is iterated accelerations, until reach the number of iterations being set in advance (here change
Generation number can be determining according to accuracy and the requirement of time, the more preferable accuracy of effect of the bigger time-consuming more macrotaxonomy of the number of iterations
It is higher), idle state is jumped back to, iteration accelerator is completed；
Step 4, each noise in noise sample is divided into after step 3 handles 50-200 output time series of iteration
Training set and test set can guarantee effective extraction time sequence and can be reduced time cost.
Step 5, the time series of each iteration of training set is averaging and is used as reference template, calculate the time sequence of test set
Euclidean distance between column and the time series of reference template is determined as same when Euclidean distance is less than noise class threshold value
Noise, and export recognition result.
The establishment process of above-mentioned PCNN model can use the prior art.
Most of different image is different from by the time series that PCNN algorithm iteration extracts, therefore can be calculated by this
Method carries out the identification and classification of noise, and has higher accuracy rate.When the present invention first carries out noisy samples-frequency conversion, it will
Input of the gray value of noise pattern as PCNN algorithm.Noise pattern by the iteration of PCNN algorithm export image when
Between sequence as feature, and FPGA is combined to realize the acceleration processing of PCNN algorithm iteration.The time series extracted after iteration is led to
The Euclidean distance crossed between calculating and reference template is classified, and output reliability result.
Embodiment
The present embodiment uses Vivado 2014.4 and MATLAB using 8 system of windows as program development software (PDS) environment
R2010a is as program development platform, by microphone records city noise as experimental data.
The present embodiment is included the following steps: based on the noise classification method of the FPGA PCNN algorithm accelerated
With sound pick-up outfits such as microphones, acquisition noise sample carries out rough cut, and editing is the sound within 300ms-10s
Frequency file.
By the audio file after editing, when progress-frequency conversion, i.e. progress Short Time Fourier Transform.First to noised audio
File framing, noised audio are generally the non-stationary signal of time-varying, so framing length can be chosen between 10ms-30ms, and it can
It is chosen according to noised audio length；Adding window is carried out to the noised audio after framing in next step, using Hanning window, window is long to be equal to frame
It is long.Fourier transformation finally is carried out to each frame, that is, completes the Short Time Fourier Transform to noised audio, obtains noise spectrum
Figure.
Noise pattern is converted into gray scale picture by MATLAB, exports picture gray value, after storage, is calculated as PCNN
The input of method.The detailed process for realizing the acceleration of PCNN algorithm iteration process by FPGA is:
FPGA circuitry is divided into these three modules of control module, computing module and memory module；Control module is responsible for coordinating whole
The normal work of a circuit, computing module complete the iterative function of PCNN algorithm, and the data generated in calculating are stored in storage mould
Block；Control module and the two-way communication of serial ports receiving module, while control module is directly connect with memory module, is responsible for coordinating FPGA
The normal work of entire circuit, serial ports receiving module connects computing module and memory module, computing module are two-way with memory module
Communication.Picture gray value is inputted FPGA circuitry by serial ports receiving module and calculates time series by PC machine, i.e. control module provides
Picture gray value is given to computing module by serial ports receiving module by the instruction of serial ports receiving module, is completed when computing module calculates
When, control module can send control signal and control computing module calling memory module by serial ports receiving module, while calculate mould
Block is stored in memory module for the data generated are calculated；FPGA circuitry will be calculated further through control module control memory module and be exported
Time series PC machine, such as Fig. 1 are uploaded to by serial ports receiving module.
The calculation formula of the archetype of PCNN algorithm is as follows:
Uij[n]=Fij[n](1+βLij[n])
In formula, Fij[n] is the feed back input of corresponding (i, j) a neuron；N is the number of iteration；SijCorrespondence image
In (i, j) a pixel gray value；M and W is link weighting coefficient matrix, also referred to as convolution kernel, indicates central nervous
The member interactional size of peripheral neurons adjacent thereto；αFAnd αLIt is normal for the channel neuron F and L channel time exponential damping
Number；K, l correspond to the coordinate of peripheral neurons；Bonding strength constant of the β between cynapse；L is linear input item；VFAnd VLRespectively
For Fij[n] and LijThe intrinsic potential of [n]；TijCan [n] is the required dynamic threshold of excitation pulse generation；Yij[n] is PCNN arteries and veins
Punching output, YijThe value of [n] is 0 or 1,0 expression no pulse output, and 1 indicates pulse output.
Single vector-quantities are converted by the two-value pulse after each iteration of PCNN model, are defined
For " time series ".
Thus formula is found out, time series has counted piece image in pixel of lighting a fire after PCNN model treatment every time
Total number, and the sequence has rotation, mirror image, translation and scale invariability, can characterize the feature of gray level image, realizes ash
Spend image classification and characteristic matching.Therefore the classification of noise can be realized using time series as the feature of noise spectrum figure.
PCNN network is also to be composed of single neuron, and single neuron receives the feedback of peripheral neurons, nerve
Interaction constitutes network between member.Single PCNN algorithm neuron models such as Fig. 2, is divided into three parts, and importation connects defeated
Enter, impulse generator.Importation by (i, j) a pixel in image gray value, that is, SijWith the influence of peripheral neurons
YijComposition, each of image pixel correspond to each neuron of neural network.The simulation of connection importation is nerve
Activity inside member.Impulse generator part mainly passes through threshold decision device and is judged, decides whether to export pulse, Y output
Pulse output is indicated when being 1.
The computing module of calculation formula design FPGA circuitry based on PCNN algorithm archetype, defines matrix convolution and calculates
For K, linear input item is L, and judgement input is U, dynamic threshold T, feed back input F, and pulse output is Y, and time series is defeated
It is out S (n), inputs as DM.
Due to the needs of circuit design, the calculation formula by PCNN archetype is needed to be converted into the language of computer calculating
Speech, is provided by the form of MATLAB code.
1, matrix convolution calculates: K=conv2 (Y, W, ' same')；
2, linear input item: L=exp (- alpha_L) * L+vL*K；
3, judgement input: U=F.* (1+beta*L)；
4, dynamic threshold: T=exp (- alpha_T) * T+vT*Y；
5, pulse exports: Y=im2double (U > T)；
6, feed back input: F=exp (- alpha_F) * F+vF*K+DM；
7, time series exports: S (n)=sum (sum (Y))；
Time series exports in order to obtain, and the above calculating step needs repeat.
Wherein the constant of storage required for computing module to memory module is alpha_L, alpha_Theta, alpha_F,
Beta, W, vL, vF, vTheta, exp (- alpha_L), exp (- alpha_Theta), exp (- alpha_F).The noise of input
Sample spectrogram gray value is 8bit, other than vTheat is 16bit integer, other constants all indicate with 8bit binary fraction,
Storage.
It needs to store to the variable of memory module and has K, L, U, T, Y, F, the size of memory space is the size of input picture.
K, L is 16bit (8 integers, 8 decimals), and U, T, F are 24bit (16 integers, 8 decimals), and Y and DM are that (8 whole by 8bit
Number).
Entire circuit is divided into four states, idle state, and init state calculates state, output state.
The state of FPGA circuitry is converted, and when circuit is in idle condition, and reset signal is effective, all variables are reset to 0,
Init state is jumped to when reset signal is invalid.
Init state gives the attached initial value of variable, and the number of iterations is initialized as 0, when write enable effective when, jump to calculating shape
State.
Calculating state, calculating state are mainly realized by computing module.The gray value of noise pattern is inputted into computing module,
Computing module mainly includes linear calculating L, T, F that matrix convolution calculates K and other matrixes.State conversion such as Fig. 3.
Matrix convolution calculates K, K=conv2 (Y, W, ' same') in computing module.By control module output signal control three
A line buffer and two counters realize that matrix convolution calculates the function of K jointly, and one of counter is for calculating gray scale
The matrix line number that convolution is crossed, another counter generate line buffer address.Noise pattern gray value is three row data
Enter the convolutional calculation that matrix carries out matrix simultaneously, but handle the first row, when gray value of the second row correctly ties in order to obtain
Fruit exports corresponding signal by control module and matrix corresponding line is all set as zero, similarly first row and secondary series data processing
When also do corresponding operating.Specific such as Fig. 4.
It further include linear calculating input L, T, F of matrix in computing module.The linear calculating process of these matrixes is all class
As.For calculating linear input item L.
For calculating linear input item L, L=exp (- alpha_L) * L+vL*K；Then need two multipliers and one
Adder is completed to calculate work.It should be noted that the representation and multiplier and adder of number export cut position problem.L is
16 integers, exp_alpha_L are 8 decimals, and output L is 16 integers.Then multiplication result retains 16 high, i.e., only retains whole
Number.To improve computational accuracy, cut position operation can be completed in adder output par, c.
When the calculating of computing module completion variable, address is provided for variable storage to memory module by counter.
Memory module is made of RAM is responsible for storage constant value and variate-value.
Control module is mainly made of counter and state machine, is responsible for output control signal, and counter completes memory
Address generates work (output of counter is the address of memory), the read-write of memory control state machine and computing module
It is enabled.So that computing module and memory module is worked normally and completes PCNN algorithm iteration accelerator.State machine other
State is converted to be completed by the control of counter overflow signal, and the mould of counter is the pixel number of image, and counting to overflow indicates
Complete the calculating or processing task of piece image all pixels point.
Time series is the summation of the igniting number after each iteration of gray level image, in the case where calculating pulse output Y,
Firing pulse counter counts, and the calculated result of Y is that a pixel of 1 namely image is lighted a fire, and firing pulse counter adds
One.I.e. every iteration is primary, and firing pulse counter exports current iteration firing pulse number, is a value in time series.Often
It completes an iteration iteration count and adds one, after reaching scheduled maximum number of iterations, complete entire time series
Output.
Using the time series exported after 50-200 iteration as the feature of noise map.The feature for completing noise map mentions
It takes.
Characteristic sequence after extraction is divided into training set and test set, the time series of each iteration of training set is averaging
As reference template, the Euclidean distance (Euclidean between the time series of test set and the time series of reference template is calculated
Distance, ED) is defined as:
Wherein, n is the number of iterations；EaFor the time series of reference template；EbFor the time series of test set.
It is determined as same noise when Euclidean distance is less than threshold value, and exports recognition result.
Recognition decision is exactly with threshold value comparison as a result, calculating the reference template of the time series and various noises of test set
Between Euclidean distance, be determined as same noise like, the result of output category if it is less than noise class threshold value.
System entire block diagram such as Fig. 5.
Noise class threshold value is the boundary numerical value of the various classification noises counted by big data early period in the present invention.
Unaccomplished matter of the present invention is well-known technique.
Claims (3)
1. a kind of noise classification method of the PCNN algorithm accelerated based on FPGA, this method are included the following steps:
Step 1, with sound pick-up outfit acquisition noise sample, and it is trimmed into the audio file within 300ms-10s；
Step 2, when audio file carries out-and frequency conversion: Short Time Fourier Transform is carried out to audio file, obtains noise pattern；
Step 3, feature extraction: being converted to grayscale image for noise pattern, using gray value as the input of PCNN model, passes through
FPGA realizes the acceleration of PCNN algorithm iteration process, and feature extraction of the output time series as different classes of noise；
The detailed process of the acceleration that PCNN algorithm iteration process is realized by FPGA is:
1) FPGA circuitry is in idle condition, and when reset signal is effective, all variables of FPGA circuitry reset, and reset signal is drawn high
Enter init state afterwards, each variable is initialized；
2) after initializing, the computing module in FPGA is jumped to, computing module is accomplished that the iterative process of PCNN model,
Gray value is iterated acceleration as input in computing module, until reaching the number of iterations being set in advance, jumps back to idle shape
State completes iteration accelerator；
Step 4, each noise in noise sample is divided into training after step 3 handles 50-200 output time series of iteration
Collection and test set；
Step 5, the time series of each iteration of training set is averaging and is used as reference template, calculate the time series of test set with
Euclidean distance between the time series of reference template is determined as same make an uproar when Euclidean distance is less than noise class threshold value
Sound, and export recognition result.
2. the noise classification method of the PCNN algorithm according to claim 1 accelerated based on FPGA, which is characterized in that in short-term
The process of Fourier transformation is；First to noised audio file framing, framing length is 10ms-30ms；In next step to framing it
Noised audio afterwards carries out adding window, and using Hanning window, window is long to be equal to frame length, finally carries out Fourier transformation to each frame, i.e., complete
At the Short Time Fourier Transform to noised audio, noise pattern is obtained.
3. the noise classification method of the PCNN algorithm according to claim 1 accelerated based on FPGA, which is characterized in that described
FPGA circuitry includes control module, computing module and memory module；Control module is responsible for coordinating the normal work of entire circuit, meter
The iterative function that module completes PCNN algorithm is calculated, the data generated in calculating are stored in memory module；Control module gives deposit respectively
Module, serial ports receiving module signal are stored up, is responsible for coordinating the normal work of the entire circuit of FPGA；PC machine will by serial ports receiving module
Picture gray value inputs FPGA circuitry and calculates time series, and FPGA circuitry will calculate defeated further through control module control memory module
Time series out is uploaded to PC machine by serial ports receiving module.
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Application publication date: 20190628 |