CN109949825A - Noise classification method based on FPGA-accelerated PCNN algorithm - Google Patents

Abstract

The present invention is a noise classification method based on an FPGA-accelerated PCNN algorithm. The method includes the following steps: Step 1, use a recording device to collect noise samples, and edit them into audio files; Step 2, the audio files are time-frequency converted; Step 3 , feature extraction: convert the noise spectrogram into a grayscale image, use the grayscale value as the input of the PCNN model, realize the acceleration of the iterative process of the PCNN algorithm through FPGA, and output the time series as the feature extraction of different types of noise; step 4, the Each noise in the noise sample is divided into a training set and a test set after being processed and iterated 50-200 times in step 3 to output the time series; in step 5, the time series of each iteration of the training set are averaged as a reference template, and the The Euclidean distance between the time series and the time series of the reference template. When the Euclidean distance is less than the noise category threshold, it is determined to be the same noise, and the recognition result is output. This method shortens the feature extraction time and saves time cost.

Description

Noise classification method based on FPGA-accelerated PCNN algorithm

technical field

The invention relates to the technical field of noise classification, in particular to a noise classification method based on an FPGA-accelerated PCNN algorithm.

Background technique

Noise pollution has brought serious harm to human society and even the entire ecological environment. However, the nature of noise pollution is very special. It cannot be seen or touched, and no pollutants will be produced. The distribution of pollution sources is wide, with many types, and it is real-time. Noise pollution can cause harm to people, animals, instruments and buildings. Noise can not only cause hearing damage, but also induce a variety of carcinogenic and deadly diseases. In China, the population is dense, the living environment is complex, and the ordinary residents have weak awareness of the harm of noise pollution. In today's era, the impact of noise pollution on the people has been very serious. The classification of urban noise has been inseparable from the improvement of the quality of life of modern people. The classification of noise is not only conducive to improving noise pollution and improving people's health, but also helping people to use legal means to protect their rights and reduce noise pollution. However, my country's current attention and prevention system for noise pollution is not perfect, and an efficient, high-accuracy, and hardware-friendly noise classification method is needed.

Since the 1990s, the research on the visual cortex of small mammals such as cats has prompted the generation and development of Pulse Coupled Neural Networks (PCNNs), which are widely used in the field of digital image recognition.

However, there are not many achievements in voice classification and recognition based on PCNN, and only some are applied to voice recognition. From the current results and literature, it has a high recognition rate for voice recognition when the method and parameter selection are appropriate. Such as Zhang Xiaojun, Tao Zhi, etc. (Zhang Xiaojun, Tao Zhi, Gu Jihua, et al. Design of speech recognition system based on PCNN and DTW [J]. Communication Technology, 2007(4): 60-62.) Speech based on PCNN and DTW In the design of the recognition system, the improved PCNN is used to extract the features of the language map and images as the extracted feature sequence, and then the classification and recognition of speech is performed by dynamic time warping (DTW). Liu Kun, Jin Wenbiao, etc. (Liu Kun, Jin Wenbiao. Research on isolated word speech recognition based on PCNN and RBF [J]. Computer Engineering and Design, 2008, 29(24): 6298-6301.) Isolated word based on PCNN and RBF In the speech recognition research, a simplified PCNN is used to extract the time series of the language map and the traditional radial basis function RBF neural network is used to realize the isolated speech recognition. However, the time cost of the above methods is relatively high, mainly because the iterative process of the PCNN network is relatively time-consuming, and according to the existing literature, the hardware implementation of the classifier is hardly involved.

SUMMARY OF THE INVENTION

Aiming at the deficiencies of the prior art, the main technical problem to be solved by the present invention is to provide a noise classification method based on the FPGA-accelerated PCNN algorithm. The PCNN algorithm is used to extract the time series as the feature sequence of the noise spectrogram, and the iterative process is accelerated by FPGA, which greatly shortens the feature extraction time and saves the time cost.

The technical solution adopted by the present invention to solve the technical problem is to provide a noise classification method based on an FPGA-accelerated PCNN algorithm, the method comprising the following steps:

Step 1, use a recording device to collect noise samples, and edit them into audio files within 300ms-10s;

Step 2, time-frequency conversion is performed on the audio file: short-time Fourier transform is performed on the audio file to obtain a noise spectrogram;

Step 3, feature extraction: convert the noise spectrogram into a grayscale image, use the grayscale value as the input of the PCNN model, realize the acceleration of the iterative process of the PCNN algorithm through FPGA, and output the time series as the feature extraction of different types of noise;

The specific process of realizing the acceleration of the iterative process of the PCNN algorithm through the FPGA is:

1) The FPGA circuit is in an idle state. When the reset signal is valid, all variables of the FPGA circuit are reset. After the reset signal is pulled high, it enters the initialization state and initializes each variable;

2) After initialization, jump to the calculation module in the FPGA. The calculation module implements the iterative process of the PCNN model. The gray value in the calculation module is used as the input for iterative acceleration until the number of iterations set in advance is reached. Jump back In idle state, complete the iterative acceleration process;

Step 4: Divide each noise in the noise samples into a training set and a test set after processing and iterating the output time series for 50-200 times in Step 3;

Step 5: Average the time series of each iteration of the training set as a reference template, and calculate the Euclidean distance between the time series of the test set and the time series of the reference template. When the Euclidean distance is less than the noise category threshold, it is determined to be the same noise. , and output the recognition result.

Compared with the prior art, the beneficial effects of the present invention are:

In the present invention, the noise samples are preprocessed, and the processed noise audio is converted into a noise spectrogram through short-time Fourier transform, the noise spectrogram is converted into a grayscale image, and the grayscale value is used as the input of the PCNN model, The pulse coupled neural algorithm implemented by FPGA performs iterative acceleration processing, and outputs the time series as the extracted features. The time series output through 50-200 iterations is used as a feature, which is divided into a test set and a training set. The reference template is determined through the training set, the test set is input to the PCNN model, the time series of the test set is output, and the time series of the test set and the reference template are calculated. The Euclidean Distance of the time series, and output the recognition result. The time series output after the PCNN algorithm is used as the feature of the classified sound, which has no deformation in time and scale, and can realize the classification of noise, and the iterative process of the PCNN algorithm is accelerated by FPGA. The PCNN algorithm implemented based on FPGA processes 128*128 grayscale images with 8 bits, and it takes about 16ms to iterate 100 times, which greatly saves time and cost. The invention not only ensures the accuracy of classification but also improves the speed of classification, and is more suitable for the realization of hardware classifiers.

Description of drawings

The method of the present invention will be described in detail below with reference to the accompanying drawings.

Figure 1 shows the modular design of the FPGA circuit.

Figure 2 is a diagram of a single neuron model of the PCNN algorithm.

Figure 3 is a state transition diagram of the FPGA circuit.

FIG. 4 is a schematic diagram of a convolution calculation process of a gray value matrix of a spectrogram.

Figure 5 is the overall block diagram of the FPGA-accelerated PCNN algorithm noise classification method.

Detailed ways

The present invention will be further described below with reference to the examples, but this is not intended to limit the protection scope of the present application.

The present invention is based on the noise classification method of the PCNN algorithm accelerated by FPGA, and the method comprises the following steps:

Step 1, use a recording device to collect noise samples, and edit them into audio files within 300ms-10s;

Step 2, time-frequency conversion is performed on the audio file: short-time Fourier transform is performed on the audio file to obtain a noise spectrogram;

Step 3, feature extraction: convert the noise spectrogram into a grayscale image, use the grayscale value as the input of the PCNN model, realize the acceleration of the iterative process of the PCNN algorithm through FPGA, and output the time series as the feature extraction of different types of noise;

The specific process of realizing the acceleration of the iterative process of the PCNN algorithm through the FPGA is:

1) The FPGA circuit is in an idle state. When the reset signal is valid, all variables of the FPGA circuit are reset. After the reset signal is pulled high, it enters the initialization state and initializes each variable;

2) After initialization, jump to the calculation module in the FPGA. The calculation module implements the iterative process of the PCNN model. The gray value in the calculation module is used as the input for iterative acceleration until the number of iterations set in advance (the iteration here is reached). The number of times can be determined according to the requirements of accuracy and time, the larger the number of iterations, the more time-consuming the classification, the better the classification effect and the higher the accuracy), jump back to the idle state, and complete the iterative acceleration process;

Step 4: Divide each noise in the noise samples into a training set and a test set after processing and iterating the output time series for 50-200 times in step 3, which can ensure the effective extraction of time series and reduce the time cost.

Step 5: Average the time series of each iteration of the training set as a reference template, and calculate the Euclidean distance between the time series of the test set and the time series of the reference template. When the Euclidean distance is less than the noise category threshold, it is determined to be the same noise. , and output the recognition result.

The establishment process of the above-mentioned PCNN model can adopt the existing technology.

The time series extracted by the iteratively extracted PCNN algorithm for most different images are different, so this algorithm can be used to identify and classify noise with high accuracy. The present invention firstly performs time-frequency conversion on the noise samples, and uses the gray value of the noise spectrogram as the input of the PCNN algorithm. The noise spectrogram is characterized by the time series of the iterative output image of the PCNN algorithm, and combined with the FPGA to realize the accelerated processing of the PCNN algorithm iteration. The time series extracted after iteration is classified by calculating the Euclidean distance from the reference template, and the reliability result is output.

Example

In this embodiment, the Windows 8 system is used as the software environment for program development, Vivado 2014.4 and MATLABR2010a are used as the program development platform, and urban noise is recorded through a microphone as experimental data.

The noise classification method based on the FPGA-accelerated PCNN algorithm in this embodiment includes the following steps:

Use recording equipment such as a microphone to collect noise samples and perform preliminary editing, which is an audio file within 300ms-10s.

The clipped audio file is subjected to time-frequency conversion, that is, short-time Fourier transform. First, the noise audio file is divided into frames. The noise audio is generally a time-varying non-stationary signal, so the frame length can be selected between 10ms and 30ms, which can be selected according to the length of the noise audio; the next step is to add the noise audio after framing. Window, using Hanning window, the window length is equal to the frame length. Finally, Fourier transform is performed on each frame, that is, the short-time Fourier transform of the noise audio is completed, and the noise spectrogram is obtained.

Convert the noise spectrogram to a grayscale image through MATLAB, output the grayscale value of the image, and store it as the input of the PCNN algorithm. The specific process of accelerating the iterative process of the PCNN algorithm through FPGA is as follows:

The FPGA circuit is divided into three modules: control module, calculation module and storage module; the control module is responsible for coordinating the normal operation of the entire circuit, the calculation module completes the iterative function of the PCNN algorithm, and the data generated in the calculation is stored in the storage module; the control module and the serial port The receiving module communicates in two directions, and the control module is directly connected with the storage module, which is responsible for coordinating the normal operation of the entire circuit of the FPGA. The serial receiving module connects the computing module and the storage module, and the computing module and the storage module communicate in two directions. The PC inputs the image gray value into the FPGA circuit through the serial port receiving module to calculate the time series, that is, the control module gives the serial port receiving module instruction to send the image gray value to the calculation module through the serial port receiving module. When the calculation module completes the calculation, the control module It will send a control signal through the serial port receiving module to control the calculation module to call the storage module, and the calculation module will store the data generated by the calculation in the storage module; the FPGA circuit controls the storage module through the control module to upload the time series of the calculation output to the PC through the serial port receiving module machine, as shown in Figure 1.

The calculation formula of the original model of the PCNN algorithm is as follows:

U _ij [n]=F _ij [n](1+βL _ij [n])

In the formula, F _ij [n] is the feedback input of the corresponding (i, j)th neuron; n is the number of iterations; S _ij corresponds to the gray value of the (i, j)th pixel in the image; M and W are the link weighting coefficient matrix, also known as the convolution kernel, indicating the magnitude of the interaction between the central neuron and its adjacent peripheral neurons; α _F and α _L are the time exponential decay constants of the neuron F channel and L channel; k , l corresponds to the coordinates of surrounding neurons; β is the connection strength constant between synapses; L is the linear input term; V _F and _VL are the intrinsic potentials of F _ij [n] and L _ij [n], respectively; T _ij [n] is the dynamic threshold required for excitation pulse generation; Y _ij [n] is the PCNN pulse output, and the value of Y _ij [n] is 0 or 1, 0 means no pulse output, 1 means there is pulse output.

Convert the binary pulse after each iteration of the PCNN model into a single vector, define

for "time series".

From this formula, it can be seen that the time series counts the total number of ignition pixels in an image after each processing by the PCNN model, and the sequence has rotation, mirroring, translation and scale invariance, which can characterize the characteristics of grayscale images. , to achieve grayscale image classification and feature matching. Therefore, the time series can be used as the characteristics of the noise spectrum to realize the classification of noise.

The PCNN network is also composed of a single neuron. A single neuron receives feedback from surrounding neurons, and the interaction between neurons constitutes a network. The neuron model of a single PCNN algorithm is shown in Figure 2, which is divided into three parts, the input part, the connection input, and the pulse generator. The input part consists of the gray value of the (i,j)th pixel in the image, namely S _ij and the influence of surrounding neurons Y _ij , and each pixel in the image corresponds to each neuron of the neural network. The connected input part simulates the activity inside the neuron. The pulse generator part is mainly judged by the threshold judger to decide whether to output pulses. When the Y output is 1, it means that there is pulse output.

Based on the calculation formula of the original model of the PCNN algorithm, the calculation module of the FPGA circuit is designed. The matrix convolution calculation is defined as K, the linear input is L, the decision input is U, the dynamic threshold is T, the feedback input is F, the pulse output is Y, and the time The sequence output is S(n) and the input is DM.

Due to the needs of circuit design, it is necessary to convert the calculation formula of the original PCNN model into a computer calculation language, which is given in the form of MATLAB code.

1. Matrix convolution calculation: K=conv2(Y,W,'same');

2. Linear input item: L=exp(-alpha_L)*L+vL*K;

3. Judgment input: U=F.*(1+beta*L);

4. Dynamic threshold: T=exp(-alpha_T)*T+vT*Y;

5. Pulse output: Y=im2double(U>T);

6. Feedback input: F=exp(-alpha_F)*F+vF*K+DM;

7. Time series output: S(n)=sum(sum(Y));

In order to obtain the time series output, the above calculation steps need to be repeated.

The constants that the calculation module needs to store in the storage module are alpha_L, alpha_Theta, alpha_F, beta, W, vL, vF, vTheta, exp(-alpha_L), exp(-alpha_Theta), exp(-alpha_F). The grayscale value of the input noise sample spectrogram is 8 bits. Except for vTheat, which is a 16-bit integer, other constants are represented and stored by 8-bit binary decimals.

The variables that need to be stored in the storage module are K, L, U, T, Y, F, and the size of the storage space is the size of the input image. K and L are 16 bits (8-bit integers with 8 decimals), U, T, and F are 24 bits (16-bit integers with 8 decimals), and Y and DM are 8 bits (8-bit integers).

The whole circuit is divided into four states, idle state, initialization state, calculation state, and output state.

The state transition of the FPGA circuit, when the circuit is in an idle state and the reset signal is valid, all variables are reset to 0, and jump to the initialization state when the reset signal is invalid.

In the initialization state, the initial value is attached to the variable, and the number of iterations is initialized to 0. When the write enable is valid, it jumps to the calculation state.

Calculation state, the calculation state is mainly realized by the calculation module. Input the gray value of the noise spectrogram into the calculation module. The calculation module mainly includes the matrix convolution calculation K and the linear calculation L, T, and F of other matrices. The state transition is shown in Figure 3.

Matrix convolution calculation K, K=conv2(Y,W,'same') in the calculation module. Three line buffers and two counters are controlled by the output signal of the control module to realize the function of matrix convolution calculation K. One of the counters is used to calculate the number of lines that have been convoluted by the grayscale matrix, and the other counter generates the line buffer address. . The gray value of the noise spectrogram is that three lines of data enter the matrix at the same time to perform the convolution calculation of the matrix, but in order to obtain the correct result when processing the gray value of the first line and the second line, the control module outputs the corresponding signal to make the matrix corresponding. All rows are set to zero, and corresponding operations are also performed when processing the data in the first and second columns. Specifically as shown in Figure 4.

The calculation module also includes linear calculation inputs L, T, F of the matrix. The linear calculation process for these matrices is similar. Take computing the linear input term L as an example.

Taking the calculation of the linear input item L as an example, L=exp(-alpha_L)*L+vL*K; then two multipliers and one adder are required to complete the calculation. Note the way the numbers are represented and the truncation of the outputs of the multipliers and adders. L is a 16-bit integer, exp_alpha_L is an 8-bit decimal, and the output L is a 16-bit integer. Then the multiplication result retains the upper 16 bits, that is, only integers are retained. In order to improve the calculation accuracy, the truncation operation can be done in the output part of the adder.

When the calculation module completes the calculation of the variable, the address is given by the counter to store the variable in the storage module.

The storage module is composed of RAM and is responsible for storing constant values and variable values.

The control module is mainly composed of a counter and a state machine, which is responsible for outputting control signals. The counter completes the address generation of the memory (the output of the counter is the address of the memory), and the state machine controls the reading and writing of the memory and the enabling of the calculation module. The computing module and the storage module can work normally to complete the iterative acceleration process of the PCNN algorithm. Other state transitions of the state machine are completed by the control of the counter overflow signal, the modulo of the counter is the number of pixels of the image, and the overflow of the count indicates that the calculation or processing task of all pixels of an image has been completed.

The time series is the sum of the ignition numbers after each iteration of the grayscale image. In the case of calculating the pulse output Y, the ignition pulse counter counts, and the calculation result of Y is 1, that is, a pixel of the image is ignited, and the ignition pulse counter is added. one. That is, for each iteration, the ignition pulse counter outputs the number of ignition pulses in this iteration, which is a value in the time series. After each iteration is completed, the iteration counter is incremented by one until the predetermined maximum number of iterations is reached, and the output of the entire time series is completed.

The time series output after 50-200 iterations is used as the feature of the noise map. Complete the feature extraction of the noise map.

Divide the extracted feature sequence into a training set and a test set, average the time series of each iteration of the training set as a reference template, and calculate the Euclidean Distance (Euclidean Distance, ED) between the time series of the test set and the time series of the reference template. )defined as:

Among them, n is the number of iterations; E _a is the time series of the reference template; E _b is the time series of the test set.

When the Euclidean distance is less than the threshold, it is determined to be the same noise, and the recognition result is output.

The identification decision is the result of comparison with the threshold, and the Euclidean distance between the time series of the test set and the reference templates of various noises is calculated. If it is smaller than the noise category threshold, it is judged as the same type of noise, and the classification result is output.

The overall block diagram of the system is shown in Figure 5.

In the present invention, the noise category threshold is the demarcation value of various categories of noises calculated through big data in the early stage.

Matters not addressed in the present invention are known in the art.

Claims (3)

1. a noise classification method based on the PCNN algorithm accelerated by FPGA, the method comprises the following steps: Step 1. Use a recording device to collect noise samples and edit them into audio files within 300ms-10s; Step 2, time-frequency conversion is performed on the audio file: short-time Fourier transform is performed on the audio file to obtain a noise spectrogram; Step 3, feature extraction: convert the noise spectrogram into a grayscale image, use the grayscale value as the input of the PCNN model, realize the acceleration of the iterative process of the PCNN algorithm through FPGA, and output the time series as the feature extraction of different types of noise; The specific process of realizing the acceleration of the iterative process of the PCNN algorithm through the FPGA is: 1) The FPGA circuit is in an idle state. When the reset signal is valid, all variables of the FPGA circuit are reset. After the reset signal is pulled high, it enters the initialization state and initializes each variable; 2) After initialization, jump to the calculation module in the FPGA. The calculation module implements the iterative process of the PCNN model. The gray value in the calculation module is used as the input for iterative acceleration until the number of iterations set in advance is reached. Jump back In idle state, complete the iterative acceleration process; Step 4: Divide each noise in the noise samples into a training set and a test set after processing and iterating the output time series for 50-200 times in Step 3; Step 5: Average the time series of each iteration of the training set as a reference template, and calculate the Euclidean distance between the time series of the test set and the time series of the reference template. When the Euclidean distance is less than the noise category threshold, it is determined to be the same noise. , and output the recognition result. 2. the noise classification method based on the PCNN algorithm accelerated by FPGA according to claim 1, is characterized in that, the process of short-time Fourier transform is; First to noise audio file framing, framing length is 10ms-30ms; The next step is to add a window to the noise audio after framing, using a Hanning window, the window length is equal to the frame length, and finally Fourier transform is performed on each frame, that is, the short-time Fourier transform of the noise audio is completed, and we get Noise spectrogram. 3. the noise classification method based on the PCNN algorithm accelerated by FPGA according to claim 1, is characterized in that, described FPGA circuit comprises control module, calculation module and storage module; Control module is responsible for coordinating the normal work of whole circuit, calculation module The iterative function of the PCNN algorithm is completed, and the data generated in the calculation is stored in the storage module; the control module sends signals to the storage module and the serial port receiving module respectively, and is responsible for coordinating the normal operation of the entire circuit of the FPGA; the PC enters the image gray value through the serial port receiving module. The FPGA circuit calculates the time series, and the FPGA circuit controls the storage module through the control module to upload the calculated output time series to the PC through the serial port receiving module.