CN109947391A - A kind of data processing method and device - Google Patents
A kind of data processing method and device Download PDFInfo
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- CN109947391A CN109947391A CN201910182657.7A CN201910182657A CN109947391A CN 109947391 A CN109947391 A CN 109947391A CN 201910182657 A CN201910182657 A CN 201910182657A CN 109947391 A CN109947391 A CN 109947391A
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Abstract
The invention discloses a kind of data processing method and device, which includes: to obtain control signal and the first data to be processed；In-place computation is carried out to the first data according to control signal and obtains the second data；Data interlaced operation is carried out to the second data according to control signal and obtains the third data of default bit wide, the bit wide of the second data is greater than the bit wide of third data.This method can be with 32,64 and 128 source datas of flexible combination, and data in-place computation is carried out to 32,64 and 128 source datas, make 32,64 and 128 source datas after data are replaced, as the data with microprocessor same bit-width, it can complete fixed/pretreated preposition calculating of floating data, to make micro process when calculating the numerous types of data such as 32/64/128 fixed/floating data, the computing resource of each clock does not waste, to improve the hardware availability ratio of microprocessor floating-point operation.
Description
Technical field
The present invention relates to microprocessor technology fields, and in particular to a kind of data processing method and device.
Background technique
With semiconductor fabrication process and the intensive development calculated, various application program extreme complications, microprocessor
Computing capability it is also growing day by day, it is the most outstanding performance be exactly calmly/floating data vector (data parallel execution) operational capability
Enhancing.Current fixed/Floating-point Computation type is broadly divided into single precision, double precision, four accuracy data operations, covers 32/64/
A variety of data such as 128.Microprocessor will support above-mentioned calculating type just to need to add and configure corresponding calculating inside it
Hardware cell, such as adder, multiplier, divider, in the microprocessor that max calculation bit wide is 128, if executed
The operation of numerous types of data will lead to when calculating 32/64 fixed/floating data, and each execution clock cycle can be not busy
Set 70% or 50% computing resource.
For above-mentioned there are problem, most straightforward procedure is exactly directly idle existing hardware resource, obviously inefficient in this way,
Waste hardware resource, it is clear that in high performance microprocessor Design be worthless.
Summary of the invention
In view of this, the embodiment of the invention provides a kind of data processing method and device, to solve high performance micro- place
Device is managed when calculating 32/64 fixed/floating data, it is each execute the clock cycle can leave unused 70% or 50% computing resource
Problem.
According in a first aspect, the embodiment of the invention provides a kind of data processing methods, comprising: obtain control signal and to
Handle the first data；In-place computation is carried out to the first data according to control signal and obtains the second data；According to control signal to the
Two data carry out data interlaced operation and obtain the third data of default bit wide, and the bit wide of the second data is greater than the position of third data
It is wide.
Optionally, in-place computation includes data saturation arithmetic, Data expansion operation, data union operation, position in-place computation
At least one of.
Optionally, the first data are carried out in-place computation to obtain the second data including: to be believed according to control according to control signal
Number saturation arithmetic is carried out to the high-order of the first data；Judge operation result whether within a preset range；If operation result is pre-
If in range, then the valid data of the first data is selected to be exported to obtain the second data.
Optionally, if operation result not within a preset range, selects preset data to be exported to obtain the second data.
Optionally, the first data are carried out in-place computation to obtain the second data including: judgement control letter according to control signal
With the presence or absence of the instruction for carrying data in number；When controlling the instruction for existing in signal and carrying data, to carrying data
The sign bit of instruction be extended, obtain the data of the first default bit wide；To the sign bit of the low datas of the first data into
Row extension, obtains the data of the second default bit wide；Using the data of the first default bit wide as high position data and by the second default position
Wide data form the second data as low data.
Optionally, in-place computation is carried out to the first data according to control signal and obtains the second data further include: when control is believed
There is no when the instruction for carrying data in number, the sign bit of the high position data of the first data is extended, it is pre- to obtain third
If the data of bit wide；Third is preset into the data of bit wide as high position data and using the data of the second default bit wide as lower-order digit
According to forming the second data.
Optionally, data interlaced operation is carried out to the second data according to control signal and obtains the third data packet of default bit wide
It includes: the second data is divided as unit of byte；According to control signal to the second data after dividing byte according to intersection
Switch matrix carries out selection output, obtains the third data of default bit wide.
According to second aspect, the embodiment of the invention provides a kind of data processing equipments, comprising: module is obtained, for obtaining
Take control signal and the first data to be processed；In-place computation module, for replace to the first data according to control signal
To the second data；Interlaced operation module obtains default position for carrying out data interlaced operation to the second data according to control signal
Wide third data, the bit wide of the second data are greater than the bit wide of third data.
According to the third aspect, the embodiment of the invention provides a kind of controllers, comprising: at least one processor；And with
The memory of at least one processor communication connection；Wherein, memory is stored with the instruction that can be executed by a processor, instruction
It is executed by least one processor, so that at least one processor executes any embodiment side of first aspect or first aspect
Data processing method in formula.
According to fourth aspect, the embodiment of the invention provides a kind of computer readable storage mediums, which is characterized in that calculates
Machine readable storage medium storing program for executing is stored with computer instruction, and computer instruction is for making computer execute first aspect or first aspect
Data processing method in any embodiment.
The embodiment of the invention provides a kind of data processing method and device, can be 32,64 and 128 with flexible combination
Source data, and data in-place computation is carried out to 32,64 and 128 source datas, for example, fixed/floating to 32/64/128
Point data format such as is compressed, is decompressed, being merged, being replicated, being replaced, being shifted, being selected at a variety of vector operations, makes 32,64
Source data with 128 becomes the data with microprocessor same bit-width after data are replaced, and can complete fixed/floating number
The preposition calculating of Data preprocess, thus make micro process when calculating the numerous types of data such as 32/64/128 fixed/floating data,
The computing resource of each clock does not waste, to improve the hardware availability ratio of microprocessor floating-point operation.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art
Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below
Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor
It puts, is also possible to obtain other drawings based on these drawings.
Fig. 1 shows the flow chart of data processing method of the embodiment of the present invention；
Fig. 2 shows data of embodiment of the present invention saturation arithmetic, Data expansion operation, data union operation basic circuit knots
Composition；
Fig. 3 shows position of the embodiment of the present invention and changes arithmetic element basic block diagram；
Fig. 4 shows data interleaved units basic block diagram of the embodiment of the present invention；
Fig. 5 shows data of the embodiment of the present invention and interlocks selector basic block diagram；
Fig. 6 shows the embodiment of the present invention without symbol to signless saturation arithmetic model structure chart；
Fig. 7, which shows the embodiment of the present invention, has symbol to signless saturation arithmetic model structure chart；
Fig. 8, which shows the embodiment of the present invention, has symbol to the saturation arithmetic model structure chart for having symbol；
Fig. 9 shows Data expansion operation basic block diagram of the embodiment of the present invention；
Figure 10 shows the structural block diagram of data processing equipment of the embodiment of the present invention；
Figure 11 shows controller architecture schematic diagram of the embodiment of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those skilled in the art are not having
Every other embodiment obtained under the premise of creative work is made, shall fall within the protection scope of the present invention.
The embodiment of the invention provides a kind of data processing methods, as shown in Figure 1, comprising:
S101. control signal and the first data to be processed are obtained.
In the present embodiment, the first data to be processed are source data, can be the group of any 32/64/128 data
It closes, control signal is signaling control unit according to the immediate in externally input selection control signal and the first data to be processed
Each function coding and corresponding logical combination are decoded and generate the corresponding control signal of each function in real time.Selection control
Signal and pending data are that correspondingly, control signal and pending data are also that correspondingly, selection controls signal
Type may include N group, can be expressed as S0, S1 ..., SN-2, SN-1.Immediate is to carry the instruction of data.
Specifically, the first data to be processed can be 32/64/128 data of multiple groups, it can be multiple groups 128 data, can be more
32/64 data of group, are also possible to 128 data being composed of 32/64 data.
S102. in-place computation is carried out to the first data according to control signal and obtains the second data.
In the present embodiment, in-place computation include data saturation arithmetic (saturate), Data expansion operation (extend),
At least one of data union operation, position in-place computation.
Specifically, data saturation arithmetic, Data expansion operation, data union operation cover function and are shown in Table 1.
Table 1
Data saturation arithmetic, Data expansion operation, data union operation basic circuit structure are as shown in Figure 2.For example, control
Signal can control data a (namely vr [vra]) in the first data and data b, and (namely vr [vrb] is saturated by data respectively
One 128 data (namely dataf_out [0:127]) can be respectively obtained after operation, or control signal can control the
Data b (namely vr [vrb]) and immediate (namely SIM [0:4]) in one data obtain one 256 after Data expansion
Data (namely dataf_out [0:255] or ex_out [0:255]), or control signal can control in the first data
Data a and data b directly merge operation without data saturation arithmetic and extended arithmetic, obtain one 256
Data (namely dataf_out [0:255]).
Position changes arithmetic element and is mainly used for realizing the in-place computation of the first data bit, because it is mainly substantially single with bit
Position is operated, and all kinds of position in-place computations being related to can not carry out circuit multiplexer, therefore the data in the circuit unit are logical
Road is mutually indepedent, and the basic structure of unit is as shown in Figure 3.Specifically, position, which is changed, is mainly divided into 6 function inside arithmetic element
Can circuit module, cover 9 class position replacement operators, comprising: step-by-step and, step-by-step or step-by-step exclusive or are negated, moved to left, moving to right.Position
In-place computation unit, can be to the number in the first data under control signal element (namely signal control module) control
According to position in-place computation is carried out, finally by calculated result (for example, bit_out [0:127]) by multiple selector (namely
Mux6_1 module) output.
S103. data interlaced operation is carried out to the second data according to control signal and obtains the third data of default bit wide, the
The bit wide of two data is greater than the bit wide of third data.
In the present embodiment, data interleaved units carry out data interlaced operation by basic unit of byte.Control is according to control
Signal processed carries out data interlaced operation to obtain the third data of default bit wide may include: by the second data with word to the second data
Section is that unit is divided；The second data after dividing byte select according to corsspoint switch matrix according to control signal defeated
Out, the third data of default bit wide are obtained.For example, data interleaved units input data interface can be set to 256, number is exported
It can be set to 128 according to interface, the data interconnected entirely inside the unit by the data of 16 same microstructure circuits are staggeredly selected
It selects device (also referred to as crossbar_mux) to compose in parallel, data interleaved units basic structure is as shown in Figure 4.What data interconnected entirely
Data selector selection data of interlocking are that selection is carried out according to the mode of corsspoint switch matrix, and data are interlocked selector
(crossbar_mux) basic structure is as shown in Figure 5.Specifically, interlock in selector in 16 identical data, each data
Staggeredly the control signal of selector is by 5 bit byte selection signals (namely sel), two 4 bit byte control words (namely Byte
[i] .bit [0:3] and Byte [i] .bit [4:7]) composition.When controlling signal is 5 bit byte selection signal, 5 sel exist
32 byte in dataf_out select one as output.When controlling signal is two 4 bit byte control words, two 4
NOR gate circuit in bit byte control word and Fig. 5 makes byte carry out displacement XOR operation, and from the height in dataf_out
16byte and low 16byte exports calculated result after respectively selecting a byte to carry out XOR operation, interlocks by 16 identical data
After selector selection, the data of output one 128.In the present embodiment, according to the demand that other are calculated, data interleaved units
Input data interface may be set to be other bit wides, such as 64, and 128,512 etc.；Output data interface can also be set
It is set to other bit wides, such as 64,256 etc.；Correspondingly, data are interlocked, the number of selector may be set to be other numbers.
The embodiment of the invention provides a kind of data processing methods, can be with 32,64 and 128 source numbers of flexible combination
According to, and data in-place computation is carried out to 32,64 and 128 source datas, for example, to 32/64/128 fixed/floating data
Format such as is compressed, is decompressed, being merged, being replicated, being replaced, being shifted, being selected at a variety of vector operations, makes 32,64 and 128
Source data after data are replaced, become the data with microprocessor same bit-width, fixed/floating data pretreatment can be completed
Preposition computing unit, to make micro process when calculating the numerous types of data such as 32/64/128 fixed/floating data, each
The computing resource of clock does not waste, to improve the hardware availability ratio of microprocessor floating-point operation.
In an alternate embodiment of the invention, obtaining the second data to the first data progress in-place computation according to control signal includes:
Saturation arithmetic is carried out to the high-order of the first data according to control signal；Judge operation result whether within a preset range；If fortune
It calculates result within a preset range, then the valid data of the first data is selected to be exported to obtain the second data.If operation result
Not within a preset range, then preset data is selected to be exported to obtain the second data.In the present embodiment, data saturation arithmetic master
Will include 3 class operation modes, for no symbol-without symbol (uu) mode, have symbol-without symbol (su) mode with there is symbol-to have symbol
Number (ss) mode.
Specifically, without symbol-without symbol (uu) mode, as without symbol to signless saturation arithmetic mode, such as Fig. 6
It is shown, saturation arithmetic is carried out to the high position data of half-word, word, double word respectively according to control signal, for example, to the height of each half-word
8 progress saturation arithmetics, obtain a calculated result, if calculated result is 0~28Between -1, then each half-word is exported
Least-significant byte data are as the second data, otherwise, export preset 8 data as the second data, preset 8 data are the upper limit
Value or lower limit value.
There is symbol-without symbol (su) mode, that is, has symbol to signless saturation arithmetic mode, as shown in fig. 7, according to
It controls signal and saturation arithmetic is carried out to the high position data of half-word, word, double word respectively, for example, each half-word is judged, if
Sign bit is equal to 1, then exports 8 ' h00 of result, if sign bit is equal to 0, then judges whether the high position data of each half-word is equal to
7 ' h7F export 8 ' hFF if being equal to 7 ' h7F, if being not equal to 7 ' h7F, export 8 ' hFF.
There is symbol-to have symbol (ss) mode, that is, has symbol to the saturation arithmetic mode for having symbol, as shown in figure 8, according to control
Signal processed carries out saturation arithmetic to the high position data of half-word, word, double word respectively, for example, judging each half-word, if symbol
Number position is equal to 0, then judges whether the high position data (vr [8:15]) of each half-word is equal to 8 ' h00, defeated if being equal to 8 ' h00
{ vr [0], vr [8:15] } (0bit and 8-15bit of vr is spliced into a byte) out；If being not equal to 8 ' h00, { vr is exported
[0],7'h7F}；If sign bit is equal to 1, then judges whether the high position data (vr [8:15]) of each half-word is equal to 8 ' hFF, such as
Fruit is equal to 8 ' hFF, then { vr [0], vr [8:15] } (0bit and 8-15bit of vr is spliced into a byte) is exported, if differed
In 8 ' hFF, then { vr [0], 7 ' h00 } is exported.
In an alternate embodiment of the invention, as shown in figure 9, carrying out in-place computation to the first data according to control signal obtains second
Data include: in judgement control signal with the presence or absence of the instruction for carrying data, and in the present embodiment, immediate is to carry
The instruction of data；When controlling the instruction for existing in signal and carrying data, the sign bit for the instruction for carrying data is carried out
Extension, obtains the data of the first default bit wide, in the present embodiment, is extended to the sign bit for the instruction for carrying data
Module is SIM [0:4] and sign-extended [0:31] module, can take 16 groups of [24:31] data to byte mode respectively
Module, half word pattern take 8 groups of [16:31] data modules, word pattern to take 4 groups of [0:31] data modules, and output obtains one 128
Data, such as ex_out [0:127]；The sign bit of the low data of first data is extended, for example, by vrb [64:
127] b_s_ex, h_s_ex or w_s_ex extension are carried out, obtains the data of the second default bit wide, such as ex_out [128:
255], wherein b_s_ex module is used to be half-word * 8 (amounting to 8 groups of half-word concurrent operation outputs) by byte symbol Bits Expanding；
H_s_ex module is used to for half-word sign bit being extended to word * 4 (amounting to 4 groups of word concurrent operation outputs)；W_s_ex module is used
In being double word * 2 (amount to 2 groups double word concurrent operations output) by character Bits Expanding；Using the data of the first default bit wide as height
Position data simultaneously form the second data, such as ex_out [0:255] for the data of the second default bit wide as low data.Work as control
There is no when the instruction for carrying data in signal processed, the sign bit of the high position data of the first data is extended, obtains the
The data of three default bit wides, such as by after vrb [0:63] progress b_s_ex, h_s_ex or w_s_ex extension, obtain one
A 128 data ex_out [0:127]；Third is preset into the data of bit wide as high position data and by the second default bit wide
Data as low data form the second data.
The embodiment of the invention provides a kind of data processing equipments, as shown in Figure 10, comprising: module 10 are obtained, for obtaining
Take control signal and the first data to be processed；In-place computation module 20, for being replaced according to control signal to the first data
Obtain the second data；Interlaced operation module 30, it is pre- for being obtained according to control signal to the second data progress data interlaced operation
If the third data of bit wide, the bit wide of the second data is greater than the bit wide of third data.
A kind of data processing equipment provided in an embodiment of the present invention both can be used as and stone accelerated to be embedded in all kinds of calculating lists
In member, it can also be integrated in the microprocessor in the form of instruction set.When the device is integrated in the microprocessor as instruction set form,
It can handle the arbitrary arrangement of different bit wide data and the vector storage/access operational order of recombination, to promote microprocessor internal
The efficiency of other instruction executions of register；/ pretreated preposition computing unit of floating data is determined when the device is used as, and can be made micro-
When calculating the numerous types of data such as 32/64/128 fixed/floating data, the computing resource of each clock is not wasted for processing,
To improve the hardware availability ratio of microprocessor floating-point operation.
The embodiment of the invention provides a kind of controllers, comprising: at least one processor 71；And it is handled at least one
The memory 72 of device communication connection；In Figure 11 by taking a processor 71 as an example.
Detection device can also include: input unit 73 and output device 74.
Processor 71, memory 72, input unit 73 and output device 74 can be connected by bus or other modes,
In Figure 11 for being connected by bus.
Processor 71 can be central processing unit (Central Processing Unit, CPU).Processor 71 can be with
For other general processors, digital signal processor (Digital Signal Processor, DSP), specific integrated circuit
(Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-
Programmable Gate Array, FPGA) either other programmable logic device, discrete gate or transistor logic,
The combination of the chips such as discrete hardware components or above-mentioned all kinds of chips.General processor can be microprocessor or the processing
Device is also possible to any conventional processor etc..
Memory 72 is used as a kind of non-transient computer readable storage medium, can be used for storing non-transient software program, non-
Transient computer executable program and module, such as the corresponding program instruction/mould of the data processing method in the embodiment of the present application
Block.Non-transient software program, instruction and the module that processor 71 is stored in memory 72 by operation, thereby executing service
The various function application and data processing of device, i.e. realization above method embodiment data processing method.
Memory 72 may include storing program area and storage data area, wherein storing program area can storage program area,
Application program required at least one function；Storage data area can store the use of the processing unit according to user terminal operations
The data etc. created.In addition, memory 72 may include high-speed random access memory, it can also include non-transient storage
Device, for example, at least a disk memory, flush memory device or other non-transient solid-state memories.In some embodiments,
Optional memory 72 includes the memory remotely located relative to processor 71, these remote memories can pass through network connection
To image detection, processing unit.The example of above-mentioned network includes but is not limited to internet, intranet, local area network, moves and lead to
Letter net and combinations thereof.
Input unit 73 can receive the number or character information of input, and generate the use with the processing unit of user terminal
Family setting and the related key signals input of function control.Output device 74 may include that display screen etc. shows equipment.
One or more module is stored in memory 72, when being executed by one or more processor 71, is executed
Method as shown in Figure 1.
It is that can lead to it will be understood by those skilled in the art that realizing all or part of the process in above-described embodiment method
Computer program is crossed to instruct relevant hardware and complete, the program can be stored in a computer-readable storage medium
In, the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, the storage medium can for magnetic disk,
CD, read-only memory (Read-Only Memory, ROM), random access memory (Random Access
Memory, RAM), flash memory (Flash Memory), hard disk (Hard Disk Drive, abbreviation: HDD) or solid state hard disk
(Solid-State Drive, SSD) etc.；The storage medium can also include the combination of the memory of mentioned kind.
Although being described in conjunction with the accompanying the embodiment of the present invention, those skilled in the art can not depart from the present invention
Spirit and scope in the case where various modifications and variations can be made, such modifications and variations are each fallen within by appended claims institute
Within the scope of restriction.
Claims (10)
1. a kind of data processing method characterized by comprising
Obtain control signal and the first data to be processed；
In-place computation is carried out to first data according to the control signal and obtains the second data；
Data interlaced operation is carried out to second data according to the control signal and obtains the third data of default bit wide, it is described
The bit wide of second data is greater than the bit wide of third data.
2. data processing method according to claim 1, which is characterized in that
The in-place computation include data saturation arithmetic, Data expansion operation, data union operation, in the in-place computation of position at least
One of.
3. data processing method according to claim 2, which is characterized in that it is described according to the control signal to described
One data progress in-place computation obtains the second data and includes:
Saturation arithmetic is carried out to the high-order of first data according to the control signal；
Judge operation result whether within a preset range；
If the operation result in the preset range, selects the valid data of first data to be exported to obtain
Second data.
4. data processing method according to claim 3, which is characterized in that if the operation result is not described default
In range, then preset data is selected to be exported to obtain the second data.
5. data processing method according to claim 2 or 3, which is characterized in that it is described according to the control signal to institute
It states the first data and carries out in-place computation and obtain the second data and include:
Judge in the control signal with the presence or absence of the instruction for carrying data；
When there is the instruction for carrying data in the control signal, the sign bit of the instruction for carrying data is carried out
Extension, obtains the data of the first default bit wide；
The sign bit of the low data of first data is extended, the data of the second default bit wide are obtained；
Using the data of the described first default bit wide as high position data and using the data of the described second default bit wide as lower-order digit
According to composition second data.
6. data processing method according to claim 4, which is characterized in that it is described according to the control signal to described
One data carry out in-place computation and obtain the second data further include:
When the instruction for carrying data is not present in the control signal, to the sign bit of the high position data of first data
It is extended, obtains the data that third presets bit wide；
The third is preset into the data of bit wide as high position data and using the data of the described second default bit wide as lower-order digit
According to composition second data.
7. data processing method according to claim 1, which is characterized in that it is described according to the control signal to described
Two data carry out data interlaced operation and obtain the third data of default bit wide
Second data are divided as unit of byte；
Selection output is carried out according to corsspoint switch matrix to second data after dividing byte according to the control signal, is obtained
To the third data of default bit wide.
8. a kind of data processing equipment characterized by comprising
Module is obtained, for obtaining control signal and the first data to be processed；
Extended arithmetic module obtains the second data for being extended operation to first data according to the control signal；
Interlaced operation module obtains default position for carrying out data interlaced operation to second data according to the control signal
Wide third data, the bit wide of second data are greater than the bit wide of third data.
9. a kind of controller characterized by comprising
At least one processor；And the memory being connect at least one described processor communication；Wherein, the memory is deposited
Contain the instruction that can be executed by one processor, described instruction is executed by least one described processor so that it is described extremely
A few processor executes the data processing method as described in claim 1-7 any one.
10. a kind of computer readable storage medium, which is characterized in that the computer-readable recording medium storage has computer to refer to
It enables, the data processing side that the computer instruction is used to that the computer to be made to execute as described in claim 1-7 any one
Method.
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