CN109935606A - A kind of dot structure of high demodulation efficiency - Google Patents

A kind of dot structure of high demodulation efficiency Download PDF

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CN109935606A
CN109935606A CN201910246974.0A CN201910246974A CN109935606A CN 109935606 A CN109935606 A CN 109935606A CN 201910246974 A CN201910246974 A CN 201910246974A CN 109935606 A CN109935606 A CN 109935606A
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charge
collecting region
charge transfer
photogenerated
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CN109935606B (en
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汪一飞
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Wuhan Silicon Integrated Co Ltd
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Abstract

The invention discloses a kind of dot structures of high demodulation efficiency, including P type substrate, P type substrate upper surface middle part is deposited with N-type photogenerated charge collecting region, P+ clamper layer is deposited on N-type photogenerated charge collecting region, the upper surface of the P+ clamper layer is concordant with the upper surface of P type substrate, two lateral charge guidance grid are symmetrically arranged at left and right sides of the P+ clamper layer upper surface, the P+ clamper layer upper surface front end is symmetrically arranged with two charge transfer gates, photogenerated charge memory block is deposited at charge transfer gate front position in the P type substrate, the shape of the N-type photogenerated charge collecting region is that width and depth are gradually reduced from front to back.The structure that the present invention is gradually reduced from front to back using the width and depth of N-type photogenerated charge collecting region can be increased the potential difference in vertical direction with amplitude peak, increase electric charge transfer speed.

Description

A kind of dot structure of high demodulation efficiency
Technical field
The present invention relates to a kind of dot structures of high demodulation efficiency.
Background technique
Usual PPD clamper photodiode is used as in two-dimensional image sensor.In 3-dimensional image sensor, when adopting When carrying out range measurement with indirect flight time telemetry, common clamper photodiode is then faced with photogenerated charge transfer velocity The slow and incomplete problem of transfer.In time-of-flight method, photodiode will not only realize the function of photoelectric conversion, it is also necessary to Realize the function of photogenerated charge demodulation.At this point, commonly the slow defect of clamper photodiode charge transfer velocity will be amplified, Its typical performance is that photogenerated charge can not be shifted in time completely by intensity grid, and the photogenerated charge generated in the period is not turned It moves, then can retain and the photogenerated charge generated in subsequent time period is included in by the transfer of another intensity grid.The defect causes by general The demodulation pixel modulation /demodulation frequency of logical clamper photodiode production once works in the case where being higher than 20MHz, it is difficult to real Existing 50% or more frequency, demodulation frequency.It is corresponding, it will lead to the increase of range measurement error.
There are two types of the charge transfer effciencies that clamper photodiode can be improved in method at present, the first: changing photoelectric tube Shape, the increase of vertical direction potential difference caused by the difference using width of depletion region improves electric charge transfer speed and effect Rate.Second: changing the doping concentration of photoelectric tube different zones, the difference of doping concentration also results in potential difference increase, equally Electric charge transfer speed and efficiency can be improved.Second method needs special technique to be manufactured, first method institute shape At potential difference it is also limited.Even if using both the above method, manufactured demodulation pixel is after frequency is more than 20MHz, solution Adjust efficiency also can dramatic decrease.Its most important reason is in " The Effect of Pinned Photodiode Shape on Time-of-Flight Demodulation Contrast, IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 5 64, NO., MAY 2017 " in analyzed and explained.Two grid that i.e. pixel both sides are demodulated can not mention For the electric field of enough horizontal directions, leading to photogenerated charge, transfer velocity is slow in the horizontal direction, ties even with PPD is improved Structure, can be quickly by before electric charge transfer to two TG transfer gates, but two TG transfer gates are when transfer level opposite direction charge Speed is still relatively slow.
Grid in cmos image sensor technique can be not only used for electric charge transfer, it can also be used to auxiliary guidance electric charge stream Dynamic purpose.In " 4.3 A programmable sub-nanosecond time- of Seo, Min Woong, et al. " gated 4-tap lock-in pixel CMOS image sensor for real-time fluorescence Lifetime imaging microscopy. " Solid-State Circuits Conference IEEE, 2017. " in, Multiple grids are applied into different biass based on standard CMOS image sensor process, quickly to guide the flowing side of photogenerated charge To for the detection of fluorescence life.
Summary of the invention
In order to solve the above technical problem, the present invention provides a kind of dot structures of the simple high demodulation efficiency of structure.
Technical proposal that the invention solves the above-mentioned problems is: a kind of dot structure of high demodulation efficiency, including P type substrate, P It is deposited with N-type photogenerated charge collecting region in the middle part of type upper surface of substrate, P+ clamper layer, institute are deposited on N-type photogenerated charge collecting region The upper surface for stating P+ clamper layer is concordant with the upper surface of P type substrate, is symmetrically arranged with two at left and right sides of the P+ clamper layer upper surface A lateral charge guides grid, and the P+ clamper layer upper surface front end is symmetrically arranged with two charge transfer gates, and the P type substrate tightens Photogenerated charge memory block is deposited at charge transfer gate front position, the shape of the N-type photogenerated charge collecting region is in the past Width and depth are gradually reduced backward.
The dot structure of above-mentioned high demodulation efficiency, the lateral charge guidance grid are connected across N-type photogenerated charge collecting region and P The intersection of type substrate is equipped with silicon dioxide layer I between lateral charge guidance grid and N-type photogenerated charge collecting region, P type substrate.
The dot structure of above-mentioned high demodulation efficiency, the charge transfer gate is connected across N-type photogenerated charge collecting region and p-type serves as a contrast The intersection at bottom is equipped with silicon dioxide layer II between charge transfer gate and N-type photogenerated charge collecting region, P type substrate.
The dot structure of above-mentioned high demodulation efficiency, II lower front of silicon dioxide layer and P type substrate contact position are equipped with P Type channel I, P-type channel I are the low-doped area P;II lower rear of silicon dioxide layer and N-type photogenerated charge collecting region, p-type P-type channel II is equipped at substrate contact, P-type channel II is the highly doped area P.
The dot structure of above-mentioned high demodulation efficiency, in symmetrical two charge transfer gates, one of charge transfer gate is applied Added with the square wave with active light source same phase, other side charge transfer gate is applied with the square wave with active light source opposite phase, And two lateral charge guidance grid are applied with are less than active light with frequency, same-phase, duty ratio with its ipsilateral charge transfer gate respectively The square wave in source.
The beneficial effects of the present invention are:
1) structure that the present invention is gradually reduced from front to back using the width and depth of N-type photogenerated charge collecting region, can be maximum Amplitude increases the potential difference in vertical direction, increases electric charge transfer speed.
2) present invention cooperates charge transfer gate to be added to lateral charge guidance grid, lateral charge at left and right sides of P+ clamper layer Guidance grid increase charge level shift direction electric field strength, so that electric charge transfer speed is accelerated, finally greatly improve high frequency Lower demodulation contrast.
3) in symmetrical two charge transfer gates of the present invention, one of charge transfer gate is applied with identical as active light source The square wave of phase, other side charge transfer gate are applied with the square wave with active light source opposite phase, and two lateral charge guidance Grid are applied with the square wave for being less than active light source with frequency, same-phase, duty ratio with its ipsilateral charge transfer gate, left and right sides side respectively A part of a length of corresponding applied grid voltage of side charge transfer gate when the grid voltage applied to charge guidance grid, this can enable For electric charge transfer in horizontal direction into demodulating process behind that corresponding side, charge will not accumulate on this, but be turned rapidly Grid are moved to collect to electric charge storage region.
Detailed description of the invention
Fig. 1 is the structure chart of existing clamper photodiode.
Fig. 2 is top view of the invention.
Fig. 3 is left view of the invention.
Fig. 4 is main view of the invention.
The voltage timing diagram that Fig. 5 is applied for the present invention.
Fig. 6 applies voltage timing diagram by existing demodulation pixel grid.
Specific embodiment
The present invention is further illustrated with reference to the accompanying drawings and examples.
As shown in figs 2-4, a kind of dot structure of high demodulation efficiency, including P type substrate 101, table in P type substrate 101 Middle face is deposited with N-type photogenerated charge collecting region 102, and P+ clamper layer 103 is deposited on N-type photogenerated charge collecting region 102, described The upper surface of P+ clamper layer 103 is concordant with the upper surface of P type substrate 101, symmetrical at left and right sides of 103 upper surface of P+ clamper layer If there are two lateral charges to guide grid 104, the 103 upper surface front end of P+ clamper layer is symmetrically arranged with two charge transfer gates 105, It is deposited with N-type photogenerated charge memory block 106 at charge transfer gate front position in the P type substrate 101, it generally, can To judge two photogenerated charge memory blocks from N-type light by the potential change before and after N-type photogenerated charge collecting region electric charge transfer Raw electric charge collecting region shifts the total amount of electric charge come.
The shape of the N-type photogenerated charge collecting region 102 is that width and depth are gradually reduced from front to back.In Fig. 2 and Fig. 3 Display width, change in depth be representative value 4, in the specific implementation process its change width quantity can according to pixel size into Row adjustment, value can be 2,3,4,5,6... ..., and integer is a.Similarly become to cooperate N-type photogenerated charge to collect sector width The quantity of the quantity of change, the lateral charge guidance grid of two sides can be increased according to change width quantity.
The lateral charge guidance grid are connected across the intersection of N-type photogenerated charge collecting region 102 Yu P type substrate 101, laterally Charge, which guides, is equipped with silicon dioxide layer I 109 between grid 104 and N-type photogenerated charge collecting region 102, P type substrate 101.N-type photoproduction Electric charge collecting region extends outwardly in lateral charge guidance grid bearing needs to overlap with lateral charge guidance grid, so as to lateral Potential on charge guidance grid can be transferred to N-type photogenerated charge collecting region 106.
The charge transfer gate 105 is connected across the intersection of N-type photogenerated charge collecting region and P type substrate, charge transfer gate Silicon dioxide layer II 110 is equipped between N-type photogenerated charge collecting region, P type substrate.
II lower front of silicon dioxide layer and P type substrate contact position are equipped with P-type channel I 108, the silicon dioxide layer II lower rear and N-type photogenerated charge collecting region, P type substrate contact position are equipped with P-type channel II 107, in order to eliminate early stage clamper The electric charge transfer potential barrier of photodiode channel, P-type channel I 108 are the low-doped area P, and P-type channel II 107 is highly doped P Area.
In symmetrical two charge transfer gates, one of charge transfer gate is applied with the side with active light source same phase Wave, other side charge transfer gate is applied with the square wave with active light source opposite phase, and two lateral charge guidance grid are applied respectively Added with the square wave for being less than active light source with frequency, same-phase, duty ratio with its ipsilateral charge transfer gate.
Fig. 5 applies voltage timing diagram by demodulation pixel grid.Its typical modulation /demodulation frequency is 20MHz, timing in figure Figure is divided into four parts.First part is picture element global reset, and the purpose is to N-type photogenerated charge collecting region redundancy charge is whole It releases, and the current potential of N+ electric charge storage region is reset to a relatively-stationary voltage.Second part is INT accumulating photo-generated charge And it is transferred to the N+ electric charge storage region time, representative value is 5 milliseconds.Part III is the row sampling time, and representative value is 2 micro- Second, Part IV is that column its representative value of sampling time is 26 microseconds.Entire timing diagram shares 6 rows.The first row represents infrared LED light The operation timing in source.Second row is that infrared light reaches object reflected offset wave forms again.Third and fifth line are two sides To the operation timing of charge guidance grid.The operation timing of 4th and the 6th two charge transfer gates of behavior.The present invention is in order to cooperate The improved timing variations of structure are second part, i.e. charge accumulation and transition phase.Keep when first charge transfer gate and When LED light source is with frequency same-phase, second charge transfer gate is then kept and LED light source with same frequency and reversed-phase, and first charge is cooperated to turn First lateral charge guidance grid for moving grid are kept and first charge transfer gate is with the same phase of frequency, and duty ratio is that first charge turns The 50% of grid is moved, i.e. its pulse width was 25 nanoseconds.At this point, second lateral charge guidance of second charge transfer gate of cooperation Grid are kept and second charge transfer gate is with the same phase of frequency, and duty ratio is the 50% of second charge transfer gate, i.e. its pulse width is 25 nanoseconds.

Claims (5)

1. a kind of dot structure of high demodulation efficiency, it is characterised in that: including P type substrate, P type substrate upper surface middle part is deposited with N-type photogenerated charge collecting region is deposited with P+ clamper layer, the upper surface of the P+ clamper layer and p-type on N-type photogenerated charge collecting region The upper surface of substrate is concordant, and two lateral charge guidance grid, the P+ are symmetrically arranged at left and right sides of the P+ clamper layer upper surface Clamper layer upper surface front end is symmetrically arranged with two charge transfer gates, abuts at charge transfer gate front position in the P type substrate It is deposited with photogenerated charge memory block, the shape of the N-type photogenerated charge collecting region is that width and depth are gradually reduced from front to back.
2. the dot structure of high demodulation efficiency according to claim 1, it is characterised in that: the lateral charge guidance grid across Connect the intersection in N-type photogenerated charge collecting region and P type substrate, lateral charge guidance grid and N-type photogenerated charge collecting region, p-type Silicon dioxide layer I is equipped between substrate.
3. the dot structure of high demodulation efficiency according to claim 1, it is characterised in that: the charge transfer gate is connected across The intersection of N-type photogenerated charge collecting region and P type substrate, between charge transfer gate and N-type photogenerated charge collecting region, P type substrate Equipped with silicon dioxide layer II.
4. the dot structure of high demodulation efficiency according to claim 3, it is characterised in that: II front of silicon dioxide layer Lower section and P type substrate contact position are equipped with P-type channel I, and P-type channel I is the low-doped area P;Under II rear portion of silicon dioxide layer Side is equipped with P-type channel II with N-type photogenerated charge collecting region, P type substrate contact position, and P-type channel II is the highly doped area P.
5. the dot structure of high demodulation efficiency according to claim 1, it is characterised in that: symmetrical two charge transfer gates In, one of charge transfer gate is applied with the square wave with active light source same phase, other side charge transfer gate be applied with The square wave of active light source opposite phase, and two lateral charges guidance grid be applied with respectively with its ipsilateral charge transfer gate with frequency, Same-phase, duty ratio are less than the square wave of active light source.
CN201910246974.0A 2019-03-29 2019-03-29 Pixel structure with high demodulation efficiency Active CN109935606B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111180477A (en) * 2020-01-06 2020-05-19 宁波飞芯电子科技有限公司 Image sensor and image acquisition equipment

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CN101663884A (en) * 2007-04-23 2010-03-03 美光科技公司 Method, apparatus, and system providing a rectilinear pixel grid with radially scaled pixels
CN102299163A (en) * 2011-09-13 2011-12-28 上海中科高等研究院 Image sensor
CN102324430A (en) * 2011-09-20 2012-01-18 天津大学 Four-tube active pixel of rapid charge transfer and making method thereof
CN102387316A (en) * 2010-08-31 2012-03-21 比亚迪股份有限公司 Pixel unit and image sensor with high dynamic range
US20170077156A1 (en) * 2015-09-10 2017-03-16 Seiko Epson Corporation Solid state imaging element and manufacturing method thereof, and electronic apparatus

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1871709A (en) * 2003-08-22 2006-11-29 微米技术有限公司 Imaging with gate controlled charge storage
CN101663884A (en) * 2007-04-23 2010-03-03 美光科技公司 Method, apparatus, and system providing a rectilinear pixel grid with radially scaled pixels
CN102387316A (en) * 2010-08-31 2012-03-21 比亚迪股份有限公司 Pixel unit and image sensor with high dynamic range
CN102299163A (en) * 2011-09-13 2011-12-28 上海中科高等研究院 Image sensor
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111180477A (en) * 2020-01-06 2020-05-19 宁波飞芯电子科技有限公司 Image sensor and image acquisition equipment
CN111180477B (en) * 2020-01-06 2022-06-28 宁波飞芯电子科技有限公司 Image sensor and image acquisition equipment

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