CN109934336A - Design method of neural network dynamic acceleration platform based on optimal structure search and neural network dynamic acceleration platform - Google Patents

Abstract

The invention provides a method for designing a neural network dynamic acceleration platform based on optimal structure search. The neural network dynamic acceleration platform includes: a control terminal and a hardware acceleration terminal; the control terminal is used for training the control neural network, and the control neural network is based on the sub-neural network. Feedback inference accuracy and preset accuracy requirements, update the structure of the sub-neural network and generate the sub-neural network structure parameters, retrain the updated sub-neural network to generate weight parameters, and generate a configuration file to send at the same time To the hardware acceleration end, the configuration file contains the structural parameters and weight parameters of the sub-neural network; when the hardware acceleration end returns the inference accuracy of the sub-neural network to be stable, the optimal structure of the sub-neural network on the hardware acceleration end is searched; The sub-neural network is a neural network that needs to perform inference acceleration at the hardware acceleration end; the present invention can dynamically search for the optimal structure of the sub-neural network that needs to perform hardware inference acceleration.

Description

Design method and neural network dynamic acceleration platform based on optimal structure search Network Dynamic Acceleration Platform

technical field

The invention relates to the field of intelligent platform computing, in particular to a neural network dynamic acceleration platform design method based on optimal network structure search.

Background technique

Deep Neural Networks (DNNs) have shown great value, and among DNNs, Convolutional Neural Networks (CNNs) have obvious advantages over traditional image recognition schemes. With the improvement of people's requirements, the deepening of the number of network layers and the continuous increase of the database have become the mainstream development technology lines of CNN. At the same time, the application of deep neural networks also faces several problems:

(1) It will take more time to train a convolutional neural network. The CNN algorithm mainly realizes convolution through a large number of multiplication operations. The CNN model proposed by LeCun et al. in 1998 for recognizing handwritten fonts is only less than 2.3×10 ⁷ The number of multiplication operations of the CNN model named AlexNet designed by Krizhevsky et al in 2012 reached 1.1×10 ⁹ times, while the number of multiplication operations required by the CNN model proposed by Simonyan and Zisserman in 2015 even exceeded 1.6 times. ×10 ¹⁰ times.

(2) Large deep neural networks consume considerable power when running and are inefficient in general-purpose processors. Because its model must be stored in external DRAM, and it needs to be called in real time during the inference of pictures or speech. The table below shows the power consumption for basic operations and storage in a 45nm CMOS processor. Without the optimization of the network structure and the optimization of the hardware structure, the access and operation of the model data will consume a lot of power consumption. Especially for embedded mobile, this is not allowed.

Table 1. 45nm CMOS processor power consumption table

In view of the above requirements and challenges, it is very urgent to provide a design method of a neural network dynamic acceleration platform based on optimal structure search based on conditions such as hardware resources and accuracy requirements, and to meet the requirements of high hardware computing efficiency and high performance-to-power ratio. .

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the deficiencies in the prior art, and to provide a neural network dynamic acceleration platform design method based on optimal structure search and a neural network dynamic acceleration platform, which can dynamically perform hardware inference acceleration for sub-neural acceleration. The network performs the optimal structure search and completes the inference acceleration process of the sub-neural network. The technical scheme adopted in the present invention is:

A neural network dynamic acceleration platform design method based on optimal structure search, comprising:

S1, the control neural network on the control end of the neural network dynamic acceleration platform updates the structure of the sub-neural network and generates the sub-neural network structure parameters according to the inference accuracy fed back by the sub-neural network and the preset accuracy accuracy requirements. At the same time, the control terminal retrains the sub-neural network with the updated structure, generates the weight parameters of the sub-neural network, and finally generates the address and access mode of the memory; configuration file;

S2, write the configuration file into the configuration cache module of the hardware acceleration side in the neural network dynamic acceleration platform, and update the volume in the core computing module according to the number of convolution layers, pooling layers, and fully connected layers in the configuration file. The number of product calculation units, pooling units, and linear calculation units, update the connection mode of each unit according to the parameters representing the connection mode of each layer in the configuration file, and update the convolution calculation unit, respectively, according to the structural parameters of the convolution layer and the pooling layer. The structure of the pooling unit;

S3, read the input data through the data input unit, and perform the convolution operation on the input data through the convolution calculation unit, and then obtain the classification result through the linear operation unit, the pooling unit and the classification unit, and calculate the inference of the sub-neural network at the same time Accuracy, and finally output the classification results and inference accuracy through the data output unit;

S4, the inference accuracy of the sub-neural network is fed back to the control terminal again, and the control neural network updates the sub-neural network again through the inference accuracy of the sub-neural network and the preset accuracy accuracy, and generates a new sub-neural At the same time, the control terminal retrains the sub-neural network whose structure has been updated, generates the weight parameters of the sub-neural network, and finally generates the address and access mode of the memory; and access mode to form a configuration file;

S5, iterates in this way, when the accuracy rate of the sub-neural network returned by the hardware acceleration terminal remains stable, the control neural network will no longer update the structure of the sub-neural network, and the structural parameters of the sub-neural network remain unchanged; Update, that is, search for the optimal structure of the sub-neural network on the hardware acceleration side.

A neural network dynamic acceleration platform, comprising: a control terminal and a hardware acceleration terminal;

The control terminal is used to train the control neural network. The control neural network updates the structure of the sub-neural network and generates the structural parameters of the sub-neural network according to the inference accuracy fed back by the sub-neural network and the preset accuracy requirements. The subsequent sub-neural network is retrained to generate weight parameters, and a configuration file is generated and sent to the hardware acceleration terminal. The configuration file contains the structural parameters and weight parameters of the sub-neural network; when the hardware acceleration terminal returns to the sub-neural network inference accuracy After the inference accuracy is stable, control The neural network no longer updates the sub-neural network, that is, the optimal structure of the sub-neural network on the hardware acceleration end is searched;

The sub-neural network is a neural network that needs to perform inference acceleration at the hardware acceleration end;

The hardware acceleration terminal is a sub-neural network hardware inference accelerator implemented by ASIC, which accepts the configuration file generated by the control terminal, completes the hardware implementation of the sub-neural network, and accelerates the inference process of the sub-neural network. The inference accuracy is fed back to the control terminal; finally, the hardware inference acceleration process of searching for the optimal structure of the sub-neural network and completing the sub-neural network with the optimal structure is achieved.

specifically,

The structure of the sub-neural network includes the number of convolutional layers, the number of pooling layers, the number of fully connected layers, the structure of the convolutional layer, the structure of the pooling layer and the connection method of each layer; the convolutional layer structure includes the convolution kernel. Number, size, step size, the pooling layer structure includes pooling window size and step size;

Parameters in the configuration file include:

The number of convolutional layers, the number of pooling layers, the number of fully connected layers, and the connection method of each layer;

The structure of the convolutional layer: the number of convolution kernels, the size, and the stride;

The structure of the pooling layer: pooling window size, step size;

The weight parameters of the retrained sub-neural network;

Memory address, memory access mode;

The hardware acceleration terminal includes a data input module, a configuration cache module, a core calculation module, and a data output module; the core calculation module includes a convolution calculation unit, a pooling unit, a linear calculation unit, and a classification unit; among which the convolution calculation unit, the pooling unit , The number of linear computing units corresponds to the number of convolutional layers, pooling layers, and fully connected layers in the configuration file respectively; the hardware structure of the convolutional computing unit is determined by the convolutional layer structure parameters in the configuration file. , the hardware structure of the pooling unit is determined by the pooling layer structure parameters in the configuration file; the hardware connection mode of each unit in the core computing module is determined by the connection mode of each layer in the configuration file;

The data input module is used to divide the data into n single-channel data blocks according to the number of input data channels, the configuration cache module is used to cache the configuration file generated on the control terminal, and the core calculation module uses a convolution calculation unit. The m convolution kernels in the n data blocks sequentially convolve the n data blocks with the step size k to generate m feature maps, where m and k represent the number of convolution kernels and the convolution step size in the convolution calculation unit respectively, which are respectively related to the configuration. The number of convolution kernels in the file corresponds to the step size, and is transmitted to the pooling unit for feature sampling, and then the classification result is generated by the linear calculation unit and the classification unit, and the inference accuracy of the sub-neural network is calculated at the same time, and finally through the data output unit Output classification results and inference accuracy.

The advantages of the present invention are: the neural network dynamic acceleration platform design method based on the optimal structure search provided by the present invention can dynamically adjust the sub-neurons on the hardware acceleration end under the condition of specific hardware resources, variable precision, and external parameters change. The optimal structure of the network is searched, and the inference of the sub-neural network of this optimal structure is accelerated; it can meet the requirements of high-performance power consumption ratio, low-latency, and variable precision of neural network processing chips, and solves the problem of the processor in the prior art. It cannot be efficiently applied to multi-function and multi-platform problems at the same time.

Description of drawings

FIG. 1 is a hierarchical diagram of a neural network dynamic acceleration platform based on optimal structure search according to the present invention.

FIG. 2 is a schematic diagram of the structure and composition of the neural network dynamic acceleration platform of the present invention.

FIG. 3 is a schematic diagram of the calculation flow of the control neural network of the present invention.

FIG. 4 is a schematic diagram of the calculation of the convolution calculation unit of the present invention.

FIG. 5 is a schematic diagram of a linear calculation unit and a classification unit of the present invention.

FIG. 6 is a schematic diagram of approximately realizing the Sigmoid function by the nonlinear approximation method of the present invention.

Detailed ways

The present invention will be further described below with reference to the specific drawings and embodiments.

Fig. 1 shows the hierarchy diagram of the neural network dynamic acceleration platform (hereinafter referred to as the acceleration platform) based on the optimal structure search proposed by the present invention; it includes a control layer, an application layer, a connection layer, and a hardware layer;

The control layer and the application layer both belong to the software layer. The control layer completes the training of the control neural network and searches for the optimal structure of the sub-neural network, and at the same time completes the retraining of the sub-neural network with the optimal structure;

For the application layer, the user realizes the data input to the hardware acceleration side by calling the supported hardware programming interface;

The connection layer provides the transmission of configuration files composed of sub-neural network structure parameters, weight parameters, etc. and the sub-neural network inference accuracy fed back by the hardware acceleration terminal;

The hardware layer mainly provides the inference acceleration function of the sub-neural network, including data input module, configuration cache module, core computing module, data output module and other modules;

2 shows a schematic structural diagram of a neural network dynamic acceleration platform based on optimal structure search proposed by the present invention, and the acceleration platform includes a control terminal and a hardware acceleration terminal;

The control terminal is a server containing a graphics processor, which is used to train the control neural network, and the control neural network updates the structure of the sub-neural network and generates the inference accuracy fed back by the sub-neural network and the preset accuracy requirements. Sub-neural network structure parameters, retrain the updated sub-neural network to generate weight parameters, and generate a configuration file and send it to the hardware acceleration terminal. The configuration file contains the structural parameters and weight parameters of the sub-neural network; when the hardware acceleration terminal returns the After the neural network inference accuracy is stable, the control neural network will no longer update the sub-neural network, that is, the optimal structure of the sub-neural network on the hardware acceleration end is searched;

The sub-neural network is a neural network that needs to perform inference acceleration on the hardware acceleration side; the structure of the sub-neural network includes the number of convolutional layers, the number of pooling layers, the number of fully connected layers, the structure of the convolutional layer, the pooling The structure of the layer and the connection method of each layer; the structure of the convolution layer includes the number, size and step size of the convolution kernel, and the structure of the pooling layer includes the size and step size of the pooling window;

Parameters in the configuration file include:

The number of convolutional layers, the number of pooling layers, the number of fully connected layers, and the connection method of each layer;

The structure of the convolutional layer: the number of convolution kernels, the size, and the stride;

The structure of the pooling layer: pooling window size, step size;

The weight parameters of the retrained sub-neural network;

Memory address, memory access mode;

The hardware acceleration terminal is a sub-neural network hardware inference accelerator implemented by ASIC, which accepts the configuration file generated by the control terminal, completes the hardware implementation of the sub-neural network, and accelerates the inference process of the sub-neural network. The inference accuracy is fed back to the control terminal; finally, the hardware inference acceleration process of sub-neural network searching for the optimal structure of the sub-neural network and completing the sub-neural network with the optimal structure is achieved;

The hardware acceleration terminal includes a data input module, a configuration cache module, a core calculation module, and a data output module; the core calculation module includes a convolution calculation unit, a pooling unit, a linear calculation unit, and a classification unit; among which the convolution calculation unit, the pooling unit , The number of linear computing units corresponds to the number of convolutional layers, pooling layers, and fully connected layers in the configuration file respectively; the hardware structure of the convolutional computing unit is determined by the convolutional layer structure parameters in the configuration file. , the hardware structure of the pooling unit is determined by the pooling layer structure parameters in the configuration file; the hardware connection mode of each unit in the core computing module is determined by the connection mode of each layer in the configuration file;

The data input module is used to divide the data into n single-channel data blocks according to the number of input data channels, the configuration cache module is used to cache the configuration file generated on the control terminal, and the core calculation module uses a convolution calculation unit. The m convolution kernels in the n data blocks sequentially convolve the n data blocks with the step size k to generate m feature maps, where m and k represent the number of convolution kernels and the convolution step size in the convolution calculation unit respectively (respectively with the configuration The number of convolution kernels in the file, the step size corresponds), and transmitted to the pooling unit for feature sampling, and then the classification results are generated by the linear calculation unit and the classification unit, and the inference accuracy of the sub-neural network is calculated at the same time, and finally output through the data The unit outputs classification results and inference accuracy;

The neural network dynamic acceleration platform design method based on optimal structure search proposed by the present invention, the main process is as follows:

S1, the control neural network on the control end of the neural network dynamic acceleration platform updates the structure of the sub-neural network and generates the sub-neural network structure parameters according to the inference accuracy fed back by the sub-neural network and the preset accuracy accuracy requirements. At the same time, the control terminal retrains the sub-neural network with the updated structure, generates the weight parameters of the sub-neural network, and finally generates the address and access mode of the memory; configuration file;

S2, write the configuration file into the configuration cache module of the hardware acceleration side in the neural network dynamic acceleration platform, and update the volume in the core computing module according to the number of convolution layers, pooling layers, and fully connected layers in the configuration file. The number of product calculation units, pooling units, and linear calculation units, update the connection mode of each unit according to the parameters representing the connection mode of each layer in the configuration file, and update the convolution calculation unit, respectively, according to the structural parameters of the convolution layer and the pooling layer. The structure of the pooling unit;

S3, read the input data through the data input unit, and perform the convolution operation on the input data through the convolution calculation unit, and then obtain the classification result through the linear operation unit, the pooling unit and the classification unit, and calculate the inference of the sub-neural network at the same time Accuracy, and finally output the classification results and inference accuracy through the data output unit;

S4, the inference accuracy of the sub-neural network is fed back to the control terminal again, and the control neural network updates the sub-neural network again through the inference accuracy of the sub-neural network and the preset accuracy accuracy, and generates a new sub-neural At the same time, the control terminal retrains the sub-neural network whose structure has been updated, generates the weight parameters of the sub-neural network, and finally generates the address and access mode of the memory; and access mode to form a configuration file;

S5, iterates in this way, when the accuracy rate of the sub-neural network returned by the hardware acceleration terminal remains stable, the control neural network will no longer update the structure of the sub-neural network, and the structural parameters of the sub-neural network remain unchanged; Update, that is, search for the optimal structure of the sub-neural network on the hardware acceleration side.

This method can dynamically search for the optimal structure of the sub-neural network on the hardware acceleration side, and complete the acceleration of the inference process of the sub-neural network with the optimal structure.

in particular,

On the control side, the control neural network of the control side is a recurrent neural network, which can generate configuration files;

The recurrent neural network is a tree structure, as shown in Figure 3, and the specific calculation process is as follows:

A1) The input x _t and h _t-1 are calculated in two ways, and x _t and h _t-1 are multiplied all the way to generate the memory unit c _t of this level, where x _t is the inference accuracy and accuracy of the sub-neural network feedback The synthesized sequence is required, and h _t-1 is the sub-neural network structure parameter that previously controlled the output of the neural network;

A2) Use the activation function ReLU to activate the multiplication result of the previous step, and perform the ReLU(h _t-1 ×x _t ) operation;

A3) The other way firstly adds x _t and h _t-1 and performs tanh(h _t-1 +x _t ) operation with activation function tanh;

A4) The result of the previous step is added to the previous memory unit c _t-1 ;

A5) Use the ReLU activation function to activate again, and perform the ReLU(tanh(h _t-1 +x _t )+c _t-1 ) operation;

A6) After multiplying the two results, input the sigmoid function, and the final output result is:

h _t =sigmoid(ReLU(x _t ×h _t-1 )×ReLU(tanh(h _t-1 +x _t )+c _t-1 ))

h _t is the structural parameter representing the sub-neural network that controls the output of the neural network;

When the accuracy rate of the sub-neural network returned by the hardware acceleration terminal remains stable and unchanged, the control neural network does not update the structure of the sub-neural network, and the structural parameters of the sub-neural network remain unchanged;

On the hardware acceleration side;

The data input module is used to divide the data into n single-channel data blocks according to the number of input data channels, and the input data is a matrix converted from image data or signal data;

The configuration cache module is used to cache the configuration file generated on the control terminal; it can be read by the core computing module;

A convolution calculation unit performs one-layer convolution layer calculation; m convolution kernels in each convolution layer convolve the n data blocks with stride k in turn to generate m feature maps, and do this for l times, Where n is the number of input data channels, l, m, and k respectively represent the number of convolution calculation units, the number of convolution kernels and convolution stride in the convolution calculation unit, and the number of convolution layers and convolution layers in the configuration file. The number of kernels and the convolution step size correspond; as shown in Figure 4;

A pooling unit performs a layer of pooling layer calculation, accepts data from the convolutional computing unit and performs feature sampling, and so on o times, where o represents the number of pooling units, corresponding to the number of pooling layers in the configuration file ;

A linear computing unit performs a layer of fully connected layer calculation, accepts the data from the pooling unit, performs a=F(Wi×c+b) operation, and repeats this T times, the output is passed to the classification unit to obtain the classification result, and finally The classification result is output to the data output module; where Wi is the weight parameter, and T is the number of linear calculation units, which corresponds to the number of fully connected layers in the configuration file. c is the data output by the pooling unit, b is the bias in the sub-neural network, a is the output of the fully connected layer, and F(*) represents the activation function, generally a Sigomid or ReLU function; as shown in Figure 5;

The present invention uses the piecewise nonlinear approximation method to approximate the realization of the Sigmoid function. When x is in different intervals, different third-order polynomials y=Ax ³ +Bx ² +Cx+D are used to fit the Sigmoid function, wherein A , B, C, and D are the coefficients of fitting the Sigmoid function through a third-order polynomial; its implementation structure is shown in Figure 6. The process of using the fitted third-order polynomial to implement the Sigmoid function in the hardware acceleration side is as follows:

(1) There are different coefficients for x in different intervals; the coefficients A, B, C, D under each segment interval are pre-stored in the on-chip memory of the hardware acceleration end, and the corresponding coefficients A, B, and D are taken out by inputting x. C, D;

(2) Select the output through the selector. When the input x is a non-negative number, output the result of Ax ³ +Bx ² +Cx+D; if the input x is a negative number, output 1-(Ax ³ +Bx ² +Cx +D) result;

In the process of sub-neural network inference acceleration on the hardware acceleration side, the data input module and the configuration cache module need to store data through the hardware acceleration side on-chip and off-chip memory, so the hardware acceleration side needs to obtain the hardware acceleration side on-chip and on-chip. The address of the external memory; in the present invention, the address of the memory is generated by the control terminal, the access mode of the memory determined by the address of the memory is determined by the configuration information in the configuration file, and the memory access mode includes the main access mode, the data access mode and the weight. access mode, etc.;

Among them, the main access mode is used for data exchange between the on-chip memory and the off-chip memory, the data access mode is used to read data from the on-chip memory to the data input module and store the final classification result in the core computing module to the memory, and the weight The access mode is used to read weight parameter data from on-chip memory;

Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to examples, those of ordinary skill in the art should understand that the technical solutions of the present invention can be Modifications or equivalent substitutions without departing from the spirit and scope of the technical solutions of the present invention should be included in the scope of the claims of the present invention.

Claims (6)

1. a neural network dynamic acceleration platform, is characterized in that, comprises: control terminal and hardware acceleration terminal; The control terminal is used to train the control neural network. The control neural network updates the structure of the sub-neural network and generates the structural parameters of the sub-neural network according to the inference accuracy fed back by the sub-neural network and the preset accuracy requirements. The subsequent sub-neural network is retrained to generate weight parameters, and a configuration file is generated and sent to the hardware acceleration terminal. The configuration file contains the structural parameters and weight parameters of the sub-neural network; when the hardware acceleration terminal returns to the sub-neural network inference accuracy After the inference accuracy is stable, control The neural network no longer updates the sub-neural network, that is, the optimal structure of the sub-neural network on the hardware acceleration end is searched; The sub-neural network is a neural network that needs to perform inference acceleration at the hardware acceleration end; The hardware acceleration terminal is a sub-neural network hardware inference accelerator implemented by ASIC, which accepts the configuration file generated by the control terminal, completes the hardware implementation of the sub-neural network, and accelerates the inference process of the sub-neural network. The inference accuracy is fed back to the control terminal; finally, the hardware inference acceleration process of searching for the optimal structure of the sub-neural network and completing the sub-neural network with the optimal structure is achieved. 2. neural network dynamic acceleration platform as claimed in claim 1, is characterized in that, The structure of the sub-neural network includes the number of convolutional layers, the number of pooling layers, the number of fully connected layers, the structure of the convolutional layer, the structure of the pooling layer and the connection method of each layer; the convolutional layer structure includes the convolution kernel. Number, size, step size, the pooling layer structure includes pooling window size and step size; Parameters in the configuration file include: The number of convolutional layers, the number of pooling layers, the number of fully connected layers, and the connection method of each layer; The structure of the convolutional layer: the number of convolution kernels, the size, and the stride; The structure of the pooling layer: pooling window size, step size; The weight parameters of the retrained sub-neural network; Memory address, memory access mode; The hardware acceleration terminal includes a data input module, a configuration cache module, a core calculation module, and a data output module; the core calculation module includes a convolution calculation unit, a pooling unit, a linear calculation unit, and a classification unit; among which the convolution calculation unit, the pooling unit , The number of linear computing units corresponds to the number of convolutional layers, pooling layers, and fully connected layers in the configuration file respectively; the hardware structure of the convolutional computing unit is determined by the convolutional layer structure parameters in the configuration file. , the hardware structure of the pooling unit is determined by the pooling layer structure parameters in the configuration file; the hardware connection mode of each unit in the core computing module is determined by the connection mode of each layer in the configuration file; The data input module is used to divide the data into n single-channel data blocks according to the number of input data channels, the configuration cache module is used to cache the configuration file generated on the control terminal, and the core calculation module uses a convolution calculation unit. The m convolution kernels in the n data blocks sequentially convolve the n data blocks with the step size k to generate m feature maps, where m and k represent the number of convolution kernels and the convolution step size in the convolution calculation unit respectively, which are respectively related to the configuration. The number of convolution kernels in the file corresponds to the step size, and is transmitted to the pooling unit for feature sampling, and then the classification result is generated by the linear calculation unit and the classification unit, and the inference accuracy of the sub-neural network is calculated at the same time, and finally through the data output unit Output classification results and inference accuracy. 3. neural network dynamic acceleration platform as claimed in claim 1, is characterized in that, On the control side, the control neural network of the control side is a recurrent neural network, and the calculation process of the recurrent neural network is as follows: A1) The input x _t and h _t-1 are calculated in two ways, and x _t and h _t-1 are multiplied all the way to generate the memory unit c _t of this level, where x _t is the inference accuracy and accuracy of the sub-neural network feedback The synthesized sequence is required, and h _t-1 is the sub-neural network structure parameter that previously controlled the output of the neural network; A2) Use the activation function ReLU to activate the multiplication result of the previous step, and perform the ReLU (h _t-1 ×x _t ) operation; A3) The other way is to add x _t and h _t-1 and use the activation function tanh to perform tanh(h _t-1 +x _t ) operation; A4) The result of the previous step is added to the previous memory unit c _t-1 ; A5) Use the ReLU activation function to activate again, and perform the ReLU(tanh(h _t-1 +x _t )+c _t-1 ) operation; A6) After multiplying the two results, input the sigmoid function, and the final output result is: h _t = sigmoid(ReLU(x _t ×h _t-1 )×ReLU(tanh(h _t-1 +x _t )+c _t-1 )) h _t is the structural parameter representing the sub-neural network that controls the output of the neural network. 4. neural network dynamic acceleration platform as claimed in claim 2, is characterized in that, On the hardware acceleration side; The data input module is used to divide the data into n single-channel data blocks according to the number of input data channels; The configuration cache module is used to cache the configuration file generated on the control terminal; and is read by the core computing module; A convolution calculation unit performs one-layer convolution layer calculation; m convolution kernels in each convolution layer convolve the n data blocks with stride k in turn to generate m feature maps, and do this for l times, Where n is the number of input data channels, l, m, and k represent the number of convolution calculation units, respectively, the number of convolution kernels and convolution stride in the convolution calculation unit, which are respectively related to the number of convolution layers in the configuration file, The number of convolution kernels and the step size correspond; A pooling unit performs a layer of pooling layer calculation, accepts data from the convolutional computing unit and performs feature sampling, and so on o times, where o represents the number of pooling units, corresponding to the number of pooling layers in the configuration file ; A linear computing unit performs a layer of fully connected layer calculation, accepts the data from the pooling unit, performs a = F (Wi × c + b) operation, and repeats this for T times, the output is passed to the classification unit to obtain the classification result, and finally The classification result is output to the data output module; where Wi is the weight parameter, T is the number of linear computing units, corresponding to the number of fully connected layers in the configuration file, c is the data output by the pooling unit, and b is the sub-neural network The bias in , a is the output of the fully connected layer, and F(*) represents the activation function. 5. neural network dynamic acceleration platform as claimed in claim 4, is characterized in that, F(*) is the Sigmoid or ReLU function; on the hardware acceleration side, the piecewise nonlinear approximation method is used to approximate the Sigmoid function. When x is in different intervals, different third-order polynomials are used respectively y=Ax ³ + Bx ² + Cx+D performs fitting processing on the Sigmoid function, where A, B, C, and D are the coefficients of fitting the Sigmoid function through a third-order polynomial; the process of implementing the Sigmoid function in the hardware acceleration side using the fitted third-order polynomial is as follows: (1) There are different coefficients for x in different intervals; the coefficients A, B, C, and D in each subsection are pre-stored in the on-chip memory of the hardware acceleration side, and the corresponding coefficients A, B, and D are extracted by inputting x. C, D; (2) Select the output through the selector. When the input x is a non-negative number, the output is Ax ³ +Bx ² +Cx+D; if the input x is a negative number, the output is 1-(Ax ³ +Bx ² +Cx +D). 6. A neural network dynamic acceleration platform design method based on optimal structure search is characterized in that, comprising: S1, the control neural network on the control end of the neural network dynamic acceleration platform updates the structure of the sub-neural network and generates the sub-neural network structure parameters according to the inference accuracy fed back by the sub-neural network and the preset accuracy accuracy requirements. At the same time, the control terminal retrains the sub-neural network with the updated structure, generates the weight parameters of the sub-neural network, and finally generates the address and access mode of the memory; configuration file; S2, write the configuration file into the configuration cache module of the hardware acceleration side in the neural network dynamic acceleration platform, and update the volume in the core computing module according to the number of convolution layers, pooling layers, and fully connected layers in the configuration file. The number of product calculation units, pooling units, and linear calculation units, update the connection mode of each unit according to the parameters representing the connection mode of each layer in the configuration file, and update the convolution calculation unit, respectively, according to the structural parameters of the convolution layer and the pooling layer. The structure of the pooling unit; S3, read the input data through the data input unit, and perform the convolution operation on the input data through the convolution calculation unit, and then obtain the classification result through the linear operation unit, the pooling unit and the classification unit, and calculate the inference of the sub-neural network at the same time Accuracy, and finally output the classification results and inference accuracy through the data output unit; S4, the inference accuracy of the sub-neural network is fed back to the control terminal again, and the control neural network updates the sub-neural network again through the inference accuracy of the sub-neural network and the preset accuracy accuracy, and generates a new sub-neural At the same time, the control terminal retrains the sub-neural network whose structure has been updated, generates the weight parameters of the sub-neural network, and finally generates the address and access mode of the memory; and access mode to form a configuration file; S5, iterates in this way, when the accuracy rate of the sub-neural network returned by the hardware acceleration terminal remains stable, the control neural network will no longer update the structure of the sub-neural network, and the structural parameters of the sub-neural network remain unchanged; Update, that is, search for the optimal structure of the sub-neural network on the hardware acceleration side.