CN109933472A - Micro-processor architecture grade soft error neurological susceptibility appraisal procedure - Google Patents
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Abstract
The present invention is micro-processor architecture grade soft error neurological susceptibility appraisal procedure.The present invention carries out the assessment of soft error neurological susceptibility to the component of microprocessor in terms of storage unit and non-memory component two.For non-memory component, the method for using instruction analysis first classifies to ACE instruction and un-ACE instruction.During instruction analysis, logic masking instruction is divided into ACE instruction.But in logic masking instruction still include un-ACE, occur to have an impact program implementing result when soft error.Therefore the present invention is found out un-ACE more by logic analysis；For storage unit, equally first carries out instruction analysis and use logic correction module, find un-ACE more.Meanwhile life cycle analysis is carried out to storage unit, to carry out the assessment of soft error neurological susceptibility to storage unit.The present invention provides a kind of more accurate soft error neurological susceptibility appraisal procedure by using logic correction module.
Description
Technical field
The present invention relates to micro-processor architecture grade soft error neurological susceptibility appraisal procedure, belong to microprocessor analogue and micro-
Processor component soft error susceptibility analysis technical field.
Background technique
For a long time, the development of microprocessor is pushed away by integrated circuit technique and the dual of Computer Architecture technology
It is dynamic.As semiconductor fabrication process enters nanometer era, the following soft error caused by radiating and interfering reduces micro-
The reliability of processor seriously limits the development and application of Modern microprocessor.Therefore, at design initial stage to microprocessor
Component carries out the assessment of soft error neurological susceptibility, helps to provide design reference for designer.
Mukherjee et al. is proposed using architecture grade soft error susceptibility factors (AVF) description processor structure
Probability of malfunction.AVF is one of index most-often used in soft error susceptibility analysis at present.The method of AVF modeling is divided into three kinds:
It counts direct fault location (SFI), error propagation model (EPM) analysis and framework correctly execute ACE analysis.
SFI method precision is high, usually executes on RTL model.But since RTL model can not be obtained at design initial stage,
Architecture grade design initial stage acquisition AVF is not suitable for using SFI method.EPM analysis method is by tracking processor memory
The probability for generating and propagating with the mistake in assembly line is to obtain AVF.Li et al. people uses EPM and analyzes and propose SoftArch
Carry out the soft error behavior of research and analysis microprocessor architectural framework grade.But EPM analysis need accurate tracking mistake generate and
The behavior of propagation, and hardware configuration is more complicated, and analytic process is more complicated.ACE analysis method is to assume initially that the institute of structure
Position is all ACE, then as much as possible in structure during program executes to find un-ACE.It can using ACE analysis
To help designer to assess AVF during Earlier designs.
Traditional soft error neurological susceptibility appraisal procedure has problems in that:
Soft error neurological susceptibility assessment for microprocessor non-memory component, the appraisal procedure generally used are being instructed
Logic masking instruction is all directly divided into ACE instruction when analysis.However also include un-ACE in logic masking instruction,
Soft error occurs on these positions un-ACE to have an impact the implementing result of program, so soft error neurological susceptibility assessment knot
Fruit is not accurate enough.
Summary of the invention
The present invention is to solve the problems, such as existing, provides a kind of micro-processor architecture grade soft error neurological susceptibility and comments
Estimate method, the present invention provides following technical schemes:
A kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure, the method using parameter configuration module,
Test program module, instruction analysis module, logic correction module, life cycle analysis module and soft error susceptibility analysis mould
Block the described method comprises the following steps:
Step 1: choosing a simulator, initial configuration is carried out to simulator by parameter configuration module, to a spy
The function and performance for determining microprocessor are simulated；
Step 2: whether the analyzed component of judgement is instruction queue, register updating unit, load store queue, function
The non-memory component of energy unit；
Step 3: the program in simulator load test program module uses instruction analysis module pair in program operation
The instruction executed in the component analyzed is analyzed, and whether can generate shadow to the subsequent execution of program according to instruction execution result
It rings, instruction is divided into ACE instruction and is instructed with un-ACE, logic masking instruction is identified by logic judgment, in order to guarantee to instruct
Logic masking instruction is directly classified as ACE instruction by the accuracy of classification；
Step 4: the position un-ACE in logic masking instruction is filtered out using logic correction module, it is susceptible to improve soft error
Property assessment accuracy；
Step 5: the architecture grade soft error neurological susceptibility of institute's analysis component is calculated using soft error susceptibility analysis module
Factor values obtain microprocessor by ACE in institute's analysis component in calculating test program module operational process proportions
Architecture grade soft error susceptibility factors value judges institute according to micro-processor architecture grade soft error susceptibility factors value
The probability that analysis component is influenced by soft error；
Step 6: terminating the assessment of micro-processor architecture grade soft error neurological susceptibility, susceptible according to obtained soft error
Property analysis as a result, to microprocessor Design teacher provide reference.
Preferably, it when the component of the analysis is non-memory component, carries out step 3 to step 5 and operates.
Preferably, when the component of the analysis is storage unit, using life cycle analysis module and instruction analysis
Life cycle is divided into ACE sections, un- according to the different operation on storage position by module binding analysis, life cycle analysis module
ACE sections and unknown number unknown sections, then carry out step 3 to step 5 and operate.
Preferably, micro-processor architecture grade soft error susceptibility factors value AVF passes through following formula meter in the step 5
It calculates:
Wherein, AVF is micro-processor architecture grade soft error susceptibility factors value, NbitsFor the total bit of component,
NACEi_bitsThe ACE digit for being component in period i, NACEi_lmispSpecific logical masking instruction position is assumed in period i for component
ACE digit, ACEjTotal clock periodicity of ACE state, ACE are in program process for position jj_lmispExist for position j
Assume that specific logical masking instruction is in the clock periodicity of ACE state, total_exec_cycles table in program process
Total periodicity that the program shown executes.
Preferably, the non-memory component includes instruction queue, memory updating unit, load store queue and function list
Member.
Preferably, operation includes " idle ", " fill ", " read ", " write " and " evict " on the storage position.
Preferably, the microprocessor architecture feature according to simulator simulation is different, is carried out according to different pipeline organizations micro-
The soft error susceptibility analysis of processor.
Preferably, the un-ACE in the logic masking instruction includes the instruction for needing two source registers, needs one
Source deposit and the instruction of an immediate need EOR and the EORS instruction of two source registers and need a source register
With EOR and the EORS instruction of an immediate.
Preferably, according to micro-processor architecture grade soft error susceptibility factors value AVF, discriminatory analysis component is by soft error
Accidentally influence degree.
Preferably, when there are specific logical masking instruction, introducing member assumes specific logical masking instruction position in period i
ACE digit and position j assume that specific logical masking instruction is in the clock periodicity of ACE state in program process.
The invention has the following advantages:
The present invention carries out soft error neurological susceptibility to the component of microprocessor in terms of storage unit and non-memory component two
Assessment.For non-memory component, the method for using instruction analysis first classifies to ACE instruction and un-ACE instruction.Referring to
During enabling analysis, logic masking instruction is typically directly divided into ACE instruction.But still include in logic masking instruction
Un-ACE, occur to have an impact program implementing result when soft error.Therefore the present invention is found out by logic analysis
It is un-ACE more；For storage unit, equally first carries out instruction analysis and use logic correction module, find more
Un-ACE.Life cycle analysis is carried out to storage unit simultaneously, to carry out the assessment of soft error neurological susceptibility to storage unit.It is logical
It crosses ACE analysis method and carries out instruction analysis, after instruction is divided into ACE instruction and un-ACE instruction, further corrected by logic
Module is found out un-ACE more from ACE instruction, joined logic correction module after instruction analysis module, raising is soft
The accuracy of mistake susceptibility analysis.If soft error susceptibility factors are bigger simultaneously, the component is easier by soft error
Influence.
Detailed description of the invention
Fig. 1 is microprocessor soft error neurological susceptibility appraisal framework figure.
Fig. 2 is microprocessor soft error susceptibility analysis flow chart.
Fig. 3 is ACE instruction and un-ACE instruction classification figure.
Specific embodiment
Below in conjunction with specific embodiment, describe the invention in detail.
Specific embodiment one:
According to Fig. 1 and Fig. 2, the present invention provides a kind of micro-processor architecture grade soft error neurological susceptibility assessment side
Method, the method is using parameter configuration module, test program module, instruction analysis module, logic correction module, life cycle point
Module and soft error susceptibility analysis module are analysed, the described method comprises the following steps:
Step 1: choosing a simulator, initial configuration is carried out to simulator by parameter configuration module, to a spy
The function and performance for determining microprocessor are simulated；
Step 2: whether the analyzed component of judgement is instruction queue, register updating unit, load store queue, function
The non-memory component of energy unit；
Step 3: the program in simulator load test program module uses instruction analysis module pair in program operation
The instruction executed in the component analyzed is analyzed, whether the subsequent execution of program can be generated according to instruction execution result
It influences, instruction is divided into ACE instruction and is instructed with un-ACE, wherein logic masking instruction, general feelings are identified by logic judgment
Under condition, in order to guarantee the accuracy of instruction classification, logic masking instruction is directly classified as ACE instruction；
Step 4: the position un-ACE in logic masking instruction is filtered out using logic correction module, it is susceptible to improve soft error
Property assessment accuracy；
Step 5: the architecture grade soft error neurological susceptibility of institute's analysis component is calculated using soft error susceptibility analysis module
Factor values obtain microprocessor by ACE in institute's analysis component in calculating test program module operational process proportions
Architecture grade soft error susceptibility factors value judges institute according to micro-processor architecture grade soft error susceptibility factors value
The probability that analysis component is influenced by soft error；
Step 6: terminating the assessment of micro-processor architecture grade soft error neurological susceptibility, susceptible according to obtained soft error
Property analysis as a result, to microprocessor Design teacher provide reference.
Specific embodiment two:
According to the difference of the microprocessor architecture feature of simulator simulation, this method can apply to different pipeline organizations
In the soft error susceptibility analysis of microprocessor.
Specific embodiment three:
Soft error susceptibility analysis process of the invention the following steps are included:
Simulator initial configuration: step 1 selects a simulator, as being with ARM instruction set in SimpleScalar
The simplesim-ARM simulator of target carries out initial configuration to simulator configuration file, simulates the complete of microprocessor
Function.The instruction set wherein used is ARMv7.
Step 2, if by non-memory component: whether the component that judgement is analyzed is instruction queue, register update list
The non-memory components such as member, load store queue, functional unit, jump to step 3, otherwise jump to step 6；
Step 3, instruction analysis module: ACE refer to being component in program operation process so that implementation procedure does not malfunction
On must assure that correct position.Corresponding, un-ACE refer to that soft error occurs on the position, will not be to program after
Continuous execution impacts.Whether influence the output of program by the result that analysis instruction executes, by instruction be divided into ACE instruction with
Un-ACE instruction.Main un-ACE instruction is NOP and dynamically dead instructions etc..It is in order to guarantee correctness, other instructions are all false
It is set as ACE instruction.ACE instruction and un-ACE instruction classification result are as shown in Figure 3.Wherein logic masking instruction is also directly classified
It is instructed in ACE.
Step 4, logic correction module: as step 3 is mentioned, in order to guarantee the accuracy of soft error susceptibility analysis,
Logic masking instruction is directly all generally classified as ACE instruction.But un-ACE may also be contained in logic masking instruction, the position
Upper generation soft error will not have an impact the output of program.Logic correction module is intended to find out the un- in logic masking instruction
ACE, improve the accuracy of soft error neurological susceptibility assessment.The position un-ACE in logic correction module in logic masking instruction includes
Following four situation:
(1) instruction for needing two source registers, such as multiplying order A*B；If one of source register is by soft error
It misleads and causes bit flipping, but the value that another source register position corresponds to position is zero, then calculated result will not change because of bit flipping
Become；Therefore, the position that bit flipping occurs is logically shielded, and referred to as un-ACE；
(2) instruction of a source register and an immediate, such as A*IMM are needed；If soft error occurs to deposit in source
Device leads to bit flipping, but immediate is zero, and calculated result will not equally change because of soft error；Therefore on the source register
Position be un-ACE；
(3) EOR and the EORS instruction of two source registers are needed；When the value of two source registers is identical, according to
Its calculated result of logical operation is zero, therefore the position on two source registers is un-ACE；(4) a source deposit is needed
Device and the EOR and EORS of an immediate instruction；If the value of source register is equal with immediate, which is
Un-ACE；
The specific logical masking instruction found out from ARMv7 in this example is specifically as shown in table 1.
Table 1: specific logical masking instruction
Step 5, soft error susceptibility analysis: the micro-processor architecture grade soft error susceptibility factors of calculating unit
(AVF) value, the calculation formula of AVF are as follows:
Wherein Nbits is the total bit of component, NACEi_bitsThe ACE digit for being component in period i, NACEi_lmispFor portion
Part assumes the ACE digit of specific logical masking instruction position, ACE in period ijACE shape is in program process for position j
Total clock periodicity of state, ACEj_lmispAssume that specific logical masking instruction is in ACE shape in program process for position j
The clock periodicity of state, total periodicity that the program that total_exec_cycles is indicated executes.NACEi_lmispIt is more, AVF assessment
It is worth higher, represents that component is easier to be influenced by soft error；On the contrary, NACEi_lmispFewer, AVF assessed value is lower, and component is more not
It is easy to be affected by soft errors；
Step 6, life cycle analysis module: if the component of analysis is storage unit, in order to guarantee that its soft error is susceptible
Property analysis accuracy, need to use the soft error susceptibility analysis side that combines with instruction analysis of life cycle analysis to component
Method；Region division between operation can be ACE, un-ACE and unknown according to the different operation on storage position by life cycle analysis
Unknown sections of position, the operation for storing position includes " idle ", " fill ", " read ", " write " and " evict "；Step 6 terminates
After jump to step 3；
Life cycle can be further divided into ACE and un-ACE by life cycle analysis in step 6.For example,
" idle ", " read-to-write " and " write-to-read " belong to the part un-ACE, and " fill-to-read " and
" write-to-read " is the part ACE.In addition, read-write operation repeatedly causes the utilization rate of storage organization very high, therefore right
Mostly than more conservative when the AVF of storage organization is estimated.In order to enable AVF estimation is practical, which further analysis had
A little parts ACE can be converted the part un-ACE.Usual then two kinds of read operation behind one write operation.One is
The read operation of ACE instruction, is referred to as ACE Read.Another kind is the read operation of dynamically dead instructions or special instruction, by it
Referred to as un-ACE Read.Un-ACE Read appears in after write operation that there are three types of different situations:
(1) un-ACE Read is followed directly after after writing；
(2) before the un-ACE Read after write operation there are one or multiple read operations；
(3) it is operated after un-ACE Read without others ACE Read.
The part ACE in first two situation will not be converted into the part un-ACE, because after appearing in un-ACE Read
ACE Read is easy to be affected by soft errors.From (3) it is found that using mixing AVF evaluation method because un-ACE Read it
It is operated afterwards without ACE Read, the part un-ACE can be classified as.Step 3 is jumped to after step 6, is carried out subsequent
Analysis.
Step 7 terminates assessment.
Compared to existing method, the present invention carries out instruction analysis by ACE analysis method, by instruction be divided into ACE instruction and
After un-ACE instruction, further found out from ACE instruction by logic correction module un-ACE more.It improves to micro- place
Manage the accuracy of device component soft error neurological susceptibility assessment.
The above is only the preferred embodiment of micro-processor architecture grade soft error neurological susceptibility appraisal procedure, micro- place
The protection scope of reason body architecture grade soft error neurological susceptibility appraisal procedure is not limited merely to above-described embodiment, all to belong to thinking
Under technical solution all belong to the scope of protection of the present invention.It should be pointed out that those of ordinary skill in the art, not
Several improvements and changes being detached under the premise of the principle of the invention, such modifications and variations also should be regarded as protection scope of the present invention.
Claims (10)
1. a kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure, it is characterized in that: the method is matched using parameter
Set module, test program module, instruction analysis module, logic correction module, life cycle analysis module and soft error neurological susceptibility
Analysis module the described method comprises the following steps:
Step 1: choosing a simulator, initial configuration is carried out to simulator by parameter configuration module, to a specific micro-
The function of processor is simulated with performance；
Step 2: whether the analyzed component of judgement is instruction queue, register updating unit, load store queue, function list
The non-memory component of member；
Step 3: the program in simulator load test program module, in program operation using instruction analysis module to dividing
Whether the instruction executed in the component of analysis is analyzed, had an impact to the subsequent execution of program according to the result of instruction execution,
Instruction is divided into ACE instruction to instruct with un-ACE, logic masking instruction is identified by logic judgment, in order to guarantee instruction classification
Accuracy, directly by logic masking instruction be classified as ACE instruction；
Step 4: filtering out the position un-ACE in logic masking instruction using logic correction module, improves soft error neurological susceptibility and comments
The accuracy estimated；
Step 5: the architecture grade soft error susceptibility factors of institute's analysis component are calculated using soft error susceptibility analysis module
Value obtains microprocessor system by ACE in institute's analysis component in calculating test program module operational process proportions
Structural level soft error susceptibility factors value judges to be analyzed according to micro-processor architecture grade soft error susceptibility factors value
The probability that component is influenced by soft error；
Step 6: terminate the assessment of micro-processor architecture grade soft error neurological susceptibility, according to obtained soft error neurological susceptibility point
Analysis as a result, to microprocessor Design teacher provide reference.
2. a kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure according to claim 1, it is characterized in that:
When the component of the analysis is non-memory component, carries out step 3 to step 5 and operate.
3. a kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure according to claim 1, it is characterized in that:
It is raw using life cycle analysis module and instruction analysis module binding analysis when the component of the analysis is storage unit
Life cycle is divided into ACE sections, un-ACE sections and unknown number by the different operation stored on position by life cycle analysis module
Unknown sections, then carry out step 3 to step 5 and operate.
4. a kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure according to claim 1, it is characterized in that:
Micro-processor architecture grade soft error susceptibility factors value AVF is calculate by the following formula in the step 5:
Wherein, AVF is micro-processor architecture grade soft error susceptibility factors value, NbitsFor the total bit of component,
The ACE digit for being component in period i,The position ACE of specific logical masking instruction position is assumed in period i for component
Number, ACEjTotal clock periodicity of ACE state, ACE are in program process for position jj_lmispIt is held for position j in program
Assume that specific logical masking instruction is in the clock periodicity of ACE state, the journey that total_exec_cycles is indicated during row
Total periodicity that sequence executes.
5. a kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure according to claim 1, it is characterized in that:
The non-memory component includes instruction queue, memory updating unit, load store queue and functional unit.
6. a kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure according to claim 1, it is characterized in that:
Operation includes " idle ", " fill ", " read ", " write " and " evict " on the storage position.
7. a kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure according to claim 1, it is characterized in that:
Microprocessor architecture feature according to simulator simulation is different, and the soft error for carrying out microprocessor according to different pipeline organizations is easy
Perceptual analysis.
8. a kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure according to claim 1, it is characterized in that:
Un-ACE in the logic masking instruction includes that the instruction for needing two source registers, one source deposit of needs and one are vertical
I.e. several instruction needs EOR and the EORS instruction of two source registers and needs a source register and immediate
EOR and EORS instruction.
9. a kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure according to claim 1, it is characterized in that:
According to micro-processor architecture grade soft error susceptibility factors value AVF, discriminatory analysis component is by soft error influence degree.
10. a kind of micro-processor architecture grade soft error neurological susceptibility appraisal procedure according to claim 1, feature
Be: when there are specific logical masking instruction, introducing member assume in period i specific logical masking instruction position ACE digit and
Position j assumes that specific logical masking instruction is in the clock periodicity of ACE state in program process.
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Application publication date: 20190625 |